| 36,14 → 36,13 |
|---|
| #define KERN_mips32_CP0_H_ |
| |
| #include <arch/types.h> |
| #include <arch/mm/tlb.h> |
| |
| #define cp0_status_ie_enabled_bit (1<<0) |
| #define cp0_status_exl_exception_bit (1<<1) |
| #define cp0_status_erl_error_bit (1<<2) |
| #define cp0_status_um_bit (1<<4) |
| #define cp0_status_bev_bootstrap_bit (1<<22) |
| #define cp0_status_fpu_bit (1<<29) |
| #define cp0_status_ie_enabled_bit (1 << 0) |
| #define cp0_status_exl_exception_bit (1 << 1) |
| #define cp0_status_erl_error_bit (1 << 2) |
| #define cp0_status_um_bit (1 << 4) |
| #define cp0_status_bev_bootstrap_bit (1 << 22) |
| #define cp0_status_fpu_bit (1 << 29) |
| |
| #define cp0_status_im_shift 8 |
| #define cp0_status_im_mask 0xff00 |
| 60,8 → 59,8 |
|---|
| |
| #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) |
| #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) |
| #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it)))) |
| #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it)))) |
| #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1 << (cp0_status_im_shift + (it)))) |
| #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1 << (cp0_status_im_shift + (it)))) |
| |
| #define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \ |
| { \ |