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  → /trunk/kernel/arch/ia32/ @ 3132

  → /trunk/kernel/arch/ia32/ @ 3133

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Ignore whitespace Rev 3132 → Rev 3133

/trunk/kernel/arch/ia32/include/barrier.h
84,6 → 84,14
# endif
#endif
/*
* On ia32, the hardware takes care about instruction and data cache coherence,
* even on SMP systems. We issue a write barrier to be sure that writes
* queueing in the store buffer drain to the memory (even though it would be
* sufficient for them to drain to the D-cache).
*/
#define smc_coherence(a) write_barrier()
#endif
/** @}