| /trunk/kernel/arch/ia64/src/fpu_context.c |
|---|
| 149,8 → 149,10 |
| "stf.spill [%7] = f127, 0x80\n;;" |
| : |
| : "r" (&((fctx->fr)[0])), "r" (&((fctx->fr)[1])), "r" (&((fctx->fr)[2])), "r" (&((fctx->fr)[3])), |
| "r" (&((fctx->fr)[4])), "r" (&((fctx->fr)[5])), "r" (&((fctx->fr)[6])), "r" (&((fctx->fr)[7])) |
| : "r" (&((fctx->fr)[0])), "r" (&((fctx->fr)[1])), |
| "r" (&((fctx->fr)[2])), "r" (&((fctx->fr)[3])), |
| "r" (&((fctx->fr)[4])), "r" (&((fctx->fr)[5])), |
| "r" (&((fctx->fr)[6])), "r" (&((fctx->fr)[7])) |
| ); |
| } |
| 267,14 → 269,16 |
| "ldf.fill f127 = [%7], 0x80\n;;" |
| : |
| : "r" (&((fctx->fr)[0])), "r" (&((fctx->fr)[1])), "r" (&((fctx->fr)[2])), "r" (&((fctx->fr)[3])), |
| "r" (&((fctx->fr)[4])), "r" (&((fctx->fr)[5])), "r" (&((fctx->fr)[6])), "r" (&((fctx->fr)[7])) |
| : "r" (&((fctx->fr)[0])), "r" (&((fctx->fr)[1])), |
| "r" (&((fctx->fr)[2])), "r" (&((fctx->fr)[3])), |
| "r" (&((fctx->fr)[4])), "r" (&((fctx->fr)[5])), |
| "r" (&((fctx->fr)[6])), "r" (&((fctx->fr)[7])) |
| ); |
| } |
| void fpu_enable(void) |
| { |
| uint64_t a = 0 ; |
| uint64_t a = 0; |
| asm volatile ( |
| "rsm %0 ;;" |
| /trunk/kernel/arch/ia64/src/ia64.c |
|---|
| 62,13 → 62,13 |
| #include <print.h> |
| #include <sysinfo/sysinfo.h> |
| /*NS16550 as a COM 1*/ |
| #define NS16550_IRQ (4+LEGACY_INTERRUPT_BASE) |
| #define NS16550_PORT 0x3f8 |
| /* NS16550 as a COM 1 */ |
| #define NS16550_IRQ (4 + LEGACY_INTERRUPT_BASE) |
| #define NS16550_PORT 0x3f8 |
| bootinfo_t *bootinfo; |
| static uint64_t iosapic_base=0xfec00000; |
| static uint64_t iosapic_base = 0xfec00000; |
| void arch_pre_main(void) |
| { |
| 79,7 → 79,9 |
| init.cnt = bootinfo->taskmap.count; |
| for (i = 0; i < init.cnt; i++) { |
| init.tasks[i].addr = ((unsigned long) bootinfo->taskmap.tasks[i].addr) | VRN_MASK; |
| init.tasks[i].addr = |
| ((unsigned long) bootinfo->taskmap.tasks[i].addr) | |
| VRN_MASK; |
| init.tasks[i].size = bootinfo->taskmap.tasks[i].size; |
| } |
| } |
| 86,7 → 88,10 |
| void arch_pre_mm_init(void) |
| { |
| /* Set Interruption Vector Address (i.e. location of interruption vector table). */ |
| /* |
| * Set Interruption Vector Address (i.e. location of interruption vector |
| * table). |
| */ |
| iva_write((uintptr_t) &ivt); |
| srlz_d(); |
| 95,25 → 100,25 |
| static void iosapic_init(void) |
| { |
| uint64_t IOSAPIC = PA2KA((unative_t)(iosapic_base))|FW_OFFSET; |
| uint64_t IOSAPIC = PA2KA((unative_t)(iosapic_base)) | FW_OFFSET; |
| int i; |
| int myid,myeid; |
| myid=ia64_get_cpu_id(); |
| myeid=ia64_get_cpu_eid(); |
| myid = ia64_get_cpu_id(); |
| myeid = ia64_get_cpu_eid(); |
| for(i=0;i<16;i++) |
| { |
| if(i==2) continue; //Disable Cascade interrupt |
| ((uint32_t*)(IOSAPIC+0x00))[0]=0x10+2*i; |
| for (i = 0; i < 16; i++) { |
| if (i == 2) |
| continue; /* Disable Cascade interrupt */ |
| ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i; |
| srlz_d(); |
| ((uint32_t*)(IOSAPIC+0x10))[0]=LEGACY_INTERRUPT_BASE+i; |
| ((uint32_t *)(IOSAPIC + 0x10))[0] = LEGACY_INTERRUPT_BASE + i; |
| srlz_d(); |
| ((uint32_t*)(IOSAPIC+0x00))[0]=0x10+2*i+1; |
| ((uint32_t *)(IOSAPIC + 0x00))[0] = 0x10 + 2 * i + 1; |
| srlz_d(); |
| ((uint32_t*)(IOSAPIC+0x10))[0]=myid<<(56-32) | myeid<<(48-32); |
| ((uint32_t *)(IOSAPIC + 0x10))[0] = myid << (56 - 32) | |
| myeid << (48 - 32); |
| srlz_d(); |
| } |
| 122,10 → 127,8 |
| void arch_post_mm_init(void) |
| { |
| if(config.cpu_active==1) |
| { |
| if (config.cpu_active == 1) { |
| iosapic_init(); |
| irq_init(INR_COUNT, INR_COUNT); |
| #ifdef SKI |
| ski_init_console(); |
| 166,57 → 169,38 |
| } |
| #endif |
| void end_of_irq_void(void *cir_arg __attribute__((unused)),inr_t inr __attribute__((unused))); |
| void end_of_irq_void(void *cir_arg __attribute__((unused)),inr_t inr __attribute__((unused))) |
| { |
| return; |
| } |
| void arch_post_smp_init(void) |
| { |
| thread_t *t; |
| { |
| /* |
| * Create thread that polls keyboard. |
| */ |
| /* |
| * Create thread that polls keyboard. |
| */ |
| #ifdef SKI |
| thread_t *t; |
| t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll", true); |
| if (!t) |
| panic("cannot create kkbdpoll\n"); |
| thread_ready(t); |
| t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll", true); |
| if (!t) |
| panic("cannot create kkbdpoll\n"); |
| thread_ready(t); |
| #endif |
| #ifdef I460GX |
| devno_t kbd = device_assign_devno(); |
| /* keyboard controller */ |
| devno_t kbd = device_assign_devno(); |
| #ifdef CONFIG_NS16550 |
| ns16550_init(kbd, NS16550_PORT, NS16550_IRQ,end_of_irq_void,NULL); // as a COM 1 |
| ns16550_init(kbd, NS16550_PORT, NS16550_IRQ, NULL, NULL); |
| #else |
| devno_t mouse = device_assign_devno(); |
| i8042_init(kbd, IRQ_KBD, mouse, IRQ_MOUSE); |
| devno_t mouse = device_assign_devno(); |
| i8042_init(kbd, IRQ_KBD, mouse, IRQ_MOUSE); |
| #endif |
| thread_t *t; |
| t = thread_create(i8042_kkbdpoll, NULL, TASK, 0, "kkbdpoll", true); |
| if (!t) |
| panic("cannot create kkbdpoll\n"); |
| thread_ready(t); |
| t = thread_create(i8042_kkbdpoll, NULL, TASK, 0, "kkbdpoll", true); |
| if (!t) |
| panic("cannot create kkbdpoll\n"); |
| thread_ready(t); |
| #endif |
| } |
| sysinfo_set_item_val("ia64_iospace", NULL, true); |
| sysinfo_set_item_val("ia64_iospace.address", NULL, true); |
| sysinfo_set_item_val("ia64_iospace.address.virtual", NULL, IO_OFFSET); |
| } |
| 228,26 → 212,25 |
| psr.value = psr_read(); |
| psr.cpl = PL_USER; |
| psr.i = true; /* start with interrupts enabled */ |
| psr.i = true; /* start with interrupts enabled */ |
| psr.ic = true; |
| psr.ri = 0; /* start with instruction #0 */ |
| psr.bn = 1; /* start in bank 0 */ |
| psr.ri = 0; /* start with instruction #0 */ |
| psr.bn = 1; /* start in bank 0 */ |
| asm volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value)); |
| rsc.loadrs = 0; |
| rsc.be = false; |
| rsc.pl = PL_USER; |
| rsc.mode = 3; /* eager mode */ |
| rsc.mode = 3; /* eager mode */ |
| switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry, |
| ((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT), |
| ((uintptr_t) kernel_uarg->uspace_stack)+PAGE_SIZE, |
| (uintptr_t) kernel_uarg->uspace_uarg, |
| psr.value, rsc.value); |
| ((uintptr_t) kernel_uarg->uspace_stack) + PAGE_SIZE - |
| ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT), |
| ((uintptr_t) kernel_uarg->uspace_stack) + PAGE_SIZE, |
| (uintptr_t) kernel_uarg->uspace_uarg, psr.value, rsc.value); |
| while (1) { |
| while (1) |
| ; |
| } |
| } |
| /** Set thread-local-storage pointer. |
| 267,13 → 250,14 |
| #ifdef SKI |
| ski_kbd_grab(); |
| #else |
| #ifdef CONFIG_NS16550 |
| ns16550_grab(); |
| #else |
| i8042_grab(); |
| #endif |
| #ifdef CONFIG_NS16550 |
| ns16550_grab(); |
| #else |
| i8042_grab(); |
| #endif |
| #endif |
| } |
| /** Return console to userspace |
| * |
| */ |
| 282,19 → 266,19 |
| #ifdef SKI |
| ski_kbd_release(); |
| #else |
| #ifdef CONFIG_NS16550 |
| ns16550_release(); |
| #else |
| i8042_release(); |
| #endif |
| #ifdef CONFIG_NS16550 |
| ns16550_release(); |
| #else |
| i8042_release(); |
| #endif |
| #endif |
| } |
| void arch_reboot(void) |
| { |
| outb(0x64,0xfe); |
| while (1); |
| outb(0x64, 0xfe); |
| while (1) |
| ; |
| } |
| /** @} |
| /trunk/kernel/arch/ia64/src/ski/ski.c |
|---|
| 118,7 → 118,7 |
| while(!(ch = ski_getchar())) |
| ; |
| if(ch == '\r') |
| if (ch == '\r') |
| ch = '\n'; |
| return (char) ch; |
| } |
| 143,7 → 143,8 |
| if(ch == '\r') |
| ch = '\n'; |
| if (ch) { |
| if (ski_kbd_irq.notif_cfg.notify && ski_kbd_irq.notif_cfg.answerbox) { |
| if (ski_kbd_irq.notif_cfg.notify && |
| ski_kbd_irq.notif_cfg.answerbox) { |
| chardev_push_character(&ski_uconsole, ch); |
| ipc_irq_send_notif(&ski_kbd_irq); |
| } else { |
| 156,7 → 157,8 |
| } |
| if (last) { |
| if (ski_kbd_irq.notif_cfg.notify && ski_kbd_irq.notif_cfg.answerbox) { |
| if (ski_kbd_irq.notif_cfg.notify && |
| ski_kbd_irq.notif_cfg.answerbox) { |
| chardev_push_character(&ski_uconsole, 0); |
| ipc_irq_send_notif(&ski_kbd_irq); |
| } |
| /trunk/kernel/arch/ia64/src/cpu/cpu.c |
|---|
| 70,8 → 70,8 |
| } |
| printf("cpu%d: %s (%s), archrev=%d, model=%d, revision=%d\n", CPU->id, |
| family_str, vendor, CPU->arch.cpuid3.archrev, CPU->arch.cpuid3.model, |
| CPU->arch.cpuid3.revision); |
| family_str, vendor, CPU->arch.cpuid3.archrev, |
| CPU->arch.cpuid3.model, CPU->arch.cpuid3.revision); |
| } |
| /** @} |
| /trunk/kernel/arch/ia64/src/start.S |
|---|
| 32,17 → 32,15 |
| #include <mm/asid.h> |
| #define RR_MASK (0xFFFFFFFF00000002) |
| #define RID_SHIFT 8 |
| #define PS_SHIFT 2 |
| #define RID_SHIFT 8 |
| #define PS_SHIFT 2 |
| #define KERNEL_TRANSLATION_I 0x0010000000000661 |
| #define KERNEL_TRANSLATION_D 0x0010000000000661 |
| #define KERNEL_TRANSLATION_VIO 0x0010000000000671 |
| #define KERNEL_TRANSLATION_IO 0x00100FFFFC000671 |
| #define KERNEL_TRANSLATION_FW 0x00100000F0000671 |
| #define KERNEL_TRANSLATION_I 0x0010000000000661 |
| #define KERNEL_TRANSLATION_D 0x0010000000000661 |
| #define KERNEL_TRANSLATION_VIO 0x0010000000000671 |
| #define KERNEL_TRANSLATION_IO 0x00100FFFFC000671 |
| #define KERNEL_TRANSLATION_FW 0x00100000F0000671 |
| .section K_TEXT_START, "ax" |
| .global kernel_image_start |
| 51,18 → 49,17 |
| kernel_image_start: |
| .auto |
| #identifi self(CPU) in OS structures by ID / EID |
| mov r9=cr64 |
| mov r10=1 |
| movl r12=0xffffffff |
| movl r8=cpu_by_id_eid_list |
| and r8=r8,r12 |
| shr r9=r9,16 |
| add r8=r8,r9 |
| st1 [r8]=r10 |
| # Identify self(CPU) in OS structures by ID / EID |
| mov r9 = cr64 |
| mov r10 = 1 |
| movl r12 = 0xffffffff |
| movl r8 = cpu_by_id_eid_list |
| and r8 = r8, r12 |
| shr r9 = r9, 16 |
| add r8 = r8, r9 |
| st1 [r8] = r10 |
| mov psr.l = r0 |
| srlz.i |
| srlz.d |
| 69,39 → 66,29 |
| # Fill TR.i and TR.d using Region Register #VRN_KERNEL |
| movl r8 = (VRN_KERNEL << VRN_SHIFT) |
| mov r9 = rr[r8] |
| movl r10 = (RR_MASK) |
| and r9 = r10, r9 |
| movl r10 = ((RID_KERNEL << RID_SHIFT) | (KERNEL_PAGE_WIDTH << PS_SHIFT)) |
| or r9 = r10, r9 |
| mov rr[r8] = r9 |
| movl r8 = (VRN_KERNEL << VRN_SHIFT) |
| mov cr.ifa = r8 |
| mov r11 = cr.itir ;; |
| movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);; |
| or r10 =r10 , r11 ;; |
| or r10 = r10, r11 ;; |
| mov cr.itir = r10;; |
| movl r10 = (KERNEL_TRANSLATION_I) |
| itr.i itr[r0] = r10 |
| movl r10 = (KERNEL_TRANSLATION_D) |
| itr.d dtr[r0] = r10 |
| movl r7 = 1 |
| movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET |
| mov cr.ifa = r8 |
| 108,15 → 95,13 |
| movl r10 = (KERNEL_TRANSLATION_VIO) |
| itr.d dtr[r7] = r10 |
| mov r11 = cr.itir ;; |
| movl r10 = ~0xfc;; |
| and r10 =r10 , r11 ;; |
| and r10 = r10, r11 ;; |
| movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);; |
| or r10 =r10 , r11 ;; |
| or r10 = r10, r11 ;; |
| mov cr.itir = r10;; |
| movl r7 = 2 |
| movl r8 = (VRN_KERNEL << VRN_SHIFT) | IO_OFFSET |
| mov cr.ifa = r8 |
| 123,16 → 108,15 |
| movl r10 = (KERNEL_TRANSLATION_IO) |
| itr.d dtr[r7] = r10 |
| # Setup mapping for fimware arrea (also SAPIC) |
| #setup mapping for fimware arrea (also SAPIC) |
| mov r11 = cr.itir ;; |
| movl r10 = ~0xfc;; |
| and r10 =r10 , r11 ;; |
| and r10 = r10, r11 ;; |
| movl r11 = (FW_PAGE_WIDTH << PS_SHIFT);; |
| or r10 =r10 , r11 ;; |
| or r10 = r10, r11 ;; |
| mov cr.itir = r10;; |
| movl r7 = 3 |
| movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET |
| mov cr.ifa = r8 |
| 139,13 → 123,11 |
| movl r10 = (KERNEL_TRANSLATION_FW) |
| itr.d dtr[r7] = r10 |
| # Initialize PSR |
| # initialize PSR |
| movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */ |
| mov r9 = psr |
| or r10 = r10, r9 |
| mov cr.ipsr = r10 |
| mov cr.ifs = r0 |
| 155,11 → 137,13 |
| srlz.i |
| .explicit |
| /* |
| * Return From Interupt is the only the way to fill upper half word of PSR. |
| */ |
| rfi;; |
| .global paging_start |
| paging_start: |
| 167,27 → 151,25 |
| * Now we are paging. |
| */ |
| # switch to register bank 1 |
| # Switch to register bank 1 |
| bsw.1 |
| #Am'I BSP or AP |
| movl r20=bsp_started;; |
| ld8 r20=[r20];; |
| cmp.eq p3,p2=r20,r0;; |
| # Am I BSP or AP? |
| movl r20 = bsp_started;; |
| ld8 r20 = [r20];; |
| cmp.eq p3, p2 = r20, r0;; |
| # initialize register stack |
| # Initialize register stack |
| mov ar.rsc = r0 |
| movl r8 = (VRN_KERNEL << VRN_SHIFT) ;; |
| mov ar.bspstore = r8 |
| loadrs |
| # initialize memory stack to some sane value |
| # Initialize memory stack to some sane value |
| movl r12 = stack0 ;; |
| add r12 = -16, r12 /* allocate a scratch area on the stack */ |
| # initialize gp (Global Pointer) register |
| # Initialize gp (Global Pointer) register |
| movl r20 = (VRN_KERNEL << VRN_SHIFT);; |
| or r20 = r20,r1;; |
| movl r1 = _hardcoded_load_address |
| 216,12 → 198,11 |
| (p2) mov b1 = r18 ;; |
| (p2) br.call.sptk.many b0 = b1 |
| #Mark that BSP is on |
| # Mark that BSP is on |
| mov r20=1;; |
| movl r21=bsp_started;; |
| st8 [r21]=r20;; |
| br.call.sptk.many b0 = arch_pre_main |
| movl r18 = main_bsp ;; |
| 228,7 → 209,6 |
| mov b1 = r18 ;; |
| br.call.sptk.many b0 = b1 |
| 0: |
| br 0b |
| .align 4096 |
| 235,30 → 215,32 |
| kernel_image_ap_start: |
| .auto |
| #identifi self(CPU) in OS structures by ID / EID |
| mov r9=cr64 |
| mov r10=1 |
| movl r12=0xffffffff |
| movl r8=cpu_by_id_eid_list |
| and r8=r8,r12 |
| shr r9=r9,16 |
| add r8=r8,r9 |
| st1 [r8]=r10 |
| # Identify self(CPU) in OS structures by ID / EID |
| mov r9 = cr64 |
| mov r10 = 1 |
| movl r12 = 0xffffffff |
| movl r8 = cpu_by_id_eid_list |
| and r8 = r8, r12 |
| shr r9 = r9, 16 |
| add r8 = r8, r9 |
| st1 [r8] = r10 |
| #wait for wakeup sychro signal (#3 in cpu_by_id_eid_list) |
| # Wait for wakeup synchro signal (#3 in cpu_by_id_eid_list) |
| kernel_image_ap_start_loop: |
| movl r11=kernel_image_ap_start_loop |
| and r11=r11,r12 |
| movl r11 = kernel_image_ap_start_loop |
| and r11 = r11, r12 |
| mov b1 = r11 |
| ld1 r20=[r8];; |
| movl r21=3;; |
| cmp.eq p2,p3=r20,r21;; |
| (p3)br.call.sptk.many b0 = b1 |
| ld1 r20 = [r8];; |
| movl r21 = 3;; |
| cmp.eq p2, p3 = r20, r21;; |
| (p3) br.call.sptk.many b0 = b1 |
| movl r11=kernel_image_start |
| and r11=r11,r12 |
| mov b1 = r11 |
| movl r11 = kernel_image_start |
| and r11 = r11, r12 |
| mov b1 = r11 |
| br.call.sptk.many b0 = b1 |
| 267,10 → 249,8 |
| bsp_started: |
| .space 8 |
| .align 4096 |
| .global cpu_by_id_eid_list |
| cpu_by_id_eid_list: |
| .space 65536 |
| /trunk/kernel/arch/ia64/src/smp/smp.c |
|---|
| 61,37 → 61,28 |
| #include <panic.h> |
| #include <print.h> |
| #ifdef CONFIG_SMP |
| extern char cpu_by_id_eid_list[256][256]; |
| static void sapic_init(void) |
| { |
| bootinfo->sapic=(unative_t *)(PA2KA((unative_t)(bootinfo->sapic))|FW_OFFSET); |
| bootinfo->sapic = (unative_t *)(PA2KA((unative_t)(bootinfo->sapic)) | |
| FW_OFFSET); |
| } |
| static void ipi_broadcast_arch_all(int ipi ) |
| static void ipi_broadcast_arch_all(int ipi) |
| { |
| int id,eid; |
| int myid,myeid; |
| int myid, myeid; |
| myid=ia64_get_cpu_id(); |
| myeid=ia64_get_cpu_eid(); |
| myid = ia64_get_cpu_id(); |
| myeid = ia64_get_cpu_eid(); |
| for(id=0;id<256;id++) |
| for(eid=0;eid<256;eid++) |
| if((id!=myid) || (eid!=myeid)) |
| ipi_send_ipi(id,eid,ipi); |
| for (id = 0; id < 256; id++) |
| for (eid = 0; eid < 256; eid++) |
| if ((id != myid) || (eid != myeid)) |
| ipi_send_ipi(id, eid, ipi); |
| } |
| void ipi_broadcast_arch(int ipi ) |
| 99,82 → 90,90 |
| int id,eid; |
| int myid,myeid; |
| myid=ia64_get_cpu_id(); |
| myeid=ia64_get_cpu_eid(); |
| myid = ia64_get_cpu_id(); |
| myeid = ia64_get_cpu_eid(); |
| for(id=0;id<256;id++) |
| for(eid=0;eid<256;eid++) |
| if((id!=myid) || (eid!=myeid)) |
| if(cpu_by_id_eid_list[id][eid]) |
| ipi_send_ipi(id,eid,ipi); |
| for (id = 0; id < 256; id++) |
| for (eid = 0; eid < 256; eid++) |
| if ((id != myid) || (eid != myeid)) |
| if (cpu_by_id_eid_list[id][eid]) |
| ipi_send_ipi(id, eid, ipi); |
| } |
| void smp_init(void) |
| { |
| if(!bootinfo->hello_configured) return; |
| //If we have not system prepared by hello, we are not able to start AP's |
| //this means we are running on simulator |
| if (!bootinfo->hello_configured) |
| return; |
| /* |
| * If we have not system prepared by hello, we are not able to start |
| * AP's. This means we are running on a simulator. |
| */ |
| sapic_init(); |
| ipi_broadcast_arch_all(bootinfo->wakeup_intno); |
| volatile long long brk; |
| for(brk=0;brk<100LL*1024LL*1024LL;brk++); //wait a while before CPUs starts |
| for (brk = 0; brk < 100LL * 1024LL * 1024LL; brk++) |
| ; /* wait a while before CPUs starts */ |
| config.cpu_count=0; |
| int id,eid; |
| config.cpu_count = 0; |
| int id, eid; |
| for(id=0;id<256;id++) |
| for(eid=0;eid<256;eid++) |
| if(cpu_by_id_eid_list[id][eid]==1){ |
| for (id = 0; id < 256; id++) |
| for (eid = 0; eid < 256; eid++) |
| if (cpu_by_id_eid_list[id][eid] == 1) { |
| config.cpu_count++; |
| cpu_by_id_eid_list[id][eid]=2; |
| cpu_by_id_eid_list[id][eid] = 2; |
| } |
| } |
| void kmp(void *arg __attribute__((unused))) |
| { |
| int id,eid; |
| int myid,myeid; |
| int myid, myeid; |
| myid=ia64_get_cpu_id(); |
| myeid=ia64_get_cpu_eid(); |
| myid = ia64_get_cpu_id(); |
| myeid = ia64_get_cpu_eid(); |
| for(id=0;id<256;id++) |
| for(eid=0;eid<256;eid++) |
| if((id!=myid) || (eid!=myeid)) |
| if(cpu_by_id_eid_list[id][eid]!=0){ |
| if(cpu_by_id_eid_list[id][eid]==1){ |
| printf("Found Late CPU ID:%d EDI:%d Not added to system!!!\n",id,eid); |
| for (id = 0; id < 256; id++) |
| for (eid = 0; eid < 256; eid++) |
| if ((id != myid) || (eid != myeid)) |
| if (cpu_by_id_eid_list[id][eid] != 0) { |
| if (cpu_by_id_eid_list[id][eid] == 1) { |
| printf("Found Late CPU ID:%d " |
| "EDI:%d Not added to " |
| "system!!!\n", id, eid); |
| continue; |
| } |
| cpu_by_id_eid_list[id][eid]=3; |
| } |
| cpu_by_id_eid_list[id][eid] = 3; |
| /* |
| * There may be just one AP being initialized at |
| * the time. After it comes completely up, it is |
| * There may be just one AP being |
| * initialized at the time. After |
| * it comes completely up, it is |
| * supposed to wake us up. |
| */ |
| if (waitq_sleep_timeout(&ap_completion_wq, 1000000, |
| SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT) { |
| printf("%s: waiting for cpu ID:%d EID:%d" |
| "timed out\n", __FUNCTION__, |
| id, eid); |
| } |
| if (waitq_sleep_timeout( |
| &ap_completion_wq, 1000000, |
| SYNCH_FLAGS_NONE) == |
| ESYNCH_TIMEOUT) { |
| printf("%s: waiting for cpu " |
| "ID:%d EID:%d timed out\n", |
| __FUNCTION__, id, eid); |
| } |
| } |
| } |
| #endif |
| /*This is just a hack for linking with assembler - may be removed in future*/ |
| #ifndef CONFIG_SMP |
| /* This is just a hack for linking with assembler - may be removed in future. */ |
| void main_ap(void); |
| void main_ap(void) |
| { |
| while(1); |
| while(1) |
| ; |
| } |
| #endif |
| /trunk/kernel/arch/ia64/src/ddi/ddi.c |
|---|
| 1,5 → 1,6 |
| /* |
| * Copyright (c) 2006 Jakub Jermar, Jakub vana |
| * Copyright (c) 2006 Jakub Jermar |
| * Copyright (c) 2008 Jakub vana |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| 38,38 → 39,36 |
| #include <mm/slab.h> |
| #include <errno.h> |
| #define IO_MEMMAP_PAGES 16384 |
| #define PORTS_PER_PAGE 4 |
| #define IO_MEMMAP_PAGES 16384 |
| #define PORTS_PER_PAGE 4 |
| /** Enable I/O space range for task. |
| * |
| * Interrupts are disabled and task is locked. |
| * |
| * @param task Task. |
| * @param ioaddr Startign I/O space address. |
| * @param size Size of the enabled I/O range. |
| * @param task Task. |
| * @param ioaddr Starting I/O space address. |
| * @param size Size of the enabled I/O range. |
| * |
| * @return 0 on success or an error code from errno.h. |
| */ |
| int ddi_iospace_enable_arch(task_t *task, uintptr_t ioaddr, size_t size) |
| { |
| if (!task->arch.iomap) { |
| uint8_t *map; |
| if(!task->arch.iomap) |
| { |
| uint8_t *map; |
| task->arch.iomap=malloc(sizeof(bitmap_t),0); |
| map=malloc(BITS2BYTES(IO_MEMMAP_PAGES),0); |
| task->arch.iomap = malloc(sizeof(bitmap_t), 0); |
| map = malloc(BITS2BYTES(IO_MEMMAP_PAGES), 0); |
| if(!map) |
| return ENOMEM; |
| bitmap_initialize(task->arch.iomap,map,IO_MEMMAP_PAGES); |
| bitmap_clear_range(task->arch.iomap,0,IO_MEMMAP_PAGES); |
| bitmap_initialize(task->arch.iomap, map, IO_MEMMAP_PAGES); |
| bitmap_clear_range(task->arch.iomap, 0, IO_MEMMAP_PAGES); |
| } |
| uintptr_t iopage = ioaddr / PORTS_PER_PAGE; |
| size = ALIGN_UP (size+ioaddr-4*iopage,PORTS_PER_PAGE); |
| bitmap_set_range(task->arch.iomap,iopage,size/4); |
| size = ALIGN_UP(size + ioaddr - 4 * iopage, PORTS_PER_PAGE); |
| bitmap_set_range(task->arch.iomap, iopage, size / 4); |
| return 0; |
| } |
| /trunk/kernel/arch/ia64/src/proc/scheduler.c |
|---|
| 47,14 → 47,17 |
| { |
| } |
| /** Prepare kernel stack pointers in bank 0 r22 and r23 and make sure the stack is mapped in DTR. */ |
| /** Prepare kernel stack pointers in bank 0 r22 and r23 and make sure the stack |
| * is mapped in DTR. |
| */ |
| void before_thread_runs_arch(void) |
| { |
| uintptr_t base; |
| base = ALIGN_DOWN(config.base, 1<<KERNEL_PAGE_WIDTH); |
| base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH); |
| if ((uintptr_t) THREAD->kstack < base || (uintptr_t) THREAD->kstack > base + (1<<(KERNEL_PAGE_WIDTH))) { |
| if ((uintptr_t) THREAD->kstack < base || |
| (uintptr_t) THREAD->kstack > base + (1 << (KERNEL_PAGE_WIDTH))) { |
| /* |
| * Kernel stack of this thread is not mapped by DTR[TR_KERNEL]. |
| * Use DTR[TR_KSTACK1] and DTR[TR_KSTACK2] to map it. |
| 64,8 → 67,11 |
| dtr_purge((uintptr_t) THREAD->kstack, PAGE_WIDTH+1); |
| /* insert DTR[TR_STACK1] and DTR[TR_STACK2] */ |
| dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK1); |
| dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack + PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true, DTR_KSTACK2); |
| dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack, |
| KA2PA(THREAD->kstack), true, DTR_KSTACK1); |
| dtlb_kernel_mapping_insert((uintptr_t) THREAD->kstack + |
| PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true, |
| DTR_KSTACK2); |
| } |
| /* |
| /trunk/kernel/arch/ia64/src/mm/tlb.c |
|---|
| 92,7 → 92,7 |
| /** Invalidate entries belonging to an address space. |
| * |
| * @param asid Address space identifier. |
| * @param asid Address space identifier. |
| */ |
| void tlb_invalidate_asid(asid_t asid) |
| { |
| 131,50 → 131,45 |
| uint64_t ps; |
| switch (b) { |
| case 0: /*cnt 1-3*/ |
| case 0: /* cnt 1 - 3 */ |
| ps = PAGE_WIDTH; |
| break; |
| case 1: /*cnt 4-15*/ |
| ps = PAGE_WIDTH+2; |
| va &= ~((1<<ps)-1); |
| case 1: /* cnt 4 - 15 */ |
| ps = PAGE_WIDTH + 2; |
| va &= ~((1 << ps) - 1); |
| break; |
| case 2: /*cnt 16-63*/ |
| ps = PAGE_WIDTH+4; |
| va &= ~((1<<ps)-1); |
| case 2: /* cnt 16 - 63 */ |
| ps = PAGE_WIDTH + 4; |
| va &= ~((1 << ps) - 1); |
| break; |
| case 3: /*cnt 64-255*/ |
| ps = PAGE_WIDTH+6; |
| va &= ~((1<<ps)-1); |
| case 3: /* cnt 64 - 255 */ |
| ps = PAGE_WIDTH + 6; |
| va &= ~((1 << ps) - 1); |
| break; |
| case 4: /*cnt 256-1023*/ |
| ps = PAGE_WIDTH+8; |
| va &= ~((1<<ps)-1); |
| case 4: /* cnt 256 - 1023 */ |
| ps = PAGE_WIDTH + 8; |
| va &= ~((1 << ps) - 1); |
| break; |
| case 5: /*cnt 1024-4095*/ |
| ps = PAGE_WIDTH+10; |
| va &= ~((1<<ps)-1); |
| case 5: /* cnt 1024 - 4095 */ |
| ps = PAGE_WIDTH + 10; |
| va &= ~((1 << ps) - 1); |
| break; |
| case 6: /*cnt 4096-16383*/ |
| ps = PAGE_WIDTH+12; |
| va &= ~((1<<ps)-1); |
| case 6: /* cnt 4096 - 16383 */ |
| ps = PAGE_WIDTH + 12; |
| va &= ~((1 << ps) - 1); |
| break; |
| case 7: /*cnt 16384-65535*/ |
| case 8: /*cnt 65536-(256K-1)*/ |
| ps = PAGE_WIDTH+14; |
| va &= ~((1<<ps)-1); |
| case 7: /* cnt 16384 - 65535 */ |
| case 8: /* cnt 65536 - (256K - 1) */ |
| ps = PAGE_WIDTH + 14; |
| va &= ~((1 << ps) - 1); |
| break; |
| default: |
| ps=PAGE_WIDTH+18; |
| va&=~((1<<ps)-1); |
| ps = PAGE_WIDTH + 18; |
| va &= ~((1 << ps) - 1); |
| break; |
| } |
| for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps)) { |
| asm volatile ( |
| "ptc.l %0,%1;;" |
| : |
| : "r" (va), "r" (ps<<2) |
| ); |
| } |
| for(; va < (page + cnt * PAGE_SIZE); va += (1 << ps)) |
| asm volatile ("ptc.l %0, %1;;" :: "r" (va), "r" (ps << 2)); |
| srlz_d(); |
| srlz_i(); |
| 187,9 → 182,10 |
| /** Insert data into data translation cache. |
| * |
| * @param va Virtual page address. |
| * @param asid Address space identifier. |
| * @param entry The rest of TLB entry as required by TLB insertion format. |
| * @param va Virtual page address. |
| * @param asid Address space identifier. |
| * @param entry The rest of TLB entry as required by TLB insertion |
| * format. |
| */ |
| void dtc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
| { |
| 198,9 → 194,10 |
| /** Insert data into instruction translation cache. |
| * |
| * @param va Virtual page address. |
| * @param asid Address space identifier. |
| * @param entry The rest of TLB entry as required by TLB insertion format. |
| * @param va Virtual page address. |
| * @param asid Address space identifier. |
| * @param entry The rest of TLB entry as required by TLB insertion |
| * format. |
| */ |
| void itc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry) |
| { |
| 209,10 → 206,12 |
| /** Insert data into instruction or data translation cache. |
| * |
| * @param va Virtual page address. |
| * @param asid Address space identifier. |
| * @param entry The rest of TLB entry as required by TLB insertion format. |
| * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise. |
| * @param va Virtual page address. |
| * @param asid Address space identifier. |
| * @param entry The rest of TLB entry as required by TLB insertion |
| * format. |
| * @param dtc If true, insert into data translation cache, use |
| * instruction translation cache otherwise. |
| */ |
| void tc_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtc) |
| { |
| 235,19 → 234,20 |
| } |
| asm volatile ( |
| "mov r8=psr;;\n" |
| "mov r8 = psr;;\n" |
| "rsm %0;;\n" /* PSR_IC_MASK */ |
| "srlz.d;;\n" |
| "srlz.i;;\n" |
| "mov cr.ifa=%1\n" /* va */ |
| "mov cr.itir=%2;;\n" /* entry.word[1] */ |
| "cmp.eq p6,p7 = %4,r0;;\n" /* decide between itc and dtc */ |
| "mov cr.ifa = %1\n" /* va */ |
| "mov cr.itir = %2;;\n" /* entry.word[1] */ |
| "cmp.eq p6,p7 = %4,r0;;\n" /* decide between itc and dtc */ |
| "(p6) itc.i %3;;\n" |
| "(p7) itc.d %3;;\n" |
| "mov psr.l=r8;;\n" |
| "mov psr.l = r8;;\n" |
| "srlz.d;;\n" |
| : |
| : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc) |
| : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), |
| "r" (entry.word[0]), "r" (dtc) |
| : "p6", "p7", "r8" |
| ); |
| 260,12 → 260,14 |
| /** Insert data into instruction translation register. |
| * |
| * @param va Virtual page address. |
| * @param asid Address space identifier. |
| * @param entry The rest of TLB entry as required by TLB insertion format. |
| * @param tr Translation register. |
| * @param va Virtual page address. |
| * @param asid Address space identifier. |
| * @param entry The rest of TLB entry as required by TLB insertion |
| * format. |
| * @param tr Translation register. |
| */ |
| void itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
| void |
| itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
| { |
| tr_mapping_insert(va, asid, entry, false, tr); |
| } |
| 272,12 → 274,14 |
| /** Insert data into data translation register. |
| * |
| * @param va Virtual page address. |
| * @param asid Address space identifier. |
| * @param entry The rest of TLB entry as required by TLB insertion format. |
| * @param tr Translation register. |
| * @param va Virtual page address. |
| * @param asid Address space identifier. |
| * @param entry The rest of TLB entry as required by TLB insertion |
| * format. |
| * @param tr Translation register. |
| */ |
| void dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
| void |
| dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr) |
| { |
| tr_mapping_insert(va, asid, entry, true, tr); |
| } |
| 284,13 → 288,17 |
| /** Insert data into instruction or data translation register. |
| * |
| * @param va Virtual page address. |
| * @param asid Address space identifier. |
| * @param entry The rest of TLB entry as required by TLB insertion format. |
| * @param dtr If true, insert into data translation register, use instruction translation register otherwise. |
| * @param tr Translation register. |
| * @param va Virtual page address. |
| * @param asid Address space identifier. |
| * @param entry The rest of TLB entry as required by TLB insertion |
| * format. |
| * @param dtr If true, insert into data translation register, use |
| * instruction translation register otherwise. |
| * @param tr Translation register. |
| */ |
| void tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr) |
| void |
| tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr, |
| index_t tr) |
| { |
| region_register rr; |
| bool restore_rr = false; |
| 311,19 → 319,20 |
| } |
| asm volatile ( |
| "mov r8=psr;;\n" |
| "mov r8 = psr;;\n" |
| "rsm %0;;\n" /* PSR_IC_MASK */ |
| "srlz.d;;\n" |
| "srlz.i;;\n" |
| "mov cr.ifa=%1\n" /* va */ |
| "mov cr.itir=%2;;\n" /* entry.word[1] */ |
| "cmp.eq p6,p7=%5,r0;;\n" /* decide between itr and dtr */ |
| "(p6) itr.i itr[%4]=%3;;\n" |
| "(p7) itr.d dtr[%4]=%3;;\n" |
| "mov psr.l=r8;;\n" |
| "mov cr.ifa = %1\n" /* va */ |
| "mov cr.itir = %2;;\n" /* entry.word[1] */ |
| "cmp.eq p6,p7 = %5,r0;;\n" /* decide between itr and dtr */ |
| "(p6) itr.i itr[%4] = %3;;\n" |
| "(p7) itr.d dtr[%4] = %3;;\n" |
| "mov psr.l = r8;;\n" |
| "srlz.d;;\n" |
| : |
| : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr) |
| : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), |
| "r" (entry.word[0]), "r" (tr), "r" (dtr) |
| : "p6", "p7", "r8" |
| ); |
| 336,12 → 345,15 |
| /** Insert data into DTLB. |
| * |
| * @param page Virtual page address including VRN bits. |
| * @param frame Physical frame address. |
| * @param dtr If true, insert into data translation register, use data translation cache otherwise. |
| * @param tr Translation register if dtr is true, ignored otherwise. |
| * @param page Virtual page address including VRN bits. |
| * @param frame Physical frame address. |
| * @param dtr If true, insert into data translation register, use data |
| * translation cache otherwise. |
| * @param tr Translation register if dtr is true, ignored otherwise. |
| */ |
| void dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, index_t tr) |
| void |
| dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr, |
| index_t tr) |
| { |
| tlb_entry_t entry; |
| 367,18 → 379,18 |
| * |
| * Purge DTR entries used by the kernel. |
| * |
| * @param page Virtual page address including VRN bits. |
| * @param width Width of the purge in bits. |
| * @param page Virtual page address including VRN bits. |
| * @param width Width of the purge in bits. |
| */ |
| void dtr_purge(uintptr_t page, count_t width) |
| { |
| asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width<<2)); |
| asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2)); |
| } |
| /** Copy content of PTE into data translation cache. |
| * |
| * @param t PTE. |
| * @param t PTE. |
| */ |
| void dtc_pte_copy(pte_t *t) |
| { |
| 404,7 → 416,7 |
| /** Copy content of PTE into instruction translation cache. |
| * |
| * @param t PTE. |
| * @param t PTE. |
| */ |
| void itc_pte_copy(pte_t *t) |
| { |
| 431,8 → 443,8 |
| /** Instruction TLB fault handler for faults with VHPT turned off. |
| * |
| * @param vector Interruption vector. |
| * @param istate Structure with saved interruption state. |
| * @param vector Interruption vector. |
| * @param istate Structure with saved interruption state. |
| */ |
| void alternate_instruction_tlb_fault(uint64_t vector, istate_t *istate) |
| { |
| 461,43 → 473,45 |
| page_table_unlock(AS, true); |
| if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
| fault_if_from_uspace(istate,"Page fault at %p",va); |
| panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
| panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, |
| istate->cr_iip); |
| } |
| } |
| } |
| static int is_io_page_accessible(int page) |
| { |
| if(TASK->arch.iomap) return bitmap_get(TASK->arch.iomap,page); |
| else return 0; |
| if (TASK->arch.iomap) |
| return bitmap_get(TASK->arch.iomap,page); |
| else |
| return 0; |
| } |
| #define IO_FRAME_BASE 0xFFFFC000000 |
| /** There is special handling of memmaped lagacy io, because |
| * of 4KB sized access |
| * only for userspace |
| /** |
| * There is special handling of memory mapped legacy io, because of 4KB sized |
| * access for userspace. |
| * |
| * @param va virtual address of page fault |
| * @param istate Structure with saved interruption state. |
| * @param va Virtual address of page fault. |
| * @param istate Structure with saved interruption state. |
| * |
| * |
| * @return 1 on success, 0 on fail |
| * @return One on success, zero on failure. |
| */ |
| static int try_memmap_io_insertion(uintptr_t va, istate_t *istate) |
| { |
| if((va >= IO_OFFSET ) && (va < IO_OFFSET + (1<<IO_PAGE_WIDTH))) |
| if(TASK){ |
| uint64_t io_page=(va & ((1<<IO_PAGE_WIDTH)-1)) >> (USPACE_IO_PAGE_WIDTH); |
| if(is_io_page_accessible(io_page)){ |
| uint64_t page,frame; |
| if ((va >= IO_OFFSET ) && (va < IO_OFFSET + (1 << IO_PAGE_WIDTH))) { |
| if (TASK) { |
| uint64_t io_page = (va & ((1 << IO_PAGE_WIDTH) - 1)) >> |
| USPACE_IO_PAGE_WIDTH; |
| page = IO_OFFSET + (1 << USPACE_IO_PAGE_WIDTH) * io_page; |
| frame = IO_FRAME_BASE + (1 << USPACE_IO_PAGE_WIDTH) * io_page; |
| if (is_io_page_accessible(io_page)) { |
| uint64_t page, frame; |
| page = IO_OFFSET + |
| (1 << USPACE_IO_PAGE_WIDTH) * io_page; |
| frame = IO_FRAME_BASE + |
| (1 << USPACE_IO_PAGE_WIDTH) * io_page; |
| tlb_entry_t entry; |
| 504,10 → 518,10 |
| entry.word[0] = 0; |
| entry.word[1] = 0; |
| entry.p = true; /* present */ |
| entry.p = true; /* present */ |
| entry.ma = MA_UNCACHEABLE; |
| entry.a = true; /* already accessed */ |
| entry.d = true; /* already dirty */ |
| entry.a = true; /* already accessed */ |
| entry.d = true; /* already dirty */ |
| entry.pl = PL_USER; |
| entry.ar = AR_READ | AR_WRITE; |
| entry.ppn = frame >> PPN_SHIFT; |
| 515,26 → 529,20 |
| dtc_mapping_insert(page, TASK->as->asid, entry); |
| return 1; |
| }else { |
| fault_if_from_uspace(istate,"IO access fault at %p",va); |
| return 0; |
| } |
| } else |
| return 0; |
| else |
| return 0; |
| } else { |
| fault_if_from_uspace(istate, |
| "IO access fault at %p", va); |
| } |
| } |
| } |
| return 0; |
| } |
| /** Data TLB fault handler for faults with VHPT turned off. |
| * |
| * @param vector Interruption vector. |
| * @param istate Structure with saved interruption state. |
| * @param vector Interruption vector. |
| * @param istate Structure with saved interruption state. |
| */ |
| void alternate_data_tlb_fault(uint64_t vector, istate_t *istate) |
| { |
| 568,13 → 576,16 |
| page_table_unlock(AS, true); |
| } else { |
| page_table_unlock(AS, true); |
| if (try_memmap_io_insertion(va,istate)) return; |
| if (try_memmap_io_insertion(va, istate)) |
| return; |
| /* |
| * Forward the page fault to the address space page fault handler. |
| * Forward the page fault to the address space page fault |
| * handler. |
| */ |
| if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
| fault_if_from_uspace(istate,"Page fault at %p",va); |
| panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
| panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, |
| istate->cr_iip); |
| } |
| } |
| } |
| 583,8 → 594,8 |
| * |
| * This fault should not occur. |
| * |
| * @param vector Interruption vector. |
| * @param istate Structure with saved interruption state. |
| * @param vector Interruption vector. |
| * @param istate Structure with saved interruption state. |
| */ |
| void data_nested_tlb_fault(uint64_t vector, istate_t *istate) |
| { |
| 593,8 → 604,8 |
| /** Data Dirty bit fault handler. |
| * |
| * @param vector Interruption vector. |
| * @param istate Structure with saved interruption state. |
| * @param vector Interruption vector. |
| * @param istate Structure with saved interruption state. |
| */ |
| void data_dirty_bit_fault(uint64_t vector, istate_t *istate) |
| { |
| 620,9 → 631,8 |
| } else { |
| if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) { |
| fault_if_from_uspace(istate,"Page fault at %p",va); |
| panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
| t->d = true; |
| dtc_pte_copy(t); |
| panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, |
| istate->cr_iip); |
| } |
| } |
| page_table_unlock(AS, true); |
| 630,8 → 640,8 |
| /** Instruction access bit fault handler. |
| * |
| * @param vector Interruption vector. |
| * @param istate Structure with saved interruption state. |
| * @param vector Interruption vector. |
| * @param istate Structure with saved interruption state. |
| */ |
| void instruction_access_bit_fault(uint64_t vector, istate_t *istate) |
| { |
| 656,10 → 666,9 |
| itc_pte_copy(t); |
| } else { |
| if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) { |
| fault_if_from_uspace(istate,"Page fault at %p",va); |
| panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
| t->a = true; |
| itc_pte_copy(t); |
| fault_if_from_uspace(istate, "Page fault at %p", va); |
| panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, |
| istate->cr_iip); |
| } |
| } |
| page_table_unlock(AS, true); |
| 693,10 → 702,9 |
| dtc_pte_copy(t); |
| } else { |
| if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
| fault_if_from_uspace(istate,"Page fault at %p",va); |
| panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, istate->cr_iip); |
| t->a = true; |
| itc_pte_copy(t); |
| fault_if_from_uspace(istate, "Page fault at %p", va); |
| panic("%s: va=%p, rid=%d, iip=%p\n", __func__, va, rid, |
| istate->cr_iip); |
| } |
| } |
| page_table_unlock(AS, true); |
| 735,7 → 743,7 |
| } else { |
| page_table_unlock(AS, true); |
| if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) { |
| fault_if_from_uspace(istate,"Page fault at %p",va); |
| fault_if_from_uspace(istate, "Page fault at %p", va); |
| panic("%s: va=%p, rid=%d\n", __func__, va, rid); |
| } |
| } |
| /trunk/kernel/arch/ia64/src/mm/vhpt.c |
|---|
| 41,7 → 41,8 |
| uintptr_t vhpt_set_up(void) |
| { |
| vhpt_base = frame_alloc(VHPT_WIDTH - FRAME_WIDTH, FRAME_KA | FRAME_ATOMIC); |
| vhpt_base = frame_alloc(VHPT_WIDTH - FRAME_WIDTH, |
| FRAME_KA | FRAME_ATOMIC); |
| if (!vhpt_base) |
| panic("Kernel configured with VHPT but no memory for table."); |
| vhpt_invalidate_all(); |
| /trunk/kernel/arch/ia64/src/mm/as.c |
|---|
| 68,7 → 68,7 |
| continue; |
| rr.word = rr_read(i); |
| rr.map.ve = false; /* disable VHPT walker */ |
| rr.map.ve = false; /* disable VHPT walker */ |
| rr.map.rid = ASID2RID(as->asid, i); |
| rr.map.ps = PAGE_WIDTH; |
| rr_write(i, rr.word); |
| /trunk/kernel/arch/ia64/src/mm/page.c |
|---|
| 123,10 → 123,10 |
| * |
| * Interrupts must be disabled. |
| * |
| * @param page Address of virtual page including VRN bits. |
| * @param asid Address space identifier. |
| * @param page Address of virtual page including VRN bits. |
| * @param asid Address space identifier. |
| * |
| * @return VHPT entry address. |
| * @return VHPT entry address. |
| */ |
| vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid) |
| { |
| 167,10 → 167,11 |
| * |
| * Interrupts must be disabled. |
| * |
| * @param page Address of virtual page including VRN bits. |
| * @param asid Address space identifier. |
| * @param page Address of virtual page including VRN bits. |
| * @param asid Address space identifier. |
| * |
| * @return True if page and asid match the page and asid of t, false otherwise. |
| * @return True if page and asid match the page and asid of t, |
| * false otherwise. |
| */ |
| bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v) |
| { |
| 211,12 → 212,15 |
| /** Set up one VHPT entry. |
| * |
| * @param v VHPT entry to be set up. |
| * @param page Virtual address of the page mapped by the entry. |
| * @param asid Address space identifier of the address space to which page belongs. |
| * @param frame Physical address of the frame to wich page is mapped. |
| * @param flags Different flags for the mapping. |
| * @param page Virtual address of the page mapped by the entry. |
| * @param asid Address space identifier of the address space to which |
| * page belongs. |
| * @param frame Physical address of the frame to wich page is mapped. |
| * @param flags Different flags for the mapping. |
| */ |
| void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags) |
| void |
| vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, |
| int flags) |
| { |
| region_register rr_save, rr; |
| index_t vrn; |
| 250,7 → 254,8 |
| v->word[3] = 0; |
| v->present.p = true; |
| v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE; |
| v->present.ma = (flags & PAGE_CACHEABLE) ? |
| MA_WRITEBACK : MA_UNCACHEABLE; |
| v->present.a = false; /* not accessed */ |
| v->present.d = false; /* not dirty */ |
| v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL; |
| 265,17 → 270,19 |
| extern uintptr_t last_frame; |
| uintptr_t hw_map(uintptr_t physaddr, size_t size) |
| { |
| if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) |
| panic("Unable to map physical memory %p (%d bytes)", physaddr, size) |
| if (last_frame + ALIGN_UP(size, PAGE_SIZE) > |
| KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH)) |
| panic("Unable to map physical memory %p (%d bytes)", physaddr, |
| size) |
| uintptr_t virtaddr = PA2KA(last_frame); |
| pfn_t i; |
| for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++) { |
| uintptr_t addr = PFN2ADDR(i); |
| page_mapping_insert(AS_KERNEL, virtaddr + addr, physaddr + addr, PAGE_NOT_CACHEABLE | PAGE_WRITE); |
| page_mapping_insert(AS_KERNEL, virtaddr + addr, physaddr + addr, |
| PAGE_NOT_CACHEABLE | PAGE_WRITE); |
| } |
| last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE); |
| 283,7 → 290,5 |
| return virtaddr; |
| } |
| /** @} |
| */ |
| /trunk/kernel/arch/ia64/src/interrupt.c |
|---|
| 244,71 → 244,61 |
| void external_interrupt(uint64_t vector, istate_t *istate) |
| { |
| cr_ivr_t ivr; |
| irq_t *irq; |
| ivr.value = ivr_read(); |
| srlz_d(); |
| switch (ivr.vector) { |
| case INTERRUPT_SPURIOUS: |
| switch (ivr.vector) { |
| case INTERRUPT_SPURIOUS: |
| #ifdef CONFIG_DEBUG |
| printf("cpu%d: spurious interrupt\n", CPU->id); |
| printf("cpu%d: spurious interrupt\n", CPU->id); |
| #endif |
| break; |
| break; |
| #ifdef CONFIG_SMP |
| case VECTOR_TLB_SHOOTDOWN_IPI: |
| tlb_shootdown_ipi_recv(); |
| end_of_local_irq(); |
| break; |
| case VECTOR_TLB_SHOOTDOWN_IPI: |
| tlb_shootdown_ipi_recv(); |
| end_of_local_irq(); |
| break; |
| #endif |
| case INTERRUPT_TIMER: |
| { |
| irq_t *irq = irq_dispatch_and_lock(ivr.vector); |
| if (irq) { |
| irq->handler(irq, irq->arg); |
| spinlock_unlock(&irq->lock); |
| } else { |
| panic("\nUnhandled Internal Timer Interrupt (%d)\n",ivr.vector); |
| } |
| } |
| break; |
| default: |
| { |
| int ack=false; |
| irq_t *irq = irq_dispatch_and_lock(ivr.vector); |
| if (irq) { |
| /* |
| * The IRQ handler was found. |
| */ |
| if (irq->preack) { |
| /* Send EOI before processing the interrupt */ |
| end_of_local_irq(); |
| ack=true; |
| } |
| irq->handler(irq, irq->arg); |
| spinlock_unlock(&irq->lock); |
| } else { |
| /* |
| * Unhandled interrupt. |
| */ |
| end_of_local_irq(); |
| ack=true; |
| case INTERRUPT_TIMER: |
| irq = irq_dispatch_and_lock(ivr.vector); |
| if (irq) { |
| irq->handler(irq, irq->arg); |
| spinlock_unlock(&irq->lock); |
| } else { |
| panic("\nUnhandled Internal Timer Interrupt (%d)\n", |
| ivr.vector); |
| } |
| break; |
| default: |
| irq = irq_dispatch_and_lock(ivr.vector); |
| if (irq) { |
| /* |
| * The IRQ handler was found. |
| */ |
| if (irq->preack) { |
| /* Send EOI before processing the interrupt */ |
| end_of_local_irq(); |
| } |
| irq->handler(irq, irq->arg); |
| if (!irq->preack) |
| end_of_local_irq(); |
| spinlock_unlock(&irq->lock); |
| } else { |
| /* |
| * Unhandled interrupt. |
| */ |
| end_of_local_irq(); |
| #ifdef CONFIG_DEBUG |
| printf("\nUnhandled External Interrupt Vector %d\n",ivr.vector); |
| printf("\nUnhandled External Interrupt Vector %d\n", |
| ivr.vector); |
| #endif |
| } |
| if(!ack) end_of_local_irq(); |
| } |
| break; |
| } |
| break; |
| } |
| } |
| /** @} |
| /trunk/kernel/arch/ia64/src/drivers/ega.c |
|---|
| 82,7 → 82,6 |
| chardev_initialize("ega_out", &ega_console, &ega_ops); |
| stdout = &ega_console; |
| ega_parea.pbase = VIDEORAM & 0xffffffff; |
| ega_parea.vbase = (uintptr_t) videoram; |
| ega_parea.frames = 1; |
| 89,13 → 88,13 |
| ega_parea.cacheable = false; |
| ddi_parea_register(&ega_parea); |
| sysinfo_set_item_val("fb", NULL, true); |
| sysinfo_set_item_val("fb.kind", NULL, 2); |
| sysinfo_set_item_val("fb.width", NULL, ROW); |
| sysinfo_set_item_val("fb.height", NULL, ROWS); |
| sysinfo_set_item_val("fb.blinking", NULL, true); |
| sysinfo_set_item_val("fb.address.physical", NULL, VIDEORAM & 0xffffffff); |
| sysinfo_set_item_val("fb.address.physical", NULL, |
| VIDEORAM & 0xffffffff); |
| #ifndef CONFIG_FB |
| putchar('\n'); |
| 116,7 → 115,8 |
| if (ega_cursor < SCREEN) |
| return; |
| memmove((void *) videoram, (void *) (videoram + ROW * 2), (SCREEN - ROW) * 2); |
| memmove((void *) videoram, (void *) (videoram + ROW * 2), |
| (SCREEN - ROW) * 2); |
| _memsetw(videoram + (SCREEN - ROW) * 2, ROW, 0x0720); |
| ega_cursor = ega_cursor - ROW; |
| } |
| /trunk/kernel/arch/ia64/src/drivers/it.c |
|---|
| 44,18 → 44,16 |
| #include <ddi/device.h> |
| #include <arch.h> |
| #define IT_SERVICE_CLOCKS 64 |
| #define IT_SERVICE_CLOCKS 64 |
| #define FREQ_NUMERATOR_SHIFT 32 |
| #define FREQ_NUMERATOR_MASK 0xffffffff00000000LL |
| #define FREQ_NUMERATOR_SHIFT 32 |
| #define FREQ_NUMERATOR_MASK 0xffffffff00000000ULL |
| #define FREQ_DENOMINATOR_SHIFT 0 |
| #define FREQ_DENOMINATOR_MASK 0xffffffffLL |
| #define FREQ_DENOMINATOR_SHIFT 0 |
| #define FREQ_DENOMINATOR_MASK 0xffffffffULL |
| uint64_t it_delta; |
| static irq_t it_irq; |
| static irq_ownership_t it_claim(void); |
| 66,8 → 64,7 |
| { |
| cr_itv_t itv; |
| if(config.cpu_active==1) |
| { |
| if (config.cpu_active == 1) { |
| irq_initialize(&it_irq); |
| it_irq.inr = INTERRUPT_TIMER; |
| it_irq.devno = device_assign_devno(); |
| 76,12 → 73,13 |
| irq_register(&it_irq); |
| uint64_t base_freq; |
| base_freq = ((bootinfo->freq_scale) & FREQ_NUMERATOR_MASK) >> FREQ_NUMERATOR_SHIFT; |
| base_freq = ((bootinfo->freq_scale) & FREQ_NUMERATOR_MASK) >> |
| FREQ_NUMERATOR_SHIFT; |
| base_freq *= bootinfo->sys_freq; |
| base_freq /= ((bootinfo->freq_scale) & FREQ_DENOMINATOR_MASK) >> FREQ_DENOMINATOR_SHIFT; |
| base_freq /= ((bootinfo->freq_scale) & FREQ_DENOMINATOR_MASK) >> |
| FREQ_DENOMINATOR_SHIFT; |
| it_delta = base_freq /HZ; |
| it_delta = base_freq / HZ; |
| } |
| /* initialize Interval Timer external interrupt vector */ |