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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /trunk/ @ 1995

  → /trunk/ @ 1996

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 1995 → Rev 1996

/trunk/kernel/kernel.config
98,7 → 98,7
! [ARCH=sparc64] CONFIG_NS16550 (y/n)
# Virtually indexed cache support
! [ARCH=sparc64] CONFIG_VIRT_IDX_SUPPORT (n/y)
! [ARCH=sparc64] CONFIG_VIRT_IDX_CACHE (n/y)
## Debugging configuration directives

/trunk/kernel/Makefile
91,6 → 91,10
DEFS += -DCONFIG_NS16550
endif
ifeq ($(CONFIG_VIRT_IDX_CACHE),y)
DEFS += -DCONFIG_VIRT_IDX_CACHE
endif
ifeq ($(CONFIG_POWEROFF),y)
DEFS += -DCONFIG_POWEROFF
endif

/trunk/kernel/arch/sparc64/src/mm/tlb.c
111,7 → 111,9
data.pfn = fr.pfn;
data.l = locked;
data.cp = cacheable;
#ifdef CONFIG_VIRT_IDX_CACHE
data.cv = cacheable;
#endif /* CONFIG_VIRT_IDX_CACHE */
data.p = true;
data.w = true;
data.g = false;
146,7 → 148,9
data.pfn = fr.pfn;
data.l = false;
data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_CACHE
data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_CACHE */
data.p = t->k; /* p like privileged */
data.w = ro ? false : t->w;
data.g = t->g;
180,7 → 184,9
data.pfn = fr.pfn;
data.l = false;
data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_CACHE
data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_CACHE */
data.p = t->k; /* p like privileged */
data.w = false;
data.g = t->g;

/trunk/kernel/arch/sparc64/src/mm/tsb.c
100,7 → 100,9
tsb->data.size = PAGESIZE_8K;
tsb->data.pfn = t->frame >> PAGE_WIDTH;
tsb->data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_CACHE
tsb->data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_CACHE */
tsb->data.p = t->k; /* p as privileged */
tsb->data.v = t->p;
140,7 → 142,9
tsb->data.size = PAGESIZE_8K;
tsb->data.pfn = t->frame >> PAGE_WIDTH;
tsb->data.cp = t->c;
#ifdef CONFIG_VIRT_IDX_CACHE
tsb->data.cv = t->c;
#endif /* CONFIG_VIRT_IDX_CACHE */
tsb->data.p = t->k; /* p as privileged */
tsb->data.w = ro ? false : t->w;
tsb->data.v = t->p;

/trunk/kernel/arch/sparc64/src/start.S
122,8 → 122,14
stxa %g1, [VA_DMMU_TAG_ACCESS] %asi
membar #Sync
#ifdef CONFIG_VIRT_IDX_CACHE
#define TTE_LOW_DATA(imm) (TTE_CP | TTE_CV | TTE_P | LMA | (imm))
#else /* CONFIG_VIRT_IDX_CACHE */
#define TTE_LOW_DATA(imm) (TTE_CP | TTE_P | LMA | (imm))
#endif /* CONFIG_VIRT_IDX_CACHE */
#define SET_TLB_DATA(r1, r2, imm) \
set TTE_CV | TTE_CP | TTE_P | LMA | imm, %r1; \
set TTE_LOW_DATA(imm), %r1; \
or %r1, %l5, %r1; \
mov PAGESIZE_4M, %r2; \
sllx %r2, TTE_SIZE_SHIFT, %r2; \
348,4 → 354,8
*/
.global kernel_8k_tlb_data_template
kernel_8k_tlb_data_template:
.quad ((1 << TTE_V_SHIFT) | TTE_CV | TTE_CP | TTE_P | TTE_W)
#ifdef CONFIG_VIRT_IDX_CACHE
.quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | TTE_CV | TTE_P | TTE_W)
#else /* CONFIG_VIRT_IDX_CACHE */
.quad ((1 << TTE_V_SHIFT) | (PAGESIZE_8K << TTE_SIZE_SHIFT) | TTE_CP | TTE_P | TTE_W)
#endif /* CONFIG_VIRT_IDX_CACHE */