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Ignore whitespace Rev 1967 → Rev 1968

/tags/0.2.0.1/kernel/doc/BUGS_FOUND
0,0 → 1,23
During development of this operating system, there were found bugs in:
 
Simics
======
- ia32 BIOS rewrites memory during AP start in SMP environment (#3351)
- ia32 Simics does not report #GP when EFER.NXE is 0 and finds NX page (#4214)
- incorrect MIPS instructions MSUB, MSUBU
 
Bochs
=====
- FXSAVE/FXRSTOR not working correctly with XMM registers (patch #1282033)
 
Msim
====
- Incorrect interpretation of lwl/lwr/swl/swr instructions
- Omitted excMod case in write_proc_mem()
- Incorrect signed multiplication
 
Gcc
===
- Incorrect generation of unaligned data access instructions
(lwl/lwr/swl/swr) when using mipsel- target and -EB(big endian)
compilation, -O2 (#23824)
/tags/0.2.0.1/kernel/doc/arch/ia64
0,0 → 1,16
ia64 port
=========
 
ia64 port is the third port of SPARTAN originally written by Jakub Jermar.
It is still in its early stages. It runs on HP Ski simulator of IA-64 architecture.
 
HARDWARE REQUIREMENTS
o no real hardware supported
 
EMULATORS AND VIRTUALIZERS
o ski
 
TOOLCHAIN REQUIREMENTS
o binutils 2.15, 2.16, 2.16.1
o gcc 4.0.0, 4.0.1, 4.1.0, 4.1.1
o older versions may do as well, but are now obsoleted
/tags/0.2.0.1/kernel/doc/arch/ppc32
0,0 → 1,16
ppc32 port
==========
 
ppc32 port is the fourth port of SPARTAN, originally written by Martin Decky.
The goal is to support 32-bit PowerPC architecture.
So far, it runs only in emulator.
 
HARDWARE REQUIREMENTS
o no real hardware supported
 
EMULATORS AND VIRTUALIZERS
o PearPC
 
TOOLCHAIN REQUIREMENTS
o binutils 2.16
o gcc 4.0.1, 4.1.0, 4.1.1
/tags/0.2.0.1/kernel/doc/arch/amd64
0,0 → 1,34
amd64 port
==========
 
The fifth port, amd64 port, was originally written by Ondrej Palkovsky.
The goal is to support AMD64 and Intel Extended Memory 64 Technology PC's.
The port makes use of portable parts of ia32.
Both uniprocessors and multiprocessors are supported.
The kernel runs on real hardware and in simulators too.
 
HARDWARE REQUIREMENTS
o AMD64 architecture processor
o Intel Extended Memory 64 Technology processor
 
CPU
o Intel Xeon with Intel Extended Memory 64 Technology
 
SMP COMPATIBILITY
o Bochs 2.2.1 - 2.2.6
o 2x-8x AMD64 CPU
o Simics 2.2.19
o 2x-15x AMD hammer CPU
o QEMU 0.8.0 - QEMU 0.8.1
o 2x-15x CPU
o HP ProLiant ML350 (HyperThreading)
 
EMULATORS AND VIRTUALIZERS
o Bochs 2.2.6
o Simics 2.2.19
o QEMU 0.8.1
 
TOOLCHAIN REQUIREMENTS
o binutils 2.16, 2.16.1
o gcc 4.0.1, 4.1.0, 4.1.1
o older versions may do as well, but are now obsoleted
/tags/0.2.0.1/kernel/doc/arch/mips32
0,0 → 1,24
mips32 port
===========
 
mips32 is the second port of SPARTAN kernel originally written by Jakub Jermar.
It was first developed to run on MIPS R4000 32-bit simulator.
Now it can run on real hardware as well.
It can be compiled and run either as little- or big-endian.
 
HARDWARE REQUIREMENTS
o SGI Indy R4600
o emulated MIPS 4K CPU
 
CPU
o QED R4600
 
EMULATORS AND VIRTUALIZERS
o msim 1.2.8
o gxemul - both big and little endian
o simics 2.2.19
 
TOOLCHAIN REQUIREMENTS
o binutils 2.16, 2.16.1
o gcc 4.0.1, 4.1.0, 4.1.1
o older versions may do as well, but are now obsoleted
/tags/0.2.0.1/kernel/doc/arch/ia32
0,0 → 1,40
ia32 port
=========
 
ia32 port is the oldest and the most advanced one.
It was originally written by Jakub Jermar.
It is meant to support ordinary PC's based on IA-32 architecture.
Both uniprocessor and multiprocessor modes are supported.
It runs both in emulated environment and on real hardware.
 
HARDWARE REQUIREMENTS
o IA-32 processor (Pentium and successors)
 
SMP COMPATIBILITY
o Bochs 2.0.2 - Bochs 2.2.6
o 2x-8x 686 CPU
o Simics 2.0.28 - Simics 2.2.19
o 2x-15x Pentium 4 CPU
o VMware Workstation 5.5
o 2x CPU
o QEMU 0.8.0 - QEMU 0.8.1
o 2x-15x CPU
o ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41
o 2x 200Mhz Pentium CPU
o ASUS PCH-DL
o 2x 3000Mhz Pentium 4 Xeon (HT) CPU
o MSI K7D Master-L
o 2x 2100MHz Athlon MP CPU
o ECS 865PE-A REV : 2.0
o 1x 2800MHz Pentium 4 Prescott (HT) CPU
 
EMULATORS AND VIRTUALIZERS
o Bochs 2.0.2 - Bochs 2.2.6
o VMware Workstation 4, VMware Workstation 5, VMware Workstation 5.5
o Simics 2.2.19
o QEMU 0.8.0 - QEMU 0.8.1
 
TOOLCHAIN REQUIREMENTS
o binutils 2.15, 2.16, 2.16.1
o gcc 3.3.5, 4.0.1, 4.1.0, 4.1.1
o older versions may do as well, but are now obsoleted
/tags/0.2.0.1/kernel/doc/arch/sparc64
0,0 → 1,8
sparc64 port
============
 
Currently, this porting effort is subject to
Jakub Jermar's work on his master thesis.
 
The goal is to provide support for UltraSPARC
implementation of SPARC V9 architecture.
/tags/0.2.0.1/kernel/doc/mm
0,0 → 1,87
Memory management
=================
 
1. Virtual Address Translation
 
1.1 Hierarchical 4-level per address space page tables
 
SPARTAN kernel deploys generic interface for 4-level page tables
for these architectures: amd64, ia32, mips32 and ppc32. In this
setting, page tables are hierarchical and are not shared by
address spaces (i.e. one set of page tables per address space).
 
 
VADDR
+-----------------------------------------------------------------------------+
| PTL0_INDEX | PTL1_INDEX | PTL2_INDEX | PTL3_INDEX | OFFSET |
+-----------------------------------------------------------------------------+
 
 
PTL0 PTL1 PTL2 PTL3
+--------+ +--------+ +--------+ +--------+
| | | | | PTL3 | -----\ | |
| | | | +--------+ | | |
| | +--------+ | | | | |
| | | PTL2 | -----\ | | | | |
| | +--------+ | | | | | |
| | | | | | | | +--------+
+--------+ | | | | | | | FRAME |
| PTL1 | -----\ | | | | | | +--------+
+--------+ | | | | | | | | |
| | | | | | | | | | |
| | | | | | | | | | |
+--------+ \----> +--------+ \----> +--------+ \----> +--------+
^
|
|
+--------+
| PTL0 |
+--------+
 
 
PTL0 Page Table Level 0 (Page Directory)
PTL1 Page Table Level 1
PTL2 Page Table Level 2
PTL3 Page Table Level 3
 
PTL0_INDEX Index into PTL0
PTL1_INDEX Index into PTL1
PTL2_INDEX Index into PTL2
PTL3_INDEX Index into PTL3
 
VADDR Virtual address for which mapping is looked up
FRAME Physical address of memory frame to which VADDR is mapped
 
 
On architectures whose hardware has fewer levels, PTL2 and, if need be, PTL1 are
left out. TLB-only architectures are to define custom format for software page
tables.
 
1.2 Single global page hash table
 
Generic page hash table interface is deployed on 64-bit architectures without
implied hardware support for hierarchical page tables, i.e. ia64 and sparc64.
There is only one global page hash table in the system shared by all address
spaces.
 
 
2. Memory allocators
 
2.1 General allocator
 
'malloc' function accepts flags as a second argument. The flags are directly
passed to the underlying frame_alloc function.
 
1) If the flags parameter contains FRAME_ATOMIC, the allocator will not sleep.
The allocator CAN return NULL, when memory is not directly available.
The caller MUST check if NULL was not returned
 
2) If the flags parameter does not contain FRAME_ATOMIC, the allocator
will never return NULL, but it CAN sleep indefinitely. The caller
does not have to check the return value.
 
3) The maximum size that can be allocated using malloc is 128K
 
Rules 1) and 2) apply to slab_alloc as well. Using SLAB allocator
to allocate too large values is not recommended.
 
/tags/0.2.0.1/kernel/doc/AUTHORS
0,0 → 1,7
Jakub Jermar <jermar@helenos.eu>
Ondrej Palkovsky <palkovsky@helenos.eu>
Martin Decky <decky@helenos.eu>
Jakub Vana <vana@helenos.eu>
Josef Cejka <cejka@helenos.eu>
Sergey Bondari <bondari@helenos.eu>
 
/tags/0.2.0.1/kernel/doc/build
0,0 → 1,14
Following make targets are supported:
 
make, make all
- Check configuration, build
 
make config
- Start kernel configuration program
 
make clean
- Clean build temporary files
 
make distclean
- Clean everything including configuration
 
/tags/0.2.0.1/kernel/doc/synchronization
0,0 → 1,29
 
SPINNING LOCKS
spinlock_lock, spinlock_trylock, spinlock_unlock
+------------+
| spinlock_t |
+------------+
 
WAIT QUEUES
waitq_sleep_timeout, waitq_wakeup
+---------+
| waitq_t |
+---------+
/ \
SEMAPHORES / \ CONDITION VARIABLES
semaphore_down_timeout, semaphore_up condvar_wait_timeout, condvar_signal
+--------------+ / \ +-----------+
| semaphore_t |<-+ +->| condvar_t |
+--------------+ +-----------+
| ^
| |
| +------+
V /
MUTEXES / READERS/WRITERS LOCKS
mutex_lock_timeout, mutex_unlock rwlock_reader/writer_lock_timeout, rwlock_unlock
+---------+ / +----------+
| mutex_t |------------------------------->| rwlock_t |
+---------+ / +----------+
| /
+------------------------+