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  → /tags/0.2.0/kernel/arch/ @ 1967

  → /tags/0.2.0/kernel/arch/ @ 1968

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Ignore whitespace Rev 1967 → Rev 1968

/tags/0.2.0/kernel/arch/mips32/src/mips32.c
0,0 → 1,178
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <arch/cp0.h>
#include <arch/exception.h>
#include <arch/asm.h>
#include <mm/as.h>
#include <userspace.h>
#include <arch/console.h>
#include <memstr.h>
#include <proc/thread.h>
#include <proc/uarg.h>
#include <print.h>
#include <syscall/syscall.h>
#include <sysinfo/sysinfo.h>
#include <arch/interrupt.h>
#include <arch/drivers/arc.h>
#include <console/chardev.h>
#include <arch/debugger.h>
#include <genarch/fb/fb.h>
#include <debug.h>
#include <arch/asm/regname.h>
/* Size of the code jumping to the exception handler code
* - J+NOP
*/
#define EXCEPTION_JUMP_SIZE 8
#define TLB_EXC ((char *) 0x80000000)
#define NORM_EXC ((char *) 0x80000180)
#define CACHE_EXC ((char *) 0x80000100)
void arch_pre_main(void)
{
/* Setup usermode */
init.cnt = 6;
init.tasks[0].addr = INIT_ADDRESS;
init.tasks[0].size = INIT_SIZE;
init.tasks[1].addr = INIT_ADDRESS + 0x100000;
init.tasks[1].size = INIT_SIZE;
init.tasks[2].addr = INIT_ADDRESS + 0x200000;
init.tasks[2].size = INIT_SIZE;
init.tasks[3].addr = INIT_ADDRESS + 0x300000;
init.tasks[3].size = INIT_SIZE;
init.tasks[4].addr = INIT_ADDRESS + 0x400000;
init.tasks[4].size = INIT_SIZE;
init.tasks[5].addr = INIT_ADDRESS + 0x500000;
init.tasks[5].size = INIT_SIZE;
}
void arch_pre_mm_init(void)
{
/* It is not assumed by default */
interrupts_disable();
/* Initialize dispatch table */
exception_init();
arc_init();
/* Copy the exception vectors to the right places */
memcpy(TLB_EXC, (char *)tlb_refill_entry, EXCEPTION_JUMP_SIZE);
memcpy(NORM_EXC, (char *)exception_entry, EXCEPTION_JUMP_SIZE);
memcpy(CACHE_EXC, (char *)cache_error_entry, EXCEPTION_JUMP_SIZE);
interrupt_init();
/*
* Switch to BEV normal level so that exception vectors point to the kernel.
* Clear the error level.
*/
cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit));
/*
* Mask all interrupts
*/
cp0_mask_all_int();
/*
* Unmask hardware clock interrupt.
*/
cp0_unmask_int(TIMER_IRQ);
console_init();
debugger_init();
}
void arch_post_mm_init(void)
{
#ifdef CONFIG_FB
fb_init(0x12000000, 640, 480, 24, 1920); // gxemul framebuffer
#endif
sysinfo_set_item_val("machine." STRING(MACHINE),NULL,1);
}
void arch_pre_smp_init(void)
{
}
void arch_post_smp_init(void)
{
}
/* Stack pointer saved when entering user mode */
/* TODO: How do we do it on SMP system???? */
/* Why the linker moves the variable 64K away in assembler
* when not in .text section ????????
*/
__address supervisor_sp __attribute__ ((section (".text")));
void userspace(uspace_arg_t *kernel_uarg)
{
/* EXL=1, UM=1, IE=1 */
cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit |
cp0_status_um_bit |
cp0_status_ie_enabled_bit));
cp0_epc_write((__address) kernel_uarg->uspace_entry);
userspace_asm(((__address) kernel_uarg->uspace_stack+PAGE_SIZE),
(__address) kernel_uarg->uspace_uarg,
(__address) kernel_uarg->uspace_entry);
while (1)
;
}
/** Perform mips32 specific tasks needed before the new task is run. */
void before_task_runs_arch(void)
{
}
/** Perform mips32 specific tasks needed before the new thread is scheduled. */
void before_thread_runs_arch(void)
{
supervisor_sp = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
}
void after_thread_ran_arch(void)
{
}
/** Set thread-local-storage pointer
*
* We have it currently in K1, it is
* possible to have it separately in the future.
*/
__native sys_tls_set(__native addr)
{
return 0;
}

/tags/0.2.0/kernel/arch/mips32/src/asm.S
0,0 → 1,299
#
# Copyright (C) 2003-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/regname.h>
.text
.macro cp0_read reg
mfc0 $2,\reg
j $31
nop
.endm
.macro cp0_write reg
mtc0 $4,\reg
j $31
nop
.endm
.set noat
.set noreorder
.set nomacro
.global cpu_halt
cpu_halt:
j cpu_halt
nop
.global memsetb
memsetb:
j _memsetb
nop
.global memcpy
.global memcpy_from_uspace
.global memcpy_to_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace_failover_address
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
addiu $v0,$a1,3
li $v1,-4 # 0xfffffffffffffffc
and $v0,$v0,$v1
beq $a1,$v0,3f
move $t0,$a0
0:
beq $a2,$zero,2f
move $a3,$zero
1:
addu $v0,$a1,$a3
lbu $a0,0($v0)
addu $v1,$t0,$a3
addiu $a3,$a3,1
bne $a3,$a2,1b
sb $a0,0($v1)
2:
jr $ra
move $v0,$a1
3:
addiu $v0,$a0,3
and $v0,$v0,$v1
bne $a0,$v0,0b
srl $t1,$a2,2
beq $t1,$zero,5f
move $a3,$zero
move $a3,$zero
move $a0,$zero
4:
addu $v0,$a1,$a0
lw $v1,0($v0)
addiu $a3,$a3,1
addu $v0,$t0,$a0
sw $v1,0($v0)
bne $a3,$t1,4b
addiu $a0,$a0,4
5:
andi $a2,$a2,0x3
beq $a2,$zero,2b
nop
sll $v0,$a3,2
addu $t1,$v0,$t0
move $a3,$zero
addu $t0,$v0,$a1
6:
addu $v0,$t0,$a3
lbu $a0,0($v0)
addu $v1,$t1,$a3
addiu $a3,$a3,1
bne $a3,$a2,6b
sb $a0,0($v1)
jr $ra
move $v0,$a1
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
jr $ra
move $v0, $zero
.macro fpu_gp_save reg ctx
mfc1 $t0,$\reg
sw $t0, \reg*4(\ctx)
.endm
.macro fpu_gp_restore reg ctx
lw $t0, \reg*4(\ctx)
mtc1 $t0,$\reg
.endm
.macro fpu_ct_save reg ctx
cfc1 $t0,$1
sw $t0, (\reg+32)*4(\ctx)
.endm
.macro fpu_ct_restore reg ctx
lw $t0, (\reg+32)*4(\ctx)
ctc1 $t0,$\reg
.endm
.global fpu_context_save
fpu_context_save:
#ifdef ARCH_HAS_FPU
fpu_gp_save 0,$a0
fpu_gp_save 1,$a0
fpu_gp_save 2,$a0
fpu_gp_save 3,$a0
fpu_gp_save 4,$a0
fpu_gp_save 5,$a0
fpu_gp_save 6,$a0
fpu_gp_save 7,$a0
fpu_gp_save 8,$a0
fpu_gp_save 9,$a0
fpu_gp_save 10,$a0
fpu_gp_save 11,$a0
fpu_gp_save 12,$a0
fpu_gp_save 13,$a0
fpu_gp_save 14,$a0
fpu_gp_save 15,$a0
fpu_gp_save 16,$a0
fpu_gp_save 17,$a0
fpu_gp_save 18,$a0
fpu_gp_save 19,$a0
fpu_gp_save 20,$a0
fpu_gp_save 21,$a0
fpu_gp_save 22,$a0
fpu_gp_save 23,$a0
fpu_gp_save 24,$a0
fpu_gp_save 25,$a0
fpu_gp_save 26,$a0
fpu_gp_save 27,$a0
fpu_gp_save 28,$a0
fpu_gp_save 29,$a0
fpu_gp_save 30,$a0
fpu_gp_save 31,$a0
fpu_ct_save 1,$a0
fpu_ct_save 2,$a0
fpu_ct_save 3,$a0
fpu_ct_save 4,$a0
fpu_ct_save 5,$a0
fpu_ct_save 6,$a0
fpu_ct_save 7,$a0
fpu_ct_save 8,$a0
fpu_ct_save 9,$a0
fpu_ct_save 10,$a0
fpu_ct_save 11,$a0
fpu_ct_save 12,$a0
fpu_ct_save 13,$a0
fpu_ct_save 14,$a0
fpu_ct_save 15,$a0
fpu_ct_save 16,$a0
fpu_ct_save 17,$a0
fpu_ct_save 18,$a0
fpu_ct_save 19,$a0
fpu_ct_save 20,$a0
fpu_ct_save 21,$a0
fpu_ct_save 22,$a0
fpu_ct_save 23,$a0
fpu_ct_save 24,$a0
fpu_ct_save 25,$a0
fpu_ct_save 26,$a0
fpu_ct_save 27,$a0
fpu_ct_save 28,$a0
fpu_ct_save 29,$a0
fpu_ct_save 30,$a0
fpu_ct_save 31,$a0
#endif
j $ra
nop
.global fpu_context_restore
fpu_context_restore:
#ifdef ARCH_HAS_FPU
fpu_gp_restore 0,$a0
fpu_gp_restore 1,$a0
fpu_gp_restore 2,$a0
fpu_gp_restore 3,$a0
fpu_gp_restore 4,$a0
fpu_gp_restore 5,$a0
fpu_gp_restore 6,$a0
fpu_gp_restore 7,$a0
fpu_gp_restore 8,$a0
fpu_gp_restore 9,$a0
fpu_gp_restore 10,$a0
fpu_gp_restore 11,$a0
fpu_gp_restore 12,$a0
fpu_gp_restore 13,$a0
fpu_gp_restore 14,$a0
fpu_gp_restore 15,$a0
fpu_gp_restore 16,$a0
fpu_gp_restore 17,$a0
fpu_gp_restore 18,$a0
fpu_gp_restore 19,$a0
fpu_gp_restore 20,$a0
fpu_gp_restore 21,$a0
fpu_gp_restore 22,$a0
fpu_gp_restore 23,$a0
fpu_gp_restore 24,$a0
fpu_gp_restore 25,$a0
fpu_gp_restore 26,$a0
fpu_gp_restore 27,$a0
fpu_gp_restore 28,$a0
fpu_gp_restore 29,$a0
fpu_gp_restore 30,$a0
fpu_gp_restore 31,$a0
fpu_ct_restore 1,$a0
fpu_ct_restore 2,$a0
fpu_ct_restore 3,$a0
fpu_ct_restore 4,$a0
fpu_ct_restore 5,$a0
fpu_ct_restore 6,$a0
fpu_ct_restore 7,$a0
fpu_ct_restore 8,$a0
fpu_ct_restore 9,$a0
fpu_ct_restore 10,$a0
fpu_ct_restore 11,$a0
fpu_ct_restore 12,$a0
fpu_ct_restore 13,$a0
fpu_ct_restore 14,$a0
fpu_ct_restore 15,$a0
fpu_ct_restore 16,$a0
fpu_ct_restore 17,$a0
fpu_ct_restore 18,$a0
fpu_ct_restore 19,$a0
fpu_ct_restore 20,$a0
fpu_ct_restore 21,$a0
fpu_ct_restore 22,$a0
fpu_ct_restore 23,$a0
fpu_ct_restore 24,$a0
fpu_ct_restore 25,$a0
fpu_ct_restore 26,$a0
fpu_ct_restore 27,$a0
fpu_ct_restore 28,$a0
fpu_ct_restore 29,$a0
fpu_ct_restore 30,$a0
fpu_ct_restore 31,$a0
#endif
j $ra
nop

/tags/0.2.0/kernel/arch/mips32/src/exception.c
0,0 → 1,167
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/exception.h>
#include <arch/interrupt.h>
#include <panic.h>
#include <arch/cp0.h>
#include <arch/types.h>
#include <arch.h>
#include <debug.h>
#include <proc/thread.h>
#include <symtab.h>
#include <print.h>
#include <interrupt.h>
#include <func.h>
#include <console/kconsole.h>
#include <arch/debugger.h>
static char * exctable[] = {
"Interrupt","TLB Modified","TLB Invalid","TLB Invalid Store",
"Address Error - load/instr. fetch",
"Address Error - store",
"Bus Error - fetch instruction",
"Bus Error - data reference",
"Syscall",
"BreakPoint",
"Reserved Instruction",
"Coprocessor Unusable",
"Arithmetic Overflow",
"Trap",
"Virtual Coherency - instruction",
"Floating Point",
NULL, NULL, NULL, NULL, NULL, NULL, NULL,
"WatchHi/WatchLo", /* 23 */
NULL, NULL, NULL, NULL, NULL, NULL, NULL,
"Virtual Coherency - data",
};
static void print_regdump(istate_t *istate)
{
char *pcsymbol = "";
char *rasymbol = "";
char *s = get_symtab_entry(istate->epc);
if (s)
pcsymbol = s;
s = get_symtab_entry(istate->ra);
if (s)
rasymbol = s;
printf("PC: %#x(%s) RA: %#x(%s), SP(%p)\n", istate->epc, pcsymbol, istate->ra, rasymbol, istate->sp);
}
static void unhandled_exception(int n, istate_t *istate)
{
fault_if_from_uspace(istate, "unhandled exception %s", exctable[n]);
print_regdump(istate);
panic("unhandled exception %s\n", exctable[n]);
}
static void reserved_instr_exception(int n, istate_t *istate)
{
if (*((__u32 *)istate->epc) == 0x7c03e83b) {
ASSERT(THREAD);
istate->epc += 4;
istate->v1 = istate->k1;
} else
unhandled_exception(n, istate);
}
static void breakpoint_exception(int n, istate_t *istate)
{
#ifdef CONFIG_DEBUG
debugger_bpoint(istate);
#else
/* it is necessary to not re-execute BREAK instruction after
returning from Exception handler
(see page 138 in R4000 Manual for more information) */
istate->epc += 4;
#endif
}
static void tlbmod_exception(int n, istate_t *istate)
{
tlb_modified(istate);
}
static void tlbinv_exception(int n, istate_t *istate)
{
tlb_invalid(istate);
}
#ifdef CONFIG_FPU_LAZY
static void cpuns_exception(int n, istate_t *istate)
{
if (cp0_cause_coperr(cp0_cause_read()) == fpu_cop_id)
scheduler_fpu_lazy_request();
else {
fault_if_from_uspace(istate, "unhandled Coprocessor Unusable Exception");
panic("unhandled Coprocessor Unusable Exception\n");
}
}
#endif
static void interrupt_exception(int n, istate_t *istate)
{
__u32 cause;
int i;
/* decode interrupt number and process the interrupt */
cause = (cp0_cause_read() >> 8) &0xff;
for (i = 0; i < 8; i++)
if (cause & (1 << i))
exc_dispatch(i+INT_OFFSET, istate);
}
/** Handle syscall userspace call */
static void syscall_exception(int n, istate_t *istate)
{
panic("Syscall is handled through shortcut");
}
void exception_init(void)
{
int i;
/* Clear exception table */
for (i=0;i < IVT_ITEMS; i++)
exc_register(i, "undef", (iroutine) unhandled_exception);
exc_register(EXC_Bp, "bkpoint", (iroutine) breakpoint_exception);
exc_register(EXC_RI, "resinstr", (iroutine) reserved_instr_exception);
exc_register(EXC_Mod, "tlb_mod", (iroutine) tlbmod_exception);
exc_register(EXC_TLBL, "tlbinvl", (iroutine) tlbinv_exception);
exc_register(EXC_TLBS, "tlbinvl", (iroutine) tlbinv_exception);
exc_register(EXC_Int, "interrupt", (iroutine) interrupt_exception);
#ifdef CONFIG_FPU_LAZY
exc_register(EXC_CpU, "cpunus", (iroutine) cpuns_exception);
#endif
exc_register(EXC_Sys, "syscall", (iroutine) syscall_exception);
}

/tags/0.2.0/kernel/arch/mips32/src/mm/tlb.c
0,0 → 1,604
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/tlb.h>
#include <mm/asid.h>
#include <mm/tlb.h>
#include <mm/page.h>
#include <mm/as.h>
#include <arch/cp0.h>
#include <panic.h>
#include <arch.h>
#include <symtab.h>
#include <synch/spinlock.h>
#include <print.h>
#include <debug.h>
#include <align.h>
#include <interrupt.h>
static void tlb_refill_fail(istate_t *istate);
static void tlb_invalid_fail(istate_t *istate);
static void tlb_modified_fail(istate_t *istate);
static pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc);
static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn);
static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);
/** Initialize TLB
*
* Initialize TLB.
* Invalidate all entries and mark wired entries.
*/
void tlb_arch_init(void)
{
int i;
cp0_pagemask_write(TLB_PAGE_MASK_16K);
cp0_entry_hi_write(0);
cp0_entry_lo0_write(0);
cp0_entry_lo1_write(0);
/* Clear and initialize TLB. */
for (i = 0; i < TLB_ENTRY_COUNT; i++) {
cp0_index_write(i);
tlbwi();
}
/*
* The kernel is going to make use of some wired
* entries (e.g. mapping kernel stacks in kseg3).
*/
cp0_wired_write(TLB_WIRED);
}
/** Process TLB Refill Exception
*
* Process TLB Refill Exception.
*
* @param istate Interrupted register context.
*/
void tlb_refill(istate_t *istate)
{
entry_lo_t lo;
entry_hi_t hi;
asid_t asid;
__address badvaddr;
pte_t *pte;
int pfrc;
badvaddr = cp0_badvaddr_read();
spinlock_lock(&AS->lock);
asid = AS->asid;
spinlock_unlock(&AS->lock);
page_table_lock(AS, true);
pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
if (!pte) {
switch (pfrc) {
case AS_PF_FAULT:
goto fail;
break;
case AS_PF_DEFER:
/*
* The page fault came during copy_from_uspace()
* or copy_to_uspace().
*/
page_table_unlock(AS, true);
return;
default:
panic("unexpected pfrc (%d)\n", pfrc);
}
}
/*
* Record access to PTE.
*/
pte->a = 1;
prepare_entry_hi(&hi, asid, badvaddr);
prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
/*
* New entry is to be inserted into TLB
*/
cp0_entry_hi_write(hi.value);
if ((badvaddr/PAGE_SIZE) % 2 == 0) {
cp0_entry_lo0_write(lo.value);
cp0_entry_lo1_write(0);
}
else {
cp0_entry_lo0_write(0);
cp0_entry_lo1_write(lo.value);
}
cp0_pagemask_write(TLB_PAGE_MASK_16K);
tlbwr();
page_table_unlock(AS, true);
return;
fail:
page_table_unlock(AS, true);
tlb_refill_fail(istate);
}
/** Process TLB Invalid Exception
*
* Process TLB Invalid Exception.
*
* @param istate Interrupted register context.
*/
void tlb_invalid(istate_t *istate)
{
tlb_index_t index;
__address badvaddr;
entry_lo_t lo;
entry_hi_t hi;
pte_t *pte;
int pfrc;
badvaddr = cp0_badvaddr_read();
/*
* Locate the faulting entry in TLB.
*/
hi.value = cp0_entry_hi_read();
prepare_entry_hi(&hi, hi.asid, badvaddr);
cp0_entry_hi_write(hi.value);
tlbp();
index.value = cp0_index_read();
page_table_lock(AS, true);
/*
* Fail if the entry is not in TLB.
*/
if (index.p) {
printf("TLB entry not found.\n");
goto fail;
}
pte = find_mapping_and_check(badvaddr, PF_ACCESS_READ, istate, &pfrc);
if (!pte) {
switch (pfrc) {
case AS_PF_FAULT:
goto fail;
break;
case AS_PF_DEFER:
/*
* The page fault came during copy_from_uspace()
* or copy_to_uspace().
*/
page_table_unlock(AS, true);
return;
default:
panic("unexpected pfrc (%d)\n", pfrc);
}
}
/*
* Read the faulting TLB entry.
*/
tlbr();
/*
* Record access to PTE.
*/
pte->a = 1;
prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
/*
* The entry is to be updated in TLB.
*/
if ((badvaddr/PAGE_SIZE) % 2 == 0)
cp0_entry_lo0_write(lo.value);
else
cp0_entry_lo1_write(lo.value);
cp0_pagemask_write(TLB_PAGE_MASK_16K);
tlbwi();
page_table_unlock(AS, true);
return;
fail:
page_table_unlock(AS, true);
tlb_invalid_fail(istate);
}
/** Process TLB Modified Exception
*
* Process TLB Modified Exception.
*
* @param istate Interrupted register context.
*/
void tlb_modified(istate_t *istate)
{
tlb_index_t index;
__address badvaddr;
entry_lo_t lo;
entry_hi_t hi;
pte_t *pte;
int pfrc;
badvaddr = cp0_badvaddr_read();
/*
* Locate the faulting entry in TLB.
*/
hi.value = cp0_entry_hi_read();
prepare_entry_hi(&hi, hi.asid, badvaddr);
cp0_entry_hi_write(hi.value);
tlbp();
index.value = cp0_index_read();
page_table_lock(AS, true);
/*
* Fail if the entry is not in TLB.
*/
if (index.p) {
printf("TLB entry not found.\n");
goto fail;
}
pte = find_mapping_and_check(badvaddr, PF_ACCESS_WRITE, istate, &pfrc);
if (!pte) {
switch (pfrc) {
case AS_PF_FAULT:
goto fail;
break;
case AS_PF_DEFER:
/*
* The page fault came during copy_from_uspace()
* or copy_to_uspace().
*/
page_table_unlock(AS, true);
return;
default:
panic("unexpected pfrc (%d)\n", pfrc);
}
}
/*
* Fail if the page is not writable.
*/
if (!pte->w)
goto fail;
/*
* Read the faulting TLB entry.
*/
tlbr();
/*
* Record access and write to PTE.
*/
pte->a = 1;
pte->d = 1;
prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
/*
* The entry is to be updated in TLB.
*/
if ((badvaddr/PAGE_SIZE) % 2 == 0)
cp0_entry_lo0_write(lo.value);
else
cp0_entry_lo1_write(lo.value);
cp0_pagemask_write(TLB_PAGE_MASK_16K);
tlbwi();
page_table_unlock(AS, true);
return;
fail:
page_table_unlock(AS, true);
tlb_modified_fail(istate);
}
void tlb_refill_fail(istate_t *istate)
{
char *symbol = "";
char *sym2 = "";
char *s = get_symtab_entry(istate->epc);
if (s)
symbol = s;
s = get_symtab_entry(istate->ra);
if (s)
sym2 = s;
fault_if_from_uspace(istate, "TLB Refill Exception on %P", cp0_badvaddr_read());
panic("%X: TLB Refill Exception at %X(%s<-%s)\n", cp0_badvaddr_read(), istate->epc, symbol, sym2);
}
void tlb_invalid_fail(istate_t *istate)
{
char *symbol = "";
char *s = get_symtab_entry(istate->epc);
if (s)
symbol = s;
fault_if_from_uspace(istate, "TLB Invalid Exception on %P", cp0_badvaddr_read());
panic("%X: TLB Invalid Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
}
void tlb_modified_fail(istate_t *istate)
{
char *symbol = "";
char *s = get_symtab_entry(istate->epc);
if (s)
symbol = s;
fault_if_from_uspace(istate, "TLB Modified Exception on %P", cp0_badvaddr_read());
panic("%X: TLB Modified Exception at %X(%s)\n", cp0_badvaddr_read(), istate->epc, symbol);
}
/** Try to find PTE for faulting address
*
* Try to find PTE for faulting address.
* The AS->lock must be held on entry to this function.
*
* @param badvaddr Faulting virtual address.
* @param access Access mode that caused the fault.
* @param istate Pointer to interrupted state.
* @param pfrc Pointer to variable where as_page_fault() return code will be stored.
*
* @return PTE on success, NULL otherwise.
*/
pte_t *find_mapping_and_check(__address badvaddr, int access, istate_t *istate, int *pfrc)
{
entry_hi_t hi;
pte_t *pte;
hi.value = cp0_entry_hi_read();
/*
* Handler cannot succeed if the ASIDs don't match.
*/
if (hi.asid != AS->asid) {
printf("EntryHi.asid=%d, AS->asid=%d\n", hi.asid, AS->asid);
return NULL;
}
/*
* Check if the mapping exists in page tables.
*/
pte = page_mapping_find(AS, badvaddr);
if (pte && pte->p) {
/*
* Mapping found in page tables.
* Immediately succeed.
*/
return pte;
} else {
int rc;
/*
* Mapping not found in page tables.
* Resort to higher-level page fault handler.
*/
page_table_unlock(AS, true);
switch (rc = as_page_fault(badvaddr, access, istate)) {
case AS_PF_OK:
/*
* The higher-level page fault handler succeeded,
* The mapping ought to be in place.
*/
page_table_lock(AS, true);
pte = page_mapping_find(AS, badvaddr);
ASSERT(pte && pte->p);
return pte;
break;
case AS_PF_DEFER:
page_table_lock(AS, true);
*pfrc = AS_PF_DEFER;
return NULL;
break;
case AS_PF_FAULT:
page_table_lock(AS, true);
printf("Page fault.\n");
*pfrc = AS_PF_FAULT;
return NULL;
break;
default:
panic("unexpected rc (%d)\n", rc);
}
}
}
void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn)
{
lo->value = 0;
lo->g = g;
lo->v = v;
lo->d = d;
lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
lo->pfn = pfn;
}
void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)
{
hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
hi->asid = asid;
}
/** Print contents of TLB. */
void tlb_print(void)
{
page_mask_t mask;
entry_lo_t lo0, lo1;
entry_hi_t hi, hi_save;
int i;
hi_save.value = cp0_entry_hi_read();
printf("TLB:\n");
for (i = 0; i < TLB_ENTRY_COUNT; i++) {
cp0_index_write(i);
tlbr();
mask.value = cp0_pagemask_read();
hi.value = cp0_entry_hi_read();
lo0.value = cp0_entry_lo0_read();
lo1.value = cp0_entry_lo1_read();
printf("%d: asid=%d, vpn2=%d, mask=%d\tg[0]=%d, v[0]=%d, d[0]=%d, c[0]=%hhd, pfn[0]=%d\n"
"\t\t\t\tg[1]=%d, v[1]=%d, d[1]=%d, c[1]=%hhd, pfn[1]=%d\n",
i, hi.asid, hi.vpn2, mask.mask, lo0.g, lo0.v, lo0.d, lo0.c, lo0.pfn,
lo1.g, lo1.v, lo1.d, lo1.c, lo1.pfn);
}
cp0_entry_hi_write(hi_save.value);
}
/** Invalidate all not wired TLB entries. */
void tlb_invalidate_all(void)
{
ipl_t ipl;
entry_lo_t lo0, lo1;
entry_hi_t hi_save;
int i;
hi_save.value = cp0_entry_hi_read();
ipl = interrupts_disable();
for (i = TLB_WIRED; i < TLB_ENTRY_COUNT; i++) {
cp0_index_write(i);
tlbr();
lo0.value = cp0_entry_lo0_read();
lo1.value = cp0_entry_lo1_read();
lo0.v = 0;
lo1.v = 0;
cp0_entry_lo0_write(lo0.value);
cp0_entry_lo1_write(lo1.value);
tlbwi();
}
interrupts_restore(ipl);
cp0_entry_hi_write(hi_save.value);
}
/** Invalidate all TLB entries belonging to specified address space.
*
* @param asid Address space identifier.
*/
void tlb_invalidate_asid(asid_t asid)
{
ipl_t ipl;
entry_lo_t lo0, lo1;
entry_hi_t hi, hi_save;
int i;
ASSERT(asid != ASID_INVALID);
hi_save.value = cp0_entry_hi_read();
ipl = interrupts_disable();
for (i = 0; i < TLB_ENTRY_COUNT; i++) {
cp0_index_write(i);
tlbr();
hi.value = cp0_entry_hi_read();
if (hi.asid == asid) {
lo0.value = cp0_entry_lo0_read();
lo1.value = cp0_entry_lo1_read();
lo0.v = 0;
lo1.v = 0;
cp0_entry_lo0_write(lo0.value);
cp0_entry_lo1_write(lo1.value);
tlbwi();
}
}
interrupts_restore(ipl);
cp0_entry_hi_write(hi_save.value);
}
/** Invalidate TLB entries for specified page range belonging to specified address space.
*
* @param asid Address space identifier.
* @param page First page whose TLB entry is to be invalidated.
* @param cnt Number of entries to invalidate.
*/
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
int i;
ipl_t ipl;
entry_lo_t lo0, lo1;
entry_hi_t hi, hi_save;
tlb_index_t index;
ASSERT(asid != ASID_INVALID);
hi_save.value = cp0_entry_hi_read();
ipl = interrupts_disable();
for (i = 0; i < cnt+1; i+=2) {
hi.value = 0;
prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
cp0_entry_hi_write(hi.value);
tlbp();
index.value = cp0_index_read();
if (!index.p) {
/* Entry was found, index register contains valid index. */
tlbr();
lo0.value = cp0_entry_lo0_read();
lo1.value = cp0_entry_lo1_read();
lo0.v = 0;
lo1.v = 0;
cp0_entry_lo0_write(lo0.value);
cp0_entry_lo1_write(lo1.value);
tlbwi();
}
}
interrupts_restore(ipl);
cp0_entry_hi_write(hi_save.value);
}

/tags/0.2.0/kernel/arch/mips32/src/mm/page.c
0,0 → 1,45
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/page.h>
#include <genarch/mm/page_pt.h>
#include <mm/page.h>
void page_arch_init(void)
{
page_mapping_operations = &pt_mapping_operations;
}
/** Map device into kernel space
* - on mips, all devices are already mapped into kernel space,
* translate the physical address to uncached area
*/
__address hw_map(__address physaddr, size_t size)
{
return physaddr + 0xa0000000;
}

/tags/0.2.0/kernel/arch/mips32/src/mm/frame.c
0,0 → 1,51
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/frame.h>
#include <mm/frame.h>
#include <config.h>
#include <arch/drivers/arc.h>
/** Create memory zones
*
* If ARC is known, read information from ARC, otherwise
* assume some defaults.
* - blacklist first FRAME because there is an exception vector
*/
void frame_arch_init(void)
{
if (arc_enabled())
arc_frame_init();
else {
zone_create(0, ADDR2PFN(config.memory_size), 1, 0);
/*
* Blacklist interrupt vektor
*/
frame_mark_unavailable(0, 1);
}
}

/tags/0.2.0/kernel/arch/mips32/src/mm/as.c
0,0 → 1,68
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/as.h>
#include <genarch/mm/as_pt.h>
#include <genarch/mm/asid_fifo.h>
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <mm/as.h>
#include <arch/cp0.h>
#include <arch.h>
/** Architecture dependent address space init. */
void as_arch_init(void)
{
as_operations = &as_pt_operations;
asid_fifo_init();
}
/** Install address space.
*
* Install ASID.
*
* @param as Address space structure.
*/
void as_install_arch(as_t *as)
{
entry_hi_t hi;
ipl_t ipl;
/*
* Install ASID.
*/
hi.value = cp0_entry_hi_read();
ipl = interrupts_disable();
spinlock_lock(&as->lock);
hi.asid = as->asid;
cp0_entry_hi_write(hi.value);
spinlock_unlock(&as->lock);
interrupts_restore(ipl);
}

/tags/0.2.0/kernel/arch/mips32/src/console.c
0,0 → 1,59
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <console/console.h>
#include <arch/console.h>
#include <arch/drivers/arc.h>
#include <arch/drivers/serial.h>
#include <arch/drivers/msim.h>
void console_init(void)
{
if (arc_enabled()) {
arc_console();
} else if (serial_init()) {
serial_console();
} else {
msim_console();
}
}
/** Acquire console back for kernel
*
*/
void arch_grab_console(void)
{
msim_kbd_grab();
}
/** Return console to userspace
*
*/
void arch_release_console(void)
{
msim_kbd_release();
}

/tags/0.2.0/kernel/arch/mips32/src/drivers/msim.c
0,0 → 1,120
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <interrupt.h>
#include <console/chardev.h>
#include <arch/drivers/msim.h>
#include <arch/cp0.h>
#include <console/console.h>
static chardev_t console;
static void msim_write(chardev_t *dev, const char ch);
static void msim_enable(chardev_t *dev);
static void msim_disable(chardev_t *dev);
static char msim_do_read(chardev_t *dev);
static chardev_operations_t msim_ops = {
.resume = msim_enable,
.suspend = msim_disable,
.write = msim_write,
.read = msim_do_read,
};
/** Putchar that works with MSIM & gxemul */
void msim_write(chardev_t *dev, const char ch)
{
*((char *) MSIM_VIDEORAM) = ch;
}
/* Called from getc(). */
void msim_enable(chardev_t *dev)
{
cp0_unmask_int(MSIM_KBD_IRQ);
}
/* Called from getc(). */
void msim_disable(chardev_t *dev)
{
cp0_mask_int(MSIM_KBD_IRQ);
}
#include <print.h>
/** Read character using polling, assume interrupts disabled */
static char msim_do_read(chardev_t *dev)
{
char ch;
while (1) {
ch = *((volatile char *) MSIM_KBD_ADDRESS);
if (ch) {
if (ch == '\r')
return '\n';
if (ch == 0x7f)
return '\b';
return ch;
}
}
}
/** Process keyboard interrupt. */
static void msim_interrupt(int n, istate_t *istate)
{
char ch = 0;
ch = *((char *) MSIM_KBD_ADDRESS);
if (ch =='\r')
ch = '\n';
if (ch == 0x7f)
ch = '\b';
chardev_push_character(&console, ch);
}
/* Return console object representing msim console */
void msim_console(void)
{
chardev_initialize("msim_console", &console, &msim_ops);
int_register(MSIM_KBD_IRQ, "msim_kbd", msim_interrupt);
cp0_unmask_int(MSIM_KBD_IRQ);
stdin = &console;
stdout = &console;
}
static iroutine oldvector;
void msim_kbd_grab(void)
{
oldvector = int_register(MSIM_KBD_IRQ, "msim_kbd", msim_interrupt);
}
void msim_kbd_release(void)
{
int_register(MSIM_KBD_IRQ, "user_interrupt", oldvector);
}

/tags/0.2.0/kernel/arch/mips32/src/drivers/arc.c
0,0 → 1,403
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/drivers/arc.h>
#include <arch/mm/page.h>
#include <print.h>
#include <arch.h>
#include <arch/byteorder.h>
#include <arch/mm/frame.h>
#include <mm/frame.h>
#include <interrupt.h>
#include <align.h>
#include <console/console.h>
#include <console/kconsole.h>
#include <console/cmd.h>
#include <mm/slab.h>
/* This is a good joke, SGI HAS different types than NT bioses... */
/* Here is the SGI type */
static char *basetypes[] = {
"ExceptionBlock",
"SystemParameterBlock",
"FreeContiguous",
"FreeMemory",
"BadMemory",
"LoadedProgram",
"FirmwareTemporary",
"FirmwarePermanent"
};
static char *ctypes[] = {
"ARC_type",
"CPU_type",
"FPU_type",
"PrimaryICache",
"PrimaryDCache",
"SecondaryICache",
"SecondaryDCache",
"SecondaryCache",
"Memory",
"EISAAdapter",
"TCAdapter",
"SCSIAdapter",
"DTIAdapter",
"MultiFunctionAdapter",
"DiskController",
"TapeController",
"CDROMController",
"WORMController",
"SerialController",
"NetworkController",
"DisplayController",
"ParallelController",
"PointerController",
"KeyboardController",
"AudioController",
"OtherController",
"DiskPeripheral",
"FloppyDiskPeripheral",
"TapePeripheral",
"ModemPeripheral",
"MonitorPeripheral",
"PrinterPeripheral",
"PointerPeripheral",
"KeyboardPeripheral",
"TerminalPeripheral",
"OtherPeripheral",
"LinePeripheral",
"NetworkPeripheral"
"OtherPeripheral",
"XTalkAdapter",
"PCIAdapter",
"GIOAdapter",
"TPUAdapter",
"Anonymous"
};
static arc_sbp *sbp = (arc_sbp *)PA2KA(0x1000);
static arc_func_vector_t *arc_entry;
static void arc_putchar(char ch);
/** Return true if ARC is available */
int arc_enabled(void)
{
return sbp != NULL;
}
/** Print configuration data that ARC reports about component */
static void arc_print_confdata(arc_component *c)
{
cm_resource_list *configdata;
int i;
if (!c->configdatasize)
return; /* No configuration data */
configdata = malloc(c->configdatasize, 0);
if (arc_entry->getconfigurationdata(configdata, c)) {
free(configdata);
return;
}
/* Does not seem to return meaningful data, don't use now */
free(configdata);
return;
for (i=0; i < configdata->count; i++) {
switch (configdata->descr[i].type) {
case CmResourceTypePort:
printf("Port: %p-size:%d ",
(__address)configdata->descr[i].u.port.start,
configdata->descr[i].u.port.length);
break;
case CmResourceTypeInterrupt:
printf("Irq: level(%d) vector(%d) ",
configdata->descr[i].u.interrupt.level,
configdata->descr[i].u.interrupt.vector);
break;
case CmResourceTypeMemory:
printf("Memory: %p-size:%d ",
(__address)configdata->descr[i].u.port.start,
configdata->descr[i].u.port.length);
break;
default:
break;
}
}
free(configdata);
}
/** Print information about component */
static void arc_print_component(arc_component *c)
{
int i;
printf("%s: ",ctypes[c->type]);
for (i=0;i < c->identifier_len;i++)
printf("%c",c->identifier[i]);
printf(" ");
arc_print_confdata(c);
printf("\n");
}
/**
* Read from ARC bios configuration data and print it
*/
static int cmd_arc_print_devices(cmd_arg_t *argv)
{
arc_component *c,*next;
c = arc_entry->getchild(NULL);
while (c) {
arc_print_component(c);
next = arc_entry->getchild(c);
while (!next) {
next = arc_entry->getpeer(c);
if (!next)
c = arc_entry->getparent(c);
if (!c)
return 0;
}
c = next;
}
return 1;
}
static cmd_info_t devlist_info = {
.name = "arcdevlist",
.description = "Print arc device list",
.func = cmd_arc_print_devices,
.argc = 0
};
/** Read from arc bios memory map and print it
*
*/
static int cmd_arc_print_memmap(cmd_arg_t *argv)
{
arc_memdescriptor_t *desc;
printf("Memory map:\n");
desc = arc_entry->getmemorydescriptor(NULL);
while (desc) {
printf("%s: %d(%p) (size: %dKB)\n",basetypes[desc->type],
desc->basepage * ARC_FRAME,
desc->basepage * ARC_FRAME,
desc->basecount*ARC_FRAME/1024);
desc = arc_entry->getmemorydescriptor(desc);
}
return 1;
}
static cmd_info_t memmap_info = {
.name = "arcmemmap",
.description = "Print arc memory map",
.func = cmd_arc_print_memmap,
.argc = 0
};
/** Print charactor to console */
static void arc_putchar(char ch)
{
__u32 cnt;
ipl_t ipl;
/* TODO: Should be spinlock? */
ipl = interrupts_disable();
arc_entry->write(1, &ch, 1, &cnt);
interrupts_restore(ipl);
}
static int cmd_reboot(cmd_arg_t *argv)
{
arc_entry->reboot();
return 0;
}
static cmd_info_t reboot_info = {
.name = "reboot",
.description = "Reboot computer",
.func = cmd_reboot,
.argc = 0
};
/** Initialize ARC structure
*
* @return 0 - ARC OK, -1 - ARC does not exist
*/
int arc_init(void)
{
if (sbp->signature != ARC_MAGIC) {
sbp = NULL;
return -1;
}
arc_entry = sbp->firmwarevector;
arc_putchar('A');
arc_putchar('R');
arc_putchar('C');
arc_putchar('\n');
/* Add command for resetting the computer */
cmd_initialize(&reboot_info);
cmd_register(&reboot_info);
cmd_initialize(&memmap_info);
cmd_register(&memmap_info);
cmd_initialize(&devlist_info);
cmd_register(&devlist_info);
return 0;
}
static bool kbd_polling_enabled;
static chardev_t console;
/** Try to get character, return character or -1 if not available */
static void arc_keyboard_poll(void)
{
char ch;
__u32 count;
long result;
if (! kbd_polling_enabled)
return;
if (arc_entry->getreadstatus(0))
return;
result = arc_entry->read(0, &ch, 1, &count);
if (result || count!=1) {
return;
}
if (ch == '\r')
ch = '\n';
if (ch == 0x7f)
ch = '\b';
chardev_push_character(&console, ch);
}
static char arc_read(chardev_t *dev)
{
char ch;
__u32 count;
long result;
result = arc_entry->read(0, &ch, 1, &count);
if (result || count!=1) {
printf("Error reading from ARC keyboard.\n");
cpu_halt();
}
if (ch == '\r')
return '\n';
if (ch == 0x7f)
return '\b';
return ch;
}
static void arc_write(chardev_t *dev, const char ch)
{
arc_putchar(ch);
}
static void arc_enable(chardev_t *dev)
{
kbd_polling_enabled = true;
}
static void arc_disable(chardev_t *dev)
{
kbd_polling_enabled = false;
}
static chardev_operations_t arc_ops = {
.resume = arc_enable,
.suspend = arc_disable,
.write = arc_write,
.read = arc_read
};
iroutine old_timer;
/** Do polling on timer interrupt */
static void timer_replace(int n, istate_t *istate)
{
arc_keyboard_poll();
old_timer(n, istate);
arc_keyboard_poll();
}
void arc_console(void)
{
kbd_polling_enabled = true;
chardev_initialize("arc_console", &console, &arc_ops);
old_timer = int_register(TIMER_IRQ, "arc_kb_poll", timer_replace);
stdin = &console;
stdout = &console;
}
/* Initialize frame zones from ARC firmware.
* In the future we may use even the FirmwareTemporary regions,
* currently we use the FreeMemory (what about the LoadedProgram?)
*/
void arc_frame_init(void)
{
arc_memdescriptor_t *desc;
int total = 0;
__address base;
size_t basesize;
desc = arc_entry->getmemorydescriptor(NULL);
while (desc) {
if (desc->type == FreeMemory ||
desc->type == FreeContiguous) {
base = desc->basepage*ARC_FRAME;
basesize = desc->basecount*ARC_FRAME;
if (base % FRAME_SIZE ) {
basesize -= FRAME_SIZE - (base % FRAME_SIZE);
base = ALIGN_UP(base, FRAME_SIZE);
}
basesize = ALIGN_DOWN(basesize, FRAME_SIZE);
total += basesize;
zone_create(ADDR2PFN(base), SIZE2FRAMES(basesize),
ADDR2PFN(base), 0);
}
desc = arc_entry->getmemorydescriptor(desc);
}
config.memory_size = total;
}

/tags/0.2.0/kernel/arch/mips32/src/drivers/serial.c
0,0 → 1,138
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <interrupt.h>
#include <arch/cp0.h>
#include <arch/drivers/serial.h>
#include <console/chardev.h>
#include <console/console.h>
static chardev_t console;
static serial_t sconf[SERIAL_MAX];
static bool kb_enabled;
static void serial_write(chardev_t *d, const char ch)
{
serial_t *sd = (serial_t *)d->data;
if (ch == '\n')
serial_write(d, '\r');
/* Wait until transmit buffer empty */
while (! (SERIAL_READ_LSR(sd->port) & (1<<TRANSMIT_EMPTY_BIT)))
;
SERIAL_WRITE(sd->port, ch);
}
static void serial_enable(chardev_t *d)
{
kb_enabled = true;
}
static void serial_disable(chardev_t *d)
{
kb_enabled = false;
}
int serial_init(void)
{
int i = 0;
if (SERIAL_READ_LSR(SERIAL_COM1) == 0x60) {
sconf[i].port = SERIAL_COM1;
sconf[i].irq = SERIAL_COM1_IRQ;
/* Enable interrupt on available data */
i++;
}
return i;
}
/** Read character from serial port, wait until available */
static char serial_do_read(chardev_t *dev)
{
serial_t *sd = (serial_t *)dev->data;
char ch;
while (!(SERIAL_READ_LSR(sd->port) & 1))
;
ch = SERIAL_READ(sd->port);
if (ch =='\r')
ch = '\n';
return ch;
}
/** Process keyboard interrupt. Does not work in simics? */
static void serial_interrupt(int n, void *stack)
{
serial_t *sd = (serial_t *)console.data;
char ch;
if (!(SERIAL_READ_LSR(sd->port) & 1))
return;
ch = SERIAL_READ(sd->port);
if (ch =='\r')
ch = '\n';
chardev_push_character(&console, ch);
}
static chardev_operations_t serial_ops = {
.resume = serial_enable,
.suspend = serial_disable,
.write = serial_write,
.read = serial_do_read
};
iroutine old_timer;
/** Do polling on timer interrupt */
static void timer_replace(int n, istate_t *istate)
{
old_timer(n, istate);
serial_interrupt(n, istate);
}
void serial_console(void)
{
serial_t *sd = &sconf[0];
chardev_initialize("serial_console", &console, &serial_ops);
console.data = sd;
kb_enabled = true;
// int_register(2, "serial_drvr", serial_interrupt);
/* I don't know why, but the serial interrupts simply
* don't work on simics
*/
old_timer = int_register(TIMER_IRQ, "serial_drvr_poll", timer_replace);
stdin = &console;
stdout = &console;
}

/tags/0.2.0/kernel/arch/mips32/src/interrupt.c
0,0 → 1,136
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <interrupt.h>
#include <arch/interrupt.h>
#include <arch/types.h>
#include <arch.h>
#include <arch/cp0.h>
#include <time/clock.h>
#include <arch/drivers/arc.h>
#include <ipc/sysipc.h>
/** Disable interrupts.
*
* @return Old interrupt priority level.
*/
ipl_t interrupts_disable(void)
{
ipl_t ipl = (ipl_t) cp0_status_read();
cp0_status_write(ipl & ~cp0_status_ie_enabled_bit);
return ipl;
}
/** Enable interrupts.
*
* @return Old interrupt priority level.
*/
ipl_t interrupts_enable(void)
{
ipl_t ipl = (ipl_t) cp0_status_read();
cp0_status_write(ipl | cp0_status_ie_enabled_bit);
return ipl;
}
/** Restore interrupt priority level.
*
* @param ipl Saved interrupt priority level.
*/
void interrupts_restore(ipl_t ipl)
{
cp0_status_write(cp0_status_read() | (ipl & cp0_status_ie_enabled_bit));
}
/** Read interrupt priority level.
*
* @return Current interrupt priority level.
*/
ipl_t interrupts_read(void)
{
return cp0_status_read();
}
/* TODO: This is SMP unsafe!!! */
static unsigned long nextcount;
/** Start hardware clock */
static void timer_start(void)
{
nextcount = cp0_compare_value + cp0_count_read();
cp0_compare_write(nextcount);
}
static void timer_exception(int n, istate_t *istate)
{
unsigned long drift;
drift = cp0_count_read() - nextcount;
while (drift > cp0_compare_value) {
drift -= cp0_compare_value;
CPU->missed_clock_ticks++;
}
nextcount = cp0_count_read() + cp0_compare_value - drift;
cp0_compare_write(nextcount);
clock();
}
static void swint0(int n, istate_t *istate)
{
cp0_cause_write(cp0_cause_read() & ~(1 << 8)); /* clear SW0 interrupt */
ipc_irq_send_notif(0);
}
static void swint1(int n, istate_t *istate)
{
cp0_cause_write(cp0_cause_read() & ~(1 << 9)); /* clear SW1 interrupt */
ipc_irq_send_notif(1);
}
/* Initialize basic tables for exception dispatching */
void interrupt_init(void)
{
int_register(TIMER_IRQ, "timer", timer_exception);
int_register(0, "swint0", swint0);
int_register(1, "swint1", swint1);
timer_start();
}
static void ipc_int(int n, istate_t *istate)
{
ipc_irq_send_notif(n-INT_OFFSET);
}
/* Reregister irq to be IPC-ready */
void irq_ipc_bind_arch(__native irq)
{
/* Do not allow to redefine timer */
/* Swint0, Swint1 are already handled */
if (irq == TIMER_IRQ || irq < 2)
return;
int_register(irq, "ipc_int", ipc_int);
}

/tags/0.2.0/kernel/arch/mips32/src/start.S
0,0 → 1,315
#
# Copyright (C) 2003-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/regname.h>
#include <arch/mm/page.h>
#include <arch/asm/boot.h>
#include <arch/context_offset.h>
.text
.set noat
.set noreorder
.set nomacro
.global kernel_image_start
.global tlb_refill_entry
.global cache_error_entry
.global exception_entry
.global userspace_asm
# Which status bits should are thread-local
#define REG_SAVE_MASK 0x1f # KSU(UM), EXL, ERL, IE
# Save registers to space defined by \r
# We will change status: Disable ERL,EXL,UM,IE
# These changes will be automatically reversed in REGISTER_LOAD
# SP is NOT saved as part of these registers
.macro REGISTERS_STORE_AND_EXC_RESET r
sw $at,EOFFSET_AT(\r)
sw $v0,EOFFSET_V0(\r)
sw $v1,EOFFSET_V1(\r)
sw $a0,EOFFSET_A0(\r)
sw $a1,EOFFSET_A1(\r)
sw $a2,EOFFSET_A2(\r)
sw $a3,EOFFSET_A3(\r)
sw $t0,EOFFSET_T0(\r)
sw $t1,EOFFSET_T1(\r)
sw $t2,EOFFSET_T2(\r)
sw $t3,EOFFSET_T3(\r)
sw $t4,EOFFSET_T4(\r)
sw $t5,EOFFSET_T5(\r)
sw $t6,EOFFSET_T6(\r)
sw $t7,EOFFSET_T7(\r)
sw $t8,EOFFSET_T8(\r)
sw $t9,EOFFSET_T9(\r)
mflo $at
sw $at, EOFFSET_LO(\r)
mfhi $at
sw $at, EOFFSET_HI(\r)
#ifdef CONFIG_DEBUG_ALLREGS
sw $s0,EOFFSET_S0(\r)
sw $s1,EOFFSET_S1(\r)
sw $s2,EOFFSET_S2(\r)
sw $s3,EOFFSET_S3(\r)
sw $s4,EOFFSET_S4(\r)
sw $s5,EOFFSET_S5(\r)
sw $s6,EOFFSET_S6(\r)
sw $s7,EOFFSET_S7(\r)
sw $s8,EOFFSET_S8(\r)
#endif
sw $gp,EOFFSET_GP(\r)
sw $ra,EOFFSET_RA(\r)
sw $k1,EOFFSET_K1(\r)
mfc0 $t0, $status
mfc0 $t1, $epc
and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE
li $t3, ~(0x1f)
and $t0, $t0, $t3 # Clear KSU,EXL,ERL,IE
sw $t2,EOFFSET_STATUS(\r)
sw $t1,EOFFSET_EPC(\r)
mtc0 $t0, $status
.endm
.macro REGISTERS_LOAD r
# Update only UM,EXR,IE from status, the rest
# is controlled by OS and not bound to task
mfc0 $t0, $status
lw $t1,EOFFSET_STATUS(\r)
li $t2, ~REG_SAVE_MASK # Mask UM,EXL,ERL,IE
and $t0, $t0, $t2
or $t0, $t0, $t1 # Copy UM,EXL,ERL,IE from saved status
mtc0 $t0, $status
lw $v0,EOFFSET_V0(\r)
lw $v1,EOFFSET_V1(\r)
lw $a0,EOFFSET_A0(\r)
lw $a1,EOFFSET_A1(\r)
lw $a2,EOFFSET_A2(\r)
lw $a3,EOFFSET_A3(\r)
lw $t0,EOFFSET_T0(\r)
lw $t1,EOFFSET_T1(\r)
lw $t2,EOFFSET_T2(\r)
lw $t3,EOFFSET_T3(\r)
lw $t4,EOFFSET_T4(\r)
lw $t5,EOFFSET_T5(\r)
lw $t6,EOFFSET_T6(\r)
lw $t7,EOFFSET_T7(\r)
lw $t8,EOFFSET_T8(\r)
lw $t9,EOFFSET_T9(\r)
#ifdef CONFIG_DEBUG_ALLREGS
lw $s0,EOFFSET_S0(\r)
lw $s1,EOFFSET_S1(\r)
lw $s2,EOFFSET_S2(\r)
lw $s3,EOFFSET_S3(\r)
lw $s4,EOFFSET_S4(\r)
lw $s5,EOFFSET_S5(\r)
lw $s6,EOFFSET_S6(\r)
lw $s7,EOFFSET_S7(\r)
lw $s8,EOFFSET_S8(\r)
#endif
lw $gp,EOFFSET_GP(\r)
lw $ra,EOFFSET_RA(\r)
lw $k1,EOFFSET_K1(\r)
lw $at,EOFFSET_LO(\r)
mtlo $at
lw $at,EOFFSET_HI(\r)
mthi $at
lw $at,EOFFSET_EPC(\r)
mtc0 $at, $epc
lw $at,EOFFSET_AT(\r)
lw $sp,EOFFSET_SP(\r)
.endm
# Move kernel stack pointer address to register K0
# - if we are in user mode, load the appropriate stack
# address
.macro KERNEL_STACK_TO_K0
# If we are in user mode
mfc0 $k0, $status
andi $k0, 0x10
beq $k0, $0, 1f
add $k0, $sp, 0
# Move $k0 pointer to kernel stack
lui $k0, %hi(supervisor_sp)
ori $k0, $k0, %lo(supervisor_sp)
# Move $k0 (superveisor_sp)
lw $k0, 0($k0)
1:
.endm
.org 0x0
kernel_image_start:
/* Load temporary stack */
lui $sp, %hi(end_stack)
ori $sp, $sp, %lo(end_stack)
/* Not sure about this, but might be needed for PIC code???? */
lui $gp, 0x8000
jal arch_pre_main
nop
j main_bsp
nop
.space TEMP_STACK_SIZE
end_stack:
tlb_refill_entry:
j tlb_refill_handler
nop
cache_error_entry:
j cache_error_handler
nop
exception_entry:
j exception_handler
nop
exception_handler:
KERNEL_STACK_TO_K0
sub $k0, REGISTER_SPACE
sw $sp,EOFFSET_SP($k0)
move $sp, $k0
mfc0 $k0, $cause
sra $k0, $k0, 0x2 # cp0_exc_cause() part 1
andi $k0, $k0, 0x1f # cp0_exc_cause() part 2
sub $k0, 8 # 8=SYSCALL
beqz $k0, syscall_shortcut
add $k0, 8 # Revert $k0 back to correct exc number
REGISTERS_STORE_AND_EXC_RESET $sp
move $a1, $sp
jal exc_dispatch # exc_dispatch(excno, register_space)
move $a0, $k0
REGISTERS_LOAD $sp
# The $sp is automatically restored to former value
eret
# it seems that mips reserves some space on stack for varfuncs???
#define SS_ARG4 16
#define SS_SP EOFFSET_SP
#define SS_STATUS EOFFSET_STATUS
#define SS_EPC EOFFSET_EPC
#define SS_K1 EOFFSET_K1
syscall_shortcut:
# We have a lot of space on the stack, with free use
mfc0 $t1, $epc
mfc0 $t0, $status
sw $t1,SS_EPC($sp) # Save EPC
sw $k1,SS_K1($sp) # Save k1, which is not saved during context switch
and $t2, $t0, REG_SAVE_MASK # Save only KSU,EXL,ERL,IE
li $t3, ~(0x1f)
and $t0, $t0, $t3 # Clear KSU,EXL,ERL
ori $t0, $t0, 0x1 # Set IE
sw $t2,SS_STATUS($sp)
mtc0 $t0, $status
# CALL Syscall handler
jal syscall_handler
sw $v0, SS_ARG4($sp) # save v0 - arg4 to stack
# restore status
mfc0 $t0, $status
lw $t1,SS_STATUS($sp)
# Change back to EXL=1(from last exception), otherwise
# an interrupt could rewrite the CP0-EPC
li $t2, ~REG_SAVE_MASK # Mask UM,EXL,ERL,IE
and $t0, $t0, $t2
or $t0, $t0, $t1 # Copy UM,EXL,ERL,IE from saved status
mtc0 $t0, $status
# restore epc+4
lw $t0,SS_EPC($sp)
lw $k1,SS_K1($sp)
addi $t0, $t0, 4
mtc0 $t0, $epc
lw $sp,SS_SP($sp) # restore sp
eret
tlb_refill_handler:
KERNEL_STACK_TO_K0
sub $k0, REGISTER_SPACE
REGISTERS_STORE_AND_EXC_RESET $k0
sw $sp,EOFFSET_SP($k0)
add $sp, $k0, 0
jal tlb_refill /* tlb_refill(register_space) */
add $a0, $sp, 0
REGISTERS_LOAD $sp
eret
cache_error_handler:
KERNEL_STACK_TO_K0
sub $k0, REGISTER_SPACE
REGISTERS_STORE_AND_EXC_RESET $k0
sw $sp,EOFFSET_SP($k0)
add $sp, $k0, 0
jal cache_error
nop
REGISTERS_LOAD $sp
eret
userspace_asm:
add $sp, $a0, 0
add $v0, $a1, 0
add $t9, $a2, 0 # Set up correct entry into PIC code
eret

/tags/0.2.0/kernel/arch/mips32/src/ddi/ddi.c
0,0 → 1,50
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <ddi/ddi.h>
#include <proc/task.h>
#include <arch/types.h>
#include <typedefs.h>
#include <security/cap.h>
#include <arch.h>
#include <arch/cp0.h>
/** Enable I/O space range for task.
*
* Interrupts are disabled and task is locked.
*
* @param task Task.
* @param ioaddr Startign I/O space address.
* @param size Size of the enabled I/O range.
*
* @return 0 on success or an error code from errno.h.
*/
int ddi_iospace_enable_arch(task_t *task, __address ioaddr, size_t size)
{
return 0;
}

/tags/0.2.0/kernel/arch/mips32/src/debugger.c
0,0 → 1,378
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/debugger.h>
#include <memstr.h>
#include <console/kconsole.h>
#include <console/cmd.h>
#include <symtab.h>
#include <print.h>
#include <panic.h>
#include <arch.h>
#include <arch/cp0.h>
#include <func.h>
bpinfo_t breakpoints[BKPOINTS_MAX];
SPINLOCK_INITIALIZE(bkpoint_lock);
static int cmd_print_breakpoints(cmd_arg_t *argv);
static cmd_info_t bkpts_info = {
.name = "bkpts",
.description = "Print breakpoint table.",
.func = cmd_print_breakpoints,
.argc = 0,
};
static int cmd_del_breakpoint(cmd_arg_t *argv);
static cmd_arg_t del_argv = {
.type = ARG_TYPE_INT
};
static cmd_info_t delbkpt_info = {
.name = "delbkpt",
.description = "delbkpt <number> - Delete breakpoint.",
.func = cmd_del_breakpoint,
.argc = 1,
.argv = &del_argv
};
static int cmd_add_breakpoint(cmd_arg_t *argv);
static cmd_arg_t add_argv = {
.type = ARG_TYPE_INT
};
static cmd_info_t addbkpt_info = {
.name = "addbkpt",
.description = "addbkpt <&symbol> - new bkpoint. Break on J/Branch insts unsupported.",
.func = cmd_add_breakpoint,
.argc = 1,
.argv = &add_argv
};
static cmd_arg_t adde_argv[] = {
{ .type = ARG_TYPE_INT },
{ .type = ARG_TYPE_INT }
};
static cmd_info_t addbkpte_info = {
.name = "addbkpte",
.description = "addebkpte <&symbol> <&func> - new bkpoint. Call func(or Nothing if 0).",
.func = cmd_add_breakpoint,
.argc = 2,
.argv = adde_argv
};
static struct {
__u32 andmask;
__u32 value;
}jmpinstr[] = {
{0xf3ff0000, 0x41000000}, /* BCzF */
{0xf3ff0000, 0x41020000}, /* BCzFL */
{0xf3ff0000, 0x41010000}, /* BCzT */
{0xf3ff0000, 0x41030000}, /* BCzTL */
{0xfc000000, 0x10000000}, /* BEQ */
{0xfc000000, 0x50000000}, /* BEQL */
{0xfc1f0000, 0x04010000}, /* BEQL */
{0xfc1f0000, 0x04110000}, /* BGEZAL */
{0xfc1f0000, 0x04130000}, /* BGEZALL */
{0xfc1f0000, 0x04030000}, /* BGEZL */
{0xfc1f0000, 0x1c000000}, /* BGTZ */
{0xfc1f0000, 0x5c000000}, /* BGTZL */
{0xfc1f0000, 0x18000000}, /* BLEZ */
{0xfc1f0000, 0x58000000}, /* BLEZL */
{0xfc1f0000, 0x04000000}, /* BLTZ */
{0xfc1f0000, 0x04100000}, /* BLTZAL */
{0xfc1f0000, 0x04120000}, /* BLTZALL */
{0xfc1f0000, 0x04020000}, /* BLTZL */
{0xfc000000, 0x14000000}, /* BNE */
{0xfc000000, 0x54000000}, /* BNEL */
{0xfc000000, 0x08000000}, /* J */
{0xfc000000, 0x0c000000}, /* JAL */
{0xfc1f07ff, 0x00000009}, /* JALR */
{0,0} /* EndOfTable */
};
/** Test, if the given instruction is a jump or branch instruction
*
* @param instr Instruction code
* @return true - it is jump instruction, false otherwise
*/
static bool is_jump(__native instr)
{
int i;
for (i=0;jmpinstr[i].andmask;i++) {
if ((instr & jmpinstr[i].andmask) == jmpinstr[i].value)
return true;
}
return false;
}
/** Add new breakpoint to table */
int cmd_add_breakpoint(cmd_arg_t *argv)
{
bpinfo_t *cur = NULL;
ipl_t ipl;
int i;
if (argv->intval & 0x3) {
printf("Not aligned instruction, forgot to use &symbol?\n");
return 1;
}
ipl = interrupts_disable();
spinlock_lock(&bkpoint_lock);
/* Check, that the breakpoints do not conflict */
for (i=0; i<BKPOINTS_MAX; i++) {
if (breakpoints[i].address == (__address)argv->intval) {
printf("Duplicate breakpoint %d.\n", i);
spinlock_unlock(&bkpoints_lock);
return 0;
} else if (breakpoints[i].address == (__address)argv->intval + sizeof(__native) || \
breakpoints[i].address == (__address)argv->intval - sizeof(__native)) {
printf("Adjacent breakpoints not supported, conflict with %d.\n", i);
spinlock_unlock(&bkpoints_lock);
return 0;
}
}
for (i=0; i<BKPOINTS_MAX; i++)
if (!breakpoints[i].address) {
cur = &breakpoints[i];
break;
}
if (!cur) {
printf("Too many breakpoints.\n");
spinlock_unlock(&bkpoint_lock);
interrupts_restore(ipl);
return 0;
}
cur->address = (__address) argv->intval;
printf("Adding breakpoint on address: %p\n", argv->intval);
cur->instruction = ((__native *)cur->address)[0];
cur->nextinstruction = ((__native *)cur->address)[1];
if (argv == &add_argv) {
cur->flags = 0;
} else { /* We are add extended */
cur->flags = BKPOINT_FUNCCALL;
cur->bkfunc = (void (*)(void *, istate_t *)) argv[1].intval;
}
if (is_jump(cur->instruction))
cur->flags |= BKPOINT_ONESHOT;
cur->counter = 0;
/* Set breakpoint */
*((__native *)cur->address) = 0x0d;
spinlock_unlock(&bkpoint_lock);
interrupts_restore(ipl);
return 1;
}
/** Remove breakpoint from table */
int cmd_del_breakpoint(cmd_arg_t *argv)
{
bpinfo_t *cur;
ipl_t ipl;
if (argv->intval < 0 || argv->intval > BKPOINTS_MAX) {
printf("Invalid breakpoint number.\n");
return 0;
}
ipl = interrupts_disable();
spinlock_lock(&bkpoint_lock);
cur = &breakpoints[argv->intval];
if (!cur->address) {
printf("Breakpoint does not exist.\n");
spinlock_unlock(&bkpoint_lock);
interrupts_restore(ipl);
return 0;
}
if ((cur->flags & BKPOINT_INPROG) && (cur->flags & BKPOINT_ONESHOT)) {
printf("Cannot remove one-shot breakpoint in-progress\n");
spinlock_unlock(&bkpoint_lock);
interrupts_restore(ipl);
return 0;
}
((__u32 *)cur->address)[0] = cur->instruction;
((__u32 *)cur->address)[1] = cur->nextinstruction;
cur->address = NULL;
spinlock_unlock(&bkpoint_lock);
interrupts_restore(ipl);
return 1;
}
/** Print table of active breakpoints */
int cmd_print_breakpoints(cmd_arg_t *argv)
{
int i;
char *symbol;
printf("Breakpoint table.\n");
for (i=0; i < BKPOINTS_MAX; i++)
if (breakpoints[i].address) {
symbol = get_symtab_entry(breakpoints[i].address);
printf("%d. %p in %s\n",i,
breakpoints[i].address, symbol);
printf(" Count(%d) ", breakpoints[i].counter);
if (breakpoints[i].flags & BKPOINT_INPROG)
printf("INPROG ");
if (breakpoints[i].flags & BKPOINT_ONESHOT)
printf("ONESHOT ");
if (breakpoints[i].flags & BKPOINT_FUNCCALL)
printf("FUNCCALL ");
printf("\n");
}
return 1;
}
/** Initialize debugger */
void debugger_init()
{
int i;
for (i=0; i<BKPOINTS_MAX; i++)
breakpoints[i].address = NULL;
cmd_initialize(&bkpts_info);
if (!cmd_register(&bkpts_info))
panic("could not register command %s\n", bkpts_info.name);
cmd_initialize(&delbkpt_info);
if (!cmd_register(&delbkpt_info))
panic("could not register command %s\n", delbkpt_info.name);
cmd_initialize(&addbkpt_info);
if (!cmd_register(&addbkpt_info))
panic("could not register command %s\n", addbkpt_info.name);
cmd_initialize(&addbkpte_info);
if (!cmd_register(&addbkpte_info))
panic("could not register command %s\n", addbkpte_info.name);
}
/** Handle breakpoint
*
* Find breakpoint in breakpoint table.
* If found, call kconsole, set break on next instruction and reexecute.
* If we are on "next instruction", set it back on the first and reexecute.
* If breakpoint not found in breakpoint table, call kconsole and start
* next instruction.
*/
void debugger_bpoint(istate_t *istate)
{
bpinfo_t *cur = NULL;
__address fireaddr = istate->epc;
int i;
/* test branch delay slot */
if (cp0_cause_read() & 0x80000000)
panic("Breakpoint in branch delay slot not supported.\n");
spinlock_lock(&bkpoint_lock);
for (i=0; i<BKPOINTS_MAX; i++) {
/* Normal breakpoint */
if (fireaddr == breakpoints[i].address \
&& !(breakpoints[i].flags & BKPOINT_REINST)) {
cur = &breakpoints[i];
break;
}
/* Reinst only breakpoint */
if ((breakpoints[i].flags & BKPOINT_REINST) \
&& (fireaddr ==breakpoints[i].address+sizeof(__native))) {
cur = &breakpoints[i];
break;
}
}
if (cur) {
if (cur->flags & BKPOINT_REINST) {
/* Set breakpoint on first instruction */
((__u32 *)cur->address)[0] = 0x0d;
/* Return back the second */
((__u32 *)cur->address)[1] = cur->nextinstruction;
cur->flags &= ~BKPOINT_REINST;
spinlock_unlock(&bkpoint_lock);
return;
}
if (cur->flags & BKPOINT_INPROG)
printf("Warning: breakpoint recursion\n");
if (!(cur->flags & BKPOINT_FUNCCALL))
printf("***Breakpoint %d: %p in %s.\n", i,
fireaddr, get_symtab_entry(istate->epc));
/* Return first instruction back */
((__u32 *)cur->address)[0] = cur->instruction;
if (! (cur->flags & BKPOINT_ONESHOT)) {
/* Set Breakpoint on next instruction */
((__u32 *)cur->address)[1] = 0x0d;
cur->flags |= BKPOINT_REINST;
}
cur->flags |= BKPOINT_INPROG;
} else {
printf("***Breakpoint %p in %s.\n", fireaddr,
get_symtab_entry(fireaddr));
/* Move on to next instruction */
istate->epc += 4;
}
if (cur)
cur->counter++;
if (cur && (cur->flags & BKPOINT_FUNCCALL)) {
/* Allow zero bkfunc, just for counting */
if (cur->bkfunc)
cur->bkfunc(cur, istate);
} else {
printf("***Type 'exit' to exit kconsole.\n");
/* This disables all other processors - we are not SMP,
* actually this gets us to cpu_halt, if scheduler() is run
* - we generally do not want scheduler to be run from debug,
* so this is a good idea
*/
atomic_set(&haltstate,1);
spinlock_unlock(&bkpoint_lock);
kconsole("debug");
spinlock_lock(&bkpoint_lock);
atomic_set(&haltstate,0);
}
if (cur && cur->address == fireaddr && (cur->flags & BKPOINT_INPROG)) {
/* Remove one-shot breakpoint */
if ((cur->flags & BKPOINT_ONESHOT))
cur->address = NULL;
/* Remove in-progress flag */
cur->flags &= ~BKPOINT_INPROG;
}
spinlock_unlock(&bkpoint_lock);
}

/tags/0.2.0/kernel/arch/mips32/src/fpu_context.c
0,0 → 1,52
/*
* Copyright (C) 2005 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <fpu_context.h>
#include <arch.h>
#include <arch/cp0.h>
#include <proc/thread.h>
void fpu_disable(void)
{
#ifdef ARCH_HAS_FPU
cp0_status_write(cp0_status_read() & ~cp0_status_fpu_bit);
#endif
}
void fpu_enable(void)
{
#ifdef ARCH_HAS_FPU
cp0_status_write(cp0_status_read() | cp0_status_fpu_bit);
#endif
}
void fpu_init()
{
/* TODO: Zero all registers */
}

/tags/0.2.0/kernel/arch/mips32/src/cpu/cpu.c
0,0 → 1,129
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/cpu.h>
#include <cpu.h>
#include <arch.h>
#include <arch/cp0.h>
#include <typedefs.h>
#include <print.h>
struct data_t {
char *vendor;
char *model;
};
static struct data_t imp_data[] = {
{ "Invalid", "Invalid" }, /* 0x00 */
{ "MIPS", "R2000" }, /* 0x01 */
{ "MIPS", "R3000" }, /* 0x02 */
{ "MIPS", "R6000" }, /* 0x03 */
{ "MIPS", " R4000/R4400" }, /* 0x04 */
{ "LSI Logic", "R3000" }, /* 0x05 */
{ "MIPS", "R6000A" }, /* 0x06 */
{ "IDT", "3051/3052" }, /* 0x07 */
{ "Invalid", "Invalid" }, /* 0x08 */
{ "MIPS", "R10000/T5" }, /* 0x09 */
{ "MIPS", "R4200" }, /* 0x0a */
{ "Unknown", "Unknown" }, /* 0x0b */
{ "Unknown", "Unknown" }, /* 0x0c */
{ "Invalid", "Invalid" }, /* 0x0d */
{ "Invalid", "Invalid" }, /* 0x0e */
{ "Invalid", "Invalid" }, /* 0x0f */
{ "MIPS", "R8000" }, /* 0x10 */
{ "Invalid", "Invalid" }, /* 0x11 */
{ "Invalid", "Invalid" }, /* 0x12 */
{ "Invalid", "Invalid" }, /* 0x13 */
{ "Invalid", "Invalid" }, /* 0x14 */
{ "Invalid", "Invalid" }, /* 0x15 */
{ "Invalid", "Invalid" }, /* 0x16 */
{ "Invalid", "Invalid" }, /* 0x17 */
{ "Invalid", "Invalid" }, /* 0x18 */
{ "Invalid", "Invalid" }, /* 0x19 */
{ "Invalid", "Invalid" }, /* 0x1a */
{ "Invalid", "Invalid" }, /* 0x1b */
{ "Invalid", "Invalid" }, /* 0x1c */
{ "Invalid", "Invalid" }, /* 0x1d */
{ "Invalid", "Invalid" }, /* 0x1e */
{ "Invalid", "Invalid" }, /* 0x1f */
{ "QED", "R4600" }, /* 0x20 */
{ "Sony", "R3000" }, /* 0x21 */
{ "Toshiba", "R3000" }, /* 0x22 */
{ "NKK", "R3000" }, /* 0x23 */
{ NULL, NULL }
};
static struct data_t imp_data80[] = {
{ "MIPS", "4Kc" }, /* 0x80 */
{"Invalid","Invalid"}, /* 0x81 */
{"Invalid","Invalid"}, /* 0x82 */
{"MIPS","4Km & 4Kp"}, /* 0x83 */
{ NULL, NULL}
};
void cpu_arch_init(void)
{
}
void cpu_identify(void)
{
CPU->arch.rev_num = cp0_prid_read() & 0xff;
CPU->arch.imp_num = (cp0_prid_read() >> 8) & 0xff;
}
void cpu_print_report(cpu_t *m)
{
struct data_t *data;
int i;
if (m->arch.imp_num & 0x80) {
/* Count records */
for (i=0;imp_data80[i].vendor;i++)
;
if ((m->arch.imp_num & 0x7f) >= i) {
printf("imp=%d\n",m->arch.imp_num);
return;
}
data = &imp_data80[m->arch.imp_num & 0x7f];
} else {
for (i=0;imp_data[i].vendor;i++)
;
if (m->arch.imp_num >= i) {
printf("imp=%d\n",m->arch.imp_num);
return;
}
data = &imp_data[m->arch.imp_num];
}
printf("cpu%d: %s %s (rev=%d.%d, imp=%d)\n",
m->id, data->vendor, data->model, m->arch.rev_num >> 4,
m->arch.rev_num & 0xf, m->arch.imp_num);
}

/tags/0.2.0/kernel/arch/mips32/src/panic.S
0,0 → 1,48
#
# Copyright (C) 2003-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
.set noat
.set noreorder
.set nomacro
#include <arch/asm/regname.h>
.global panic_printf
/* From printf return directly to halt() */
panic_printf:
jal printf
nop
j halt
nop
/* This code does not work, god knows why */
/* lui $ra, %hi(halt)
j printf
ori $ra, %lo(halt) */

/tags/0.2.0/kernel/arch/mips32/src/context.S
0,0 → 1,86
#
# Copyright (C) 2003-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/regname.h>
#include <arch/context_offset.h>
.text
.set noat
.set noreorder
.set nomacro
.global context_save_arch
.global context_restore_arch
.macro CONTEXT_STORE r
sw $s0,OFFSET_S0(\r)
sw $s1,OFFSET_S1(\r)
sw $s2,OFFSET_S2(\r)
sw $s3,OFFSET_S3(\r)
sw $s4,OFFSET_S4(\r)
sw $s5,OFFSET_S5(\r)
sw $s6,OFFSET_S6(\r)
sw $s7,OFFSET_S7(\r)
sw $s8,OFFSET_S8(\r)
sw $gp,OFFSET_GP(\r)
sw $ra,OFFSET_PC(\r)
sw $sp,OFFSET_SP(\r)
.endm
.macro CONTEXT_LOAD r
lw $s0,OFFSET_S0(\r)
lw $s1,OFFSET_S1(\r)
lw $s2,OFFSET_S2(\r)
lw $s3,OFFSET_S3(\r)
lw $s4,OFFSET_S4(\r)
lw $s5,OFFSET_S5(\r)
lw $s6,OFFSET_S6(\r)
lw $s7,OFFSET_S7(\r)
lw $s8,OFFSET_S8(\r)
lw $gp,OFFSET_GP(\r)
lw $ra,OFFSET_PC(\r)
lw $sp,OFFSET_SP(\r)
.endm
context_save_arch:
CONTEXT_STORE $a0
# context_save returns 1
j $31
li $2, 1
context_restore_arch:
CONTEXT_LOAD $a0
# context_restore returns 0
j $31
xor $2, $2

/tags/0.2.0/kernel/arch/mips32/src/dummy.S
0,0 → 1,41
#
# Copyright (C) 2003-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
.set noat
.global calibrate_delay_loop
.global asm_delay_loop
.global dummy
calibrate_delay_loop:
asm_delay_loop:
dummy:
j $31
nop

/tags/0.2.0/kernel/arch/mips32/src/cache.c
0,0 → 1,35
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/cache.h>
#include <panic.h>
void cache_error(void)
{
panic("cache_error exception\n");
}

/tags/0.2.0/kernel/arch/mips32/Makefile.inc
0,0 → 1,136
#
# Copyright (C) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
## Toolchain configuration
#
BFD_ARCH = mips
TARGET = mipsel-linux-gnu
TOOLCHAIN_DIR = /usr/local/mipsel/bin
## Make some default assumptions
#
ifndef MIPS_MACHINE
MIPS_MACHINE = msim
endif
KERNEL_LOAD_ADDRESS = 0x80100000
INIT_ADDRESS = 0x81000000
INIT_SIZE = 262144
CFLAGS += -mno-abicalls -G 0 -fno-zero-initialized-in-bss
DEFS += -D__32_BITS__ -DMACHINE=${MIPS_MACHINE} -DKERNEL_LOAD_ADDRESS=${KERNEL_LOAD_ADDRESS} -DINIT_ADDRESS=${INIT_ADDRESS} -DINIT_SIZE=${INIT_SIZE}
## Compile with hierarchical page tables support.
#
CONFIG_PAGE_PT = y
DEFS += -DCONFIG_PAGE_PT
## Compile with support for address space identifiers.
#
CONFIG_ASID = y
CONFIG_ASID_FIFO = y
## Accepted MACHINEs
#
ifeq ($(MIPS_MACHINE),indy)
# GCC 4.0.1 compiled for mipsEL has problems compiling in
# BigEndian mode with the swl/swr/lwl/lwr instructions.
# We have to compile it with mips-sgi-irix5 to get it right.
BFD_NAME = elf32-bigmips
BFD = ecoff-bigmips --impure
TARGET = mips-sgi-irix5
TOOLCHAIN_DIR = /usr/local/mips/bin
KERNEL_LOAD_ADDRESS = 0x88002000
CFLAGS += -EB -DBIG_ENDIAN -DARCH_HAS_FPU -march=r4600
INIT_ADDRESS = 0
INIT_SIZE = 0
endif
ifeq ($(MIPS_MACHINE),lgxemul)
BFD_NAME=elf32-tradlittlemips
BFD = ecoff-littlemips
CFLAGS += -DFB_BIG_ENDIAN -DARCH_HAS_FPU -mips3
INIT_ADDRESS = 0x81800000
endif
ifeq ($(MIPS_MACHINE),bgxemul)
BFD_NAME=elf32-bigmips
BFD = ecoff-bigmips
TARGET = mips-sgi-irix5
TOOLCHAIN_DIR = /usr/local/mips/bin
CFLAGS += -EB -DBIG_ENDIAN -DARCH_HAS_FPU -mips3
INIT_ADDRESS = 0x81800000
endif
ifeq ($(MIPS_MACHINE),simics)
# SIMICS 4kc emulation is broken, although for instructions
# that do not bother us
BFD_NAME = elf32-tradlittlemips
BFD = elf32-tradlittlemips
CFLAGS += -mhard-float -mips3 -DTLBCNT=16
TLBCNT = 16
endif
ifeq ($(MIPS_MACHINE),msim)
BFD_NAME = elf32-tradlittlemips
BFD = binary
CFLAGS += -mhard-float -mips3
endif
## Compile with support for software integer division.
#
CONFIG_SOFTINT = y
ARCH_SOURCES = \
arch/$(ARCH)/src/start.S \
arch/$(ARCH)/src/context.S \
arch/$(ARCH)/src/panic.S \
arch/$(ARCH)/src/mips32.c \
arch/$(ARCH)/src/dummy.S \
arch/$(ARCH)/src/console.c \
arch/$(ARCH)/src/asm.S \
arch/$(ARCH)/src/exception.c \
arch/$(ARCH)/src/interrupt.c \
arch/$(ARCH)/src/cache.c \
arch/$(ARCH)/src/debugger.c \
arch/$(ARCH)/src/cpu/cpu.c \
arch/$(ARCH)/src/mm/frame.c \
arch/$(ARCH)/src/mm/page.c \
arch/$(ARCH)/src/mm/tlb.c \
arch/$(ARCH)/src/mm/as.c \
arch/$(ARCH)/src/fpu_context.c \
arch/$(ARCH)/src/ddi/ddi.c \
arch/$(ARCH)/src/drivers/arc.c \
arch/$(ARCH)/src/drivers/msim.c \
arch/$(ARCH)/src/drivers/serial.c

/tags/0.2.0/kernel/arch/mips32/include/exception.h
0,0 → 1,118
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_EXCEPTION_H__
#define __mips32_EXCEPTION_H__
#ifndef __mips32_TYPES_H__
# include <arch/types.h>
#endif
#include <typedefs.h>
#include <arch/cp0.h>
#define EXC_Int 0
#define EXC_Mod 1
#define EXC_TLBL 2
#define EXC_TLBS 3
#define EXC_AdEL 4
#define EXC_AdES 5
#define EXC_IBE 6
#define EXC_DBE 7
#define EXC_Sys 8
#define EXC_Bp 9
#define EXC_RI 10
#define EXC_CpU 11
#define EXC_Ov 12
#define EXC_Tr 13
#define EXC_VCEI 14
#define EXC_FPE 15
#define EXC_WATCH 23
#define EXC_VCED 31
struct istate {
__u32 at;
__u32 v0;
__u32 v1;
__u32 a0;
__u32 a1;
__u32 a2;
__u32 a3;
__u32 t0;
__u32 t1;
__u32 t2;
__u32 t3;
__u32 t4;
__u32 t5;
__u32 t6;
__u32 t7;
__u32 s0;
__u32 s1;
__u32 s2;
__u32 s3;
__u32 s4;
__u32 s5;
__u32 s6;
__u32 s7;
__u32 t8;
__u32 t9;
__u32 gp;
__u32 sp;
__u32 s8;
__u32 ra;
__u32 lo;
__u32 hi;
__u32 status; /* cp0_status */
__u32 epc; /* cp0_epc */
__u32 k1; /* We use it as thread-local pointer */
};
static inline void istate_set_retaddr(istate_t *istate, __address retaddr)
{
istate->epc = retaddr;
}
/** Return true if exception happened while in userspace */
static inline int istate_from_uspace(istate_t *istate)
{
return istate->status & cp0_status_um_bit;
}
static inline __native istate_get_pc(istate_t *istate)
{
return istate->epc;
}
extern void exception(istate_t *istate);
extern void tlb_refill_entry(void);
extern void exception_entry(void);
extern void cache_error_entry(void);
extern void exception_init(void);
#endif

/tags/0.2.0/kernel/arch/mips32/include/arg.h
0,0 → 1,51
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_ARG_H__
#define __mips32_ARG_H__
#include <arch/types.h>
/**
* va_arg macro for MIPS32 - problem is that 64 bit values must be aligned on an 8-byte boundary (32bit values not)
* To satisfy this, paddings must be sometimes inserted.
*/
typedef __address va_list;
#define va_start(ap, lst) \
((ap) = (va_list)&(lst) + sizeof(lst))
#define va_arg(ap, type) \
(((type *)((ap) = (va_list)( (sizeof(type) <= 4) ? ((__address)((ap) + 2*4 - 1) & (~3)) : ((__address)((ap) + 2*8 -1) & (~7)) )))[-1])
#define va_copy(dst,src) ((dst)=(src))
#define va_end(ap)
#endif

/tags/0.2.0/kernel/arch/mips32/include/proc/task.h
0,0 → 1,38
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_TASK_H__
#define __mips32_TASK_H__
typedef struct {
} task_arch_t;
#define task_create_arch(t)
#define task_destroy_arch(t)
#endif

/tags/0.2.0/kernel/arch/mips32/include/proc/thread.h
0,0 → 1,37
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_THREAD_H__
#define __mips32_THREAD_H__
typedef struct {
} thread_arch_t;
#define thread_create_arch(t)
#endif

/tags/0.2.0/kernel/arch/mips32/include/mm/as.h
0,0 → 1,43
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_AS_H__
#define __mips32_AS_H__
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0
#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x80000000
#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffff
#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x00000000
#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0x7fffffff
#define USTACK_ADDRESS_ARCH (0x80000000-PAGE_SIZE)
extern void as_arch_init(void);
#endif

/tags/0.2.0/kernel/arch/mips32/include/mm/page.h
0,0 → 1,147
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_PAGE_H__
#define __mips32_PAGE_H__
#include <arch/mm/frame.h>
#define PAGE_WIDTH FRAME_WIDTH
#define PAGE_SIZE FRAME_SIZE
#ifndef __ASM__
# define KA2PA(x) (((__address) (x)) - 0x80000000)
# define PA2KA(x) (((__address) (x)) + 0x80000000)
#else
# define KA2PA(x) ((x) - 0x80000000)
# define PA2KA(x) ((x) + 0x80000000)
#endif
#ifdef KERNEL
/*
* Implementation of generic 4-level page table interface.
* NOTE: this implementation is under construction
*
* Page table layout:
* - 32-bit virtual addresses
* - Offset is 14 bits => pages are 16K long
* - PTE's use similar format as CP0 EntryLo[01] registers => PTE is therefore 4 bytes long
* - PTE's replace EntryLo v (valid) bit with p (present) bit
* - PTE's use only one bit to distinguish between cacheable and uncacheable mappings
* - PTE's define soft_valid field to ensure there is at least one 1 bit even if the p bit is cleared
* - PTE's make use of CP0 EntryLo's two-bit reserved field for bit W (writable) and bit A (accessed)
* - PTL0 has 64 entries (6 bits)
* - PTL1 is not used
* - PTL2 is not used
* - PTL3 has 4096 entries (12 bits)
*/
#define PTL0_ENTRIES_ARCH 64
#define PTL1_ENTRIES_ARCH 0
#define PTL2_ENTRIES_ARCH 0
#define PTL3_ENTRIES_ARCH 4096
#define PTL0_INDEX_ARCH(vaddr) ((vaddr)>>26)
#define PTL1_INDEX_ARCH(vaddr) 0
#define PTL2_INDEX_ARCH(vaddr) 0
#define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>14) & 0xfff)
#define SET_PTL0_ADDRESS_ARCH(ptl0)
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *)(ptl0))[(i)].pfn<<12)
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *)(ptl3))[(i)].pfn<<12)
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].pfn = (a)>>12)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].pfn = (a)>>12)
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i))
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
#define PTE_VALID_ARCH(pte) (*((__u32 *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte) ((pte)->p != 0)
#define PTE_GET_FRAME_ARCH(pte) ((pte)->pfn<<12)
#define PTE_WRITABLE_ARCH(pte) ((pte)->w != 0)
#define PTE_EXECUTABLE_ARCH(pte) 1
#ifndef __ASM__
#include <arch/mm/tlb.h>
#include <mm/page.h>
#include <arch/mm/frame.h>
#include <arch/types.h>
static inline int get_pt_flags(pte_t *pt, index_t i)
{
pte_t *p = &pt[i];
return (
(p->cacheable<<PAGE_CACHEABLE_SHIFT) |
((!p->p)<<PAGE_PRESENT_SHIFT) |
(1<<PAGE_USER_SHIFT) |
(1<<PAGE_READ_SHIFT) |
((p->w)<<PAGE_WRITE_SHIFT) |
(1<<PAGE_EXEC_SHIFT) |
(p->g<<PAGE_GLOBAL_SHIFT)
);
}
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
{
pte_t *p = &pt[i];
p->cacheable = (flags & PAGE_CACHEABLE) != 0;
p->p = !(flags & PAGE_NOT_PRESENT);
p->g = (flags & PAGE_GLOBAL) != 0;
p->w = (flags & PAGE_WRITE) != 0;
/*
* Ensure that valid entries have at least one bit set.
*/
p->soft_valid = 1;
}
extern void page_arch_init(void);
#endif /* __ASM__ */
#endif /* KERNEL */
#endif

/tags/0.2.0/kernel/arch/mips32/include/mm/frame.h
0,0 → 1,43
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_FRAME_H__
#define __mips32_FRAME_H__
#define FRAME_WIDTH 14 /* 16K */
#define FRAME_SIZE (1<<FRAME_WIDTH)
#ifdef KERNEL
#ifndef __ASM__
extern void frame_arch_init(void);
#endif /* __ASM__ */
#endif /* KERNEL */
#endif

/tags/0.2.0/kernel/arch/mips32/include/mm/tlb.h
0,0 → 1,176
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_TLB_H__
#define __mips32_TLB_H__
#include <arch/exception.h>
#include <typedefs.h>
#ifdef TLBCNT
# define TLB_ENTRY_COUNT TLBCNT
#else
# define TLB_ENTRY_COUNT 48
#endif
#define TLB_WIRED 1
#define TLB_KSTACK_WIRED_INDEX 0
#define TLB_PAGE_MASK_16K (0x3<<13)
#define PAGE_UNCACHED 2
#define PAGE_CACHEABLE_EXC_WRITE 5
typedef union entry_lo entry_lo_t;
typedef union entry_hi entry_hi_t;
typedef union page_mask page_mask_t;
typedef union index tlb_index_t;
union entry_lo {
struct {
#ifdef BIG_ENDIAN
unsigned : 2; /* zero */
unsigned pfn : 24; /* frame number */
unsigned c : 3; /* cache coherency attribute */
unsigned d : 1; /* dirty/write-protect bit */
unsigned v : 1; /* valid bit */
unsigned g : 1; /* global bit */
#else
unsigned g : 1; /* global bit */
unsigned v : 1; /* valid bit */
unsigned d : 1; /* dirty/write-protect bit */
unsigned c : 3; /* cache coherency attribute */
unsigned pfn : 24; /* frame number */
unsigned : 2; /* zero */
#endif
} __attribute__ ((packed));
__u32 value;
};
/** Page Table Entry. */
struct pte {
unsigned g : 1; /**< Global bit. */
unsigned p : 1; /**< Present bit. */
unsigned d : 1; /**< Dirty bit. */
unsigned cacheable : 1; /**< Cacheable bit. */
unsigned : 1; /**< Unused. */
unsigned soft_valid : 1; /**< Valid content even if not present. */
unsigned pfn : 24; /**< Physical frame number. */
unsigned w : 1; /**< Page writable bit. */
unsigned a : 1; /**< Accessed bit. */
};
union entry_hi {
struct {
#ifdef BIG_ENDIAN
unsigned vpn2 : 19;
unsigned : 5;
unsigned asid : 8;
#else
unsigned asid : 8;
unsigned : 5;
unsigned vpn2 : 19;
#endif
} __attribute__ ((packed));
__u32 value;
};
union page_mask {
struct {
#ifdef BIG_ENDIAN
unsigned : 7;
unsigned mask : 12;
unsigned : 13;
#else
unsigned : 13;
unsigned mask : 12;
unsigned : 7;
#endif
} __attribute__ ((packed));
__u32 value;
};
union index {
struct {
#ifdef BIG_ENDIAN
unsigned p : 1;
unsigned : 27;
unsigned index : 4;
#else
unsigned index : 4;
unsigned : 27;
unsigned p : 1;
#endif
} __attribute__ ((packed));
__u32 value;
};
/** Probe TLB for Matching Entry
*
* Probe TLB for Matching Entry.
*/
static inline void tlbp(void)
{
__asm__ volatile ("tlbp\n\t");
}
/** Read Indexed TLB Entry
*
* Read Indexed TLB Entry.
*/
static inline void tlbr(void)
{
__asm__ volatile ("tlbr\n\t");
}
/** Write Indexed TLB Entry
*
* Write Indexed TLB Entry.
*/
static inline void tlbwi(void)
{
__asm__ volatile ("tlbwi\n\t");
}
/** Write Random TLB Entry
*
* Write Random TLB Entry.
*/
static inline void tlbwr(void)
{
__asm__ volatile ("tlbwr\n\t");
}
#define tlb_invalidate(asid) tlb_invalidate_asid(asid)
extern void tlb_invalid(istate_t *istate);
extern void tlb_refill(istate_t *istate);
extern void tlb_modified(istate_t *istate);
#endif

/tags/0.2.0/kernel/arch/mips32/include/mm/asid.h
0,0 → 1,38
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_ASID_H__
#define __mips32_ASID_H__
#include <arch/types.h>
#define ASID_MAX_ARCH 255 /* 2^8 - 1 */
typedef __u8 asid_t;
#endif

/tags/0.2.0/kernel/arch/mips32/include/mm/memory_init.h
0,0 → 1,39
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_MEMORY_INIT_H__
#define __mips32_MEMORY_INIT_H__
#include <config.h>
/* When this function is called, we do not have ARC initiated
* - provide some reasonable minimum and update it later
*/
#define get_memory_size() CONFIG_MEMORY_SIZE
#endif

/tags/0.2.0/kernel/arch/mips32/include/drivers/msim.h
0,0 → 1,43
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MSIM_H_
#define _MSIM_H_
#include <console/chardev.h>
#define MSIM_VIDEORAM 0xB0000000
/** Address of 'keyboard' device. */
#define MSIM_KBD_ADDRESS 0xB0000000
#define MSIM_KBD_IRQ 2
void msim_console(void);
void msim_kbd_release(void);
void msim_kbd_grab(void);
#endif

/tags/0.2.0/kernel/arch/mips32/include/drivers/arc.h
0,0 → 1,258
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_ARC_H__
#define __mips32_ARC_H__
#include <arch/types.h>
#include <console/chardev.h>
#define ARC_BASE_ADDR 0x1000;
#define ARC_MAGIC 0x53435241
/* Frame size used by ARC */
#define ARC_FRAME 4096
typedef enum {
CmResourceTypeNull = 0,
CmResourceTypePort,
CmResourceTypeInterrupt,
CmResourceTypeMemory,
CmResourceTypeDma,
CmResourceTypeDeviceSpecific,
CmResourceTypeVendor,
CmResourceTypeProductName,
CmResourceTypeSerialNumber
}cm_resource_type;
typedef struct {
__u8 type;
__u8 sharedisposition;
__u16 flags;
union {
struct {
long long start; /* 64-bit phys address */
unsigned long length;
}port;
struct {
unsigned long level;
unsigned long vector;
unsigned long reserved1;
}interrupt;
struct {
long long start; /* 64-bit phys address */
unsigned long length;
}memory;
}u;
}__attribute__ ((packed)) cm_resource_descriptor;
typedef struct {
__u16 version;
__u16 revision;
unsigned long count;
cm_resource_descriptor descr[1];
}__attribute__ ((packed)) cm_resource_list;
typedef enum {
SystemClass = 0,
ProcessorClass,
CacheClass,
AdapterClass,
ControllerClass,
PeripheralClass,
MemoryClass
} arc_component_class;
typedef enum {
ARC_type = 0,
CPU_type,
FPU_type,
PrimaryICache,
PrimaryDCache,
SecondaryICache,
SecondaryDCache,
SecondaryCache,
Memory, /* Not in NT PROM */
EISAAdapter,
TCAdapter,
SCSIAdapter,
DTIAdapter,
MultiFunctionAdapter,
DiskController,
TapeController,
CDROMController,
WORMController,
SerialController,
NetworkController,
DisplayController,
ParallelController,
PointerController,
KeyboardController,
AudioController,
OtherController,
DiskPeripheral,
FloppyDiskPeripheral,
TapePeripheral,
ModemPeripheral,
MonitorPeripheral,
PrinterPeripheral,
PointerPeripheral,
KeyboardPeripheral,
TerminalPeripheral,
LinePeripheral,
NetworkPeripheral,
OtherPeripheral,
XTalkAdapter,
PCIAdapter,
GIOAdapter,
TPUAdapter,
Anonymous
}arc_component_type;
typedef enum {
Failed = 1,
ReadOnly = 2,
Removable = 4,
ConsoleIn = 8,
ConsoleOut = 16,
Input = 32,
Output = 64
}arc_component_flags;
typedef struct {
arc_component_class class;
arc_component_type type;
arc_component_flags flags;
__u16 revision;
__u16 version;
__u32 key;
__u32 affinitymask;
__u32 configdatasize;
__u32 identifier_len;
char *identifier;
} __attribute__ ((packed)) arc_component;
typedef struct {
__u16 year;
__u16 month;
__u16 day;
__u16 hour;
__u16 minutes;
__u16 seconds;
__u16 mseconds;
} __attribute__ ((packed)) arc_timeinfo;
/* This is the SGI block structure, WinNT has it different */
typedef enum {
ExceptionBlock,
SystemParameterBlock,
FreeContiguous,
FreeMemory,
BadMemory,
LoadedProgram,
FirmwareTemporary,
FirmwarePermanent
}arc_memorytype_t;
typedef struct {
arc_memorytype_t type;
__u32 basepage; /* *4096 = baseaddr */
__u32 basecount;
}arc_memdescriptor_t;
typedef struct {
char vendorid[8];
char prodid[8];
}arc_sysid_t;
typedef struct {
long (*load)(void); /* ... */
long (*invoke)(__u32 eaddr,__u32 saddr,__u32 argc,char **argv,
char **envp);
long (*execute)(char *path,__u32 argc,char **argv,char **envp);
void (*halt)(void);
void (*powerdown)(void);
void (*restart)(void);
void (*reboot)(void);
void (*enterinteractivemode)(void);
long (*reserved)(void);
/* 10 */
arc_component * (*getpeer)(arc_component *c);
arc_component * (*getchild)(arc_component *c);
arc_component * (*getparent)(arc_component *c);
long (*getconfigurationdata)(void *configdata, arc_component *c);
long (*addchild)(arc_component *c, arc_component *template,
void *configdata);
long (*deletecomponet)(arc_component *current);
long (*getcomponent)(char *path);
long (*saveconfiguration)(void);
arc_sysid_t (*getsystemid)(void);
arc_memdescriptor_t * (*getmemorydescriptor)(arc_memdescriptor_t *cur);
/* 20 */
long (*reserved2)(void);
arc_timeinfo * (*gettime)(void);
__u32 (*getrelativetime)(void);
long (*getdirectoryentry)();
long (*open)(void); /* ... */
long (*close)(__u32 fileid);
long (*read)(__u32 fileid,void *buf,__u32 n,__u32 *cnt);
long (*getreadstatus)(__u32 fileid);
long (*write)(__u32 fileid, void *buf,__u32 n,__u32 *cnt);
long (*seek)(void); /* ... */
/* 30 */
long (*mount)(void); /* ... */
char * (*getenvironmentvariable)(char *name);
char * (*setenvironmentvariable)(char *name, char *value);
long (*getfileinformation)(void); /* ... */
long (*setfileinformation)(__u32 fileid,__u32 attflags,__u32 attmask);
void (*flushallcaches)(void);
long (*testunicodecharacter)(void); /* ... */
long (*getdisplaystatus)(void); /* ... */
} arc_func_vector_t;
typedef struct {
__u32 signature;
__u32 length;
__u16 version;
__u16 revision;
void *restartblock;
void *debugblock;
void *gevector;
void *utlbmissvector;
__u32 firmwarevectorlen;
arc_func_vector_t *firmwarevector;
__u32 privvectorlen;
void *privvector;
__u32 adaptercount;
}__attribute__ ((packed)) arc_sbp;
extern int arc_init(void);
extern int arc_enabled(void);
void arc_frame_init(void);
void arc_console(void);
#endif

/tags/0.2.0/kernel/arch/mips32/include/drivers/serial.h
0,0 → 1,62
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DRV_SERIAL_H__
#define __DRV_SERIAL_H__
#include <console/chardev.h>
#define SERIAL_MAX 4
#define SERIAL_COM1 0x3f8
#define SERIAL_COM1_IRQ 4
#define SERIAL_COM2 0x2f8
#define SERIAL_COM2_IRQ 3
#define P_WRITEB(where,what) (*((volatile char *) (0xB8000000+where))=what)
#define P_READB(where) (*((volatile char *)(0xB8000000+where)))
#define SERIAL_READ(x) P_READB(x)
#define SERIAL_WRITE(x,c) P_WRITEB(x,c)
/* Interrupt enable register */
#define SERIAL_READ_IER(x) (P_READB((x) + 1))
#define SERIAL_WRITE_IER(x,c) (P_WRITEB((x)+1,c))
/* Interrupt identification register */
#define SERIAL_READ_IIR(x) (P_READB((x) + 2))
/* Line status register */
#define SERIAL_READ_LSR(x) (P_READB((x) + 5))
#define TRANSMIT_EMPTY_BIT 5
typedef struct {
int port;
int irq;
}serial_t;
void serial_console(void);
int serial_init(void);
#endif

/tags/0.2.0/kernel/arch/mips32/include/cp0.h
0,0 → 1,114
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_CP0_H__
#define __mips32_CP0_H__
#include <arch/types.h>
#include <arch/mm/tlb.h>
#define cp0_status_ie_enabled_bit (1<<0)
#define cp0_status_exl_exception_bit (1<<1)
#define cp0_status_erl_error_bit (1<<2)
#define cp0_status_um_bit (1<<4)
#define cp0_status_bev_bootstrap_bit (1<<22)
#define cp0_status_fpu_bit (1<<29)
#define cp0_status_im_shift 8
#define cp0_status_im_mask 0xff00
#define cp0_cause_excno(cause) ((cause >> 2) & 0x1f)
#define cp0_cause_coperr(cause) ((cause >> 28) & 0x3)
#define fpu_cop_id 1
/*
* Magic value for use in msim.
*/
#define cp0_compare_value 100000
#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
#define GEN_READ_CP0(nm,reg) static inline __u32 cp0_ ##nm##_read(void) \
{ \
__u32 retval; \
asm("mfc0 %0, $" #reg : "=r"(retval)); \
return retval; \
}
#define GEN_WRITE_CP0(nm,reg) static inline void cp0_ ##nm##_write(__u32 val) \
{ \
asm("mtc0 %0, $" #reg : : "r"(val) ); \
}
GEN_READ_CP0(index, 0);
GEN_WRITE_CP0(index, 0);
GEN_READ_CP0(random, 1);
GEN_READ_CP0(entry_lo0, 2);
GEN_WRITE_CP0(entry_lo0, 2);
GEN_READ_CP0(entry_lo1, 3);
GEN_WRITE_CP0(entry_lo1, 3);
GEN_READ_CP0(context, 4);
GEN_WRITE_CP0(context, 4);
GEN_READ_CP0(pagemask, 5);
GEN_WRITE_CP0(pagemask, 5);
GEN_READ_CP0(wired, 6);
GEN_WRITE_CP0(wired, 6);
GEN_READ_CP0(badvaddr, 8);
GEN_READ_CP0(count, 9);
GEN_WRITE_CP0(count, 9);
GEN_READ_CP0(entry_hi, 10);
GEN_WRITE_CP0(entry_hi, 10);
GEN_READ_CP0(compare, 11);
GEN_WRITE_CP0(compare, 11);
GEN_READ_CP0(status, 12);
GEN_WRITE_CP0(status, 12);
GEN_READ_CP0(cause, 13);
GEN_WRITE_CP0(cause, 13);
GEN_READ_CP0(epc, 14);
GEN_WRITE_CP0(epc, 14);
GEN_READ_CP0(prid, 15);
#endif

/tags/0.2.0/kernel/arch/mips32/include/barrier.h
0,0 → 1,42
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_BARRIER_H__
#define __mips32_BARRIER_H__
/*
* TODO: implement true MIPS memory barriers for macros below.
*/
#define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory")
#define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory")
#define memory_barrier() __asm__ volatile ("" ::: "memory")
#define read_barrier() __asm__ volatile ("" ::: "memory")
#define write_barrier() __asm__ volatile ("" ::: "memory")
#endif

/tags/0.2.0/kernel/arch/mips32/include/interrupt.h
0,0 → 1,48
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_INTERRUPT_H__
#define __mips32_INTERRUPT_H__
#include <arch/exception.h>
#define IVT_ITEMS 40
#define INT_OFFSET 32
#define IRQ_COUNT 8
#define int_register(it, name, handler) exc_register(((it)+INT_OFFSET),name,handler)
#define IRQ2 2
#define IRQ3 3
#define IRQ7 7
#define TIMER_IRQ IRQ7
extern void interrupt_init(void);
#endif

/tags/0.2.0/kernel/arch/mips32/include/arch.h
0,0 → 1,32
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_ARCH_H__
#define __mips32_ARCH_H__
#endif

/tags/0.2.0/kernel/arch/mips32/include/asm.h
0,0 → 1,63
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_ASM_H__
#define __mips32_ASM_H__
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
static inline void cpu_sleep(void)
{
/* Most of the simulators do not support */
/* __asm__ volatile ("wait"); */
}
/** Return base address of current stack
*
* Return the base address of the current stack.
* The stack is assumed to be STACK_SIZE bytes long.
* The stack must start on page boundary.
*/
static inline __address get_stack_base(void)
{
__address v;
__asm__ volatile ("and %0, $29, %1\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
return v;
}
extern void cpu_halt(void);
extern void asm_delay_loop(__u32 t);
extern void userspace_asm(__address ustack, __address uspace_uarg,
__address entry);
#endif

/tags/0.2.0/kernel/arch/mips32/include/atomic.h
0,0 → 1,67
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_ATOMIC_H__
#define __mips32_ATOMIC_H__
#define atomic_inc(x) ((void) atomic_add(x, 1))
#define atomic_dec(x) ((void) atomic_add(x, -1))
#define atomic_postinc(x) (atomic_add(x, 1) - 1)
#define atomic_postdec(x) (atomic_add(x, -1) + 1)
#define atomic_preinc(x) atomic_add(x, 1)
#define atomic_predec(x) atomic_add(x, -1)
/* Atomic addition of immediate value.
*
* @param val Memory location to which will be the immediate value added.
* @param i Signed immediate that will be added to *val.
*
* @return Value after addition.
*/
static inline long atomic_add(atomic_t *val, int i)
{
long tmp, v;
__asm__ volatile (
"1:\n"
" ll %0, %1\n"
" addiu %0, %0, %3\n" /* same as addi, but never traps on overflow */
" move %2, %0\n"
" sc %0, %1\n"
" beq %0, %4, 1b\n" /* if the atomic operation failed, try again */
/* nop */ /* nop is inserted automatically by compiler */
: "=r" (tmp), "=m" (val->count), "=r" (v)
: "i" (i), "i" (0)
);
return v;
}
#endif

/tags/0.2.0/kernel/arch/mips32/include/context_offset.h
0,0 → 1,52
/* This file is automatically generated by gencontext.c. */
/* struct context */
#define OFFSET_SP 0x0
#define OFFSET_PC 0x4
#define OFFSET_S0 0x8
#define OFFSET_S1 0xc
#define OFFSET_S2 0x10
#define OFFSET_S3 0x14
#define OFFSET_S4 0x18
#define OFFSET_S5 0x1c
#define OFFSET_S6 0x20
#define OFFSET_S7 0x24
#define OFFSET_S8 0x28
#define OFFSET_GP 0x2c
/* struct register_dump */
#define EOFFSET_AT 0x0
#define EOFFSET_V0 0x4
#define EOFFSET_V1 0x8
#define EOFFSET_A0 0xc
#define EOFFSET_A1 0x10
#define EOFFSET_A2 0x14
#define EOFFSET_A3 0x18
#define EOFFSET_T0 0x1c
#define EOFFSET_T1 0x20
#define EOFFSET_T2 0x24
#define EOFFSET_T3 0x28
#define EOFFSET_T4 0x2c
#define EOFFSET_T5 0x30
#define EOFFSET_T6 0x34
#define EOFFSET_T7 0x38
#define EOFFSET_S0 0x3c
#define EOFFSET_S1 0x40
#define EOFFSET_S2 0x44
#define EOFFSET_S3 0x48
#define EOFFSET_S4 0x4c
#define EOFFSET_S5 0x50
#define EOFFSET_S6 0x54
#define EOFFSET_S7 0x58
#define EOFFSET_T8 0x5c
#define EOFFSET_T9 0x60
#define EOFFSET_GP 0x64
#define EOFFSET_SP 0x68
#define EOFFSET_S8 0x6c
#define EOFFSET_RA 0x70
#define EOFFSET_LO 0x74
#define EOFFSET_HI 0x78
#define EOFFSET_STATUS 0x7c
#define EOFFSET_EPC 0x80
#define EOFFSET_K1 0x84
#define REGISTER_SPACE 136

/tags/0.2.0/kernel/arch/mips32/include/stack.h
0,0 → 1,35
/*
* Copyright (C) 2006 Josef Cejka
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_STACK_H__
#define __mips32_STACK_H__
#define STACK_ITEM_SIZE 4
#define STACK_ALIGNMENT 8
#endif

/tags/0.2.0/kernel/arch/mips32/include/context.h
0,0 → 1,71
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_CONTEXT_H__
#define __mips32_CONTEXT_H__
#include <align.h>
#include <arch/stack.h>
/*
* Put one item onto the stack to support get_stack_base() and align it up.
*/
#define SP_DELTA (0 + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT))
#ifndef __ASM__
#ifndef __mips32_TYPES_H__
# include <arch/types.h>
#endif
/*
* Only save registers that must be preserved across
* function calls.
*/
struct context {
__address sp;
__address pc;
__u32 s0;
__u32 s1;
__u32 s2;
__u32 s3;
__u32 s4;
__u32 s5;
__u32 s6;
__u32 s7;
__u32 s8;
__u32 gp;
ipl_t ipl;
};
#endif /* __ASM__ */
#endif

/tags/0.2.0/kernel/arch/mips32/include/debugger.h
0,0 → 1,60
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _mips32_DEBUGGER_H_
#define _mips32_DEBUGGER_H_
#include <typedefs.h>
#include <arch/exception.h>
#include <arch/types.h>
#define BKPOINTS_MAX 10
#define BKPOINT_INPROG (1 << 0) /**< Breakpoint was shot */
#define BKPOINT_ONESHOT (1 << 1) /**< One-time breakpoint,mandatory for j/b
instructions */
#define BKPOINT_REINST (1 << 2) /**< Breakpoint is set on the next
instruction, so that it could be
reinstalled on the previous one */
#define BKPOINT_FUNCCALL (1 << 3) /**< Call a predefined function */
typedef struct {
__address address; /**< Breakpoint address */
__native instruction; /**< Original instruction */
__native nextinstruction; /**< Original instruction following break */
int flags; /**< Flags regarding breakpoint */
count_t counter;
void (*bkfunc)(void *b, istate_t *istate);
} bpinfo_t;
extern void debugger_init(void);
void debugger_bpoint(istate_t *istate);
extern bpinfo_t breakpoints[BKPOINTS_MAX];
#endif

/tags/0.2.0/kernel/arch/mips32/include/types.h
0,0 → 1,57
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_TYPES_H__
#define __mips32_TYPES_H__
#define NULL 0
typedef signed char __s8;
typedef unsigned char __u8;
typedef signed short __s16;
typedef unsigned short __u16;
typedef unsigned long __u32;
typedef signed long __s32;
typedef unsigned long long __u64;
typedef signed long long __s64;
typedef __u32 __address;
typedef __u32 ipl_t;
typedef __u32 __native;
typedef __s32 __snative;
typedef struct pte pte_t;
typedef __u32 pfn_t;
#endif

/tags/0.2.0/kernel/arch/mips32/include/elf.h
0,0 → 1,42
/*
* Copyright (C) 2006 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_ELF_H__
#define __mips32_ELF_H__
#define ELF_MACHINE EM_MIPS
#ifdef BIG_ENDIAN
# define ELF_DATA_ENCODING ELFDATA2MSB
#else
# define ELF_DATA_ENCODING ELFDATA2LSB
#endif
#define ELF_CLASS ELFCLASS32
#endif

/tags/0.2.0/kernel/arch/mips32/include/fpu_context.h
0,0 → 1,41
/*
* Copyright (C) 2005 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_FPU_CONTEXT_H__
#define __mips32_FPU_CONTEXT_H__
#include <arch/types.h>
#define FPU_CONTEXT_ALIGN sizeof(__native)
struct fpu_context {
__native dregs[32];
__native cregs[32];
};
#endif

/tags/0.2.0/kernel/arch/mips32/include/asm/regname.h
0,0 → 1,89
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_REGNAME_H_
#define __mips32_REGNAME_H_
#define zero 0
#define at 1
#define v0 2
#define v1 3
#define a0 4
#define a1 5
#define a2 6
#define a3 7
#define t0 8
#define t1 9
#define t2 10
#define t3 11
#define t4 12
#define t5 13
#define t6 14
#define t7 15
#define s0 16
#define s1 17
#define s2 18
#define s3 19
#define s4 20
#define s5 21
#define s6 22
#define s7 23
#define t8 24
#define t9 25
#define k0 26
#define k1 27
#define gp 28
#define sp 29
#define s8 30
#define ra 31
#define rindex 0
#define rrandom 1
#define entrylo0 2
#define entrylo1 3
#define context 4
#define pagemask 5
#define wired 6
#define badvaddr 8
#define count 9
#define entryhi 10
#define compare 11
#define status 12
#define cause 13
#define epc 14
#define rconfig 16
#define lladdr 17
#define watchlo 18
#define watchhi 19
#define xcontext 20
#define rdebug 23
#define depc 24
#define eepc 30
#endif /* _REGNAME_H_ */

/tags/0.2.0/kernel/arch/mips32/include/asm/boot.h
0,0 → 1,36
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_BOOT_H_
#define __mips32_BOOT_H_
/* Temporary stack size for boot process */
#define TEMP_STACK_SIZE 0x100
#endif

/tags/0.2.0/kernel/arch/mips32/include/memstr.h
0,0 → 1,39
/*
* Copyright (C) 2005 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_MEMSTR_H__
#define __mips32_MEMSTR_H__
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt))
extern void memsetw(__address dst, size_t cnt, __u16 x);
extern void memsetb(__address dst, size_t cnt, __u8 x);
extern int memcmp(__address src, __address dst, int cnt);
#endif

/tags/0.2.0/kernel/arch/mips32/include/debug.h
0,0 → 1,46
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_DEBUG_H__
#define __mips23_DEBUG_H__
/** simulator enters the trace mode */
#define ___traceon() asm volatile ( "\t.word\t0x39\n");
/** simulator leaves the trace mode */
#define ___traceoff() asm volatile ( "\t.word\t0x3d\n");
/** register dump */
#define ___regview() asm volatile ( "\t.word\t0x37\n");
/** halt the simulator */
#define ___halt() asm volatile ( "\t.word\t0x28\n");
/** simulator enters interactive mode */
#define ___intmode() asm volatile ( "\t.word\t0x29\n");
#endif

/tags/0.2.0/kernel/arch/mips32/include/console.h
0,0 → 1,35
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_CONSOLE_H__
#define __mips32_CONSOLE_H__
void console_init(void);
#endif

/tags/0.2.0/kernel/arch/mips32/include/cpu.h
0,0 → 1,39
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_CPU_H__
#define __mips32_CPU_H__
#include <arch/types.h>
struct cpu_arch {
__u32 imp_num;
__u32 rev_num;
};
#endif

/tags/0.2.0/kernel/arch/mips32/include/byteorder.h
0,0 → 1,51
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_BYTEORDER_H__
#define __mips32_BYTEORDER_H__
#include <arch/types.h>
#include <byteorder.h>
#ifdef BIG_ENDIAN
static inline __u64 __u64_le2host(__u64 n)
{
return __u64_byteorder_swap(n);
}
static inline __native __native_le2host(__native n)
{
return __u32_byteorder_swap(n);
}
#else
# define __native_le2host(n) (n)
# define __u64_le2host(n) (n)
#endif
#endif

/tags/0.2.0/kernel/arch/mips32/include/cache.h
0,0 → 1,34
/*
* Copyright (C) 2003-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_CACHE_H__
#define __mips32_CACHE_H__
extern void cache_error(void);
#endif

/tags/0.2.0/kernel/arch/mips32/include/faddr.h
0,0 → 1,36
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __mips32_FADDR_H__
#define __mips32_FADDR_H__
#include <arch/types.h>
#define FADDR(fptr) ((__address) (fptr))
#endif

/tags/0.2.0/kernel/arch/mips32/_link.ld.in
0,0 → 1,60
/*
* MIPS32 linker script
*
* kernel text
* kernel data
*
*/
#undef mips
#define mips mips
OUTPUT_ARCH(mips)
ENTRY(kernel_image_start)
SECTIONS {
. = KERNEL_LOAD_ADDRESS;
.text : {
ktext_start = .;
*(.text);
ktext_end = .;
}
.data : {
kdata_start = .;
*(.data); /* initialized data */
hardcoded_ktext_size = .;
LONG(ktext_end - ktext_start);
hardcoded_kdata_size = .;
LONG(kdata_end - kdata_start);
hardcoded_load_address = .;
LONG(KERNEL_LOAD_ADDRESS);
*(.rodata*);
*(.sdata);
*(.reginfo);
/* Unfortunately IRIX does not allow us
* to include this as a last section :-(
* BSS/SBSS addresses will be wrong */
symbol_table = .;
*(symtab.*);
}
_gp = . + 0x8000;
.lit8 : { *(.lit8) }
.lit4 : { *(.lit4) }
.sbss : {
*(.sbss);
*(.scommon);
}
.bss : {
*(.bss); /* uninitialized static variables */
*(COMMON); /* global variables */
}
kdata_end = .;
/DISCARD/ : {
*(.mdebug*);
*(.pdr);
*(.comment);
*(.note);
}
}

/tags/0.2.0/kernel/arch/amd64/src/boot/boot.S
0,0 → 1,515
#
# Copyright (C) 2005 Ondrej Palkovsky
# Copyright (C) 2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/boot/boot.h>
#include <arch/boot/memmap.h>
#include <arch/mm/page.h>
#include <arch/mm/ptl.h>
#include <arch/pm.h>
#include <arch/cpu.h>
#include <arch/cpuid.h>
#define START_STACK (BOOT_OFFSET - BOOT_STACK_SIZE)
.section K_TEXT_START, "ax"
.code32
.align 4
.global multiboot_image_start
multiboot_header:
.long MULTIBOOT_HEADER_MAGIC
.long MULTIBOOT_HEADER_FLAGS
.long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS) # checksum
.long multiboot_header
.long unmapped_ktext_start
.long 0
.long 0
.long multiboot_image_start
multiboot_image_start:
movl $START_STACK, %esp # initialize stack pointer
lgdt bootstrap_gdtr # initialize Global Descriptor Table register
movw $gdtselector(KDATA_DES), %cx
movw %cx, %es
movw %cx, %ds # kernel data + stack
movw %cx, %ss
# Simics seems to remove hidden part of GS on entering user mode
# when _visible_ part of GS does not point to user-mode segment
movw $gdtselector(UDATA_DES), %cx
movw %cx, %fs
movw %cx, %gs
jmpl $gdtselector(KTEXT32_DES), $multiboot_meeting_point
multiboot_meeting_point:
movl %eax, grub_eax # save parameters from GRUB
movl %ebx, grub_ebx
#ifdef CONFIG_FB
mov $vesa_init, %esi;
mov $VESA_INIT_SEGMENT << 4, %edi
mov $e_vesa_init - vesa_init, %ecx
cld
rep movsb
mov $VESA_INIT_SEGMENT << 4, %edi
jmpl *%edi
vesa_meeting_point:
mov %esi, KA2PA(vesa_ph_addr)
mov %di, KA2PA(vesa_height)
shr $16, %edi
mov %di, KA2PA(vesa_width)
mov %bx, KA2PA(vesa_scanline)
shr $16, %ebx
mov %bx, KA2PA(vesa_bpp)
#endif
# Protected 32-bit. We want to reuse the code-seg descriptor,
# the Default operand size must not be 1 when entering long mode
movl $0x80000000, %eax
cpuid
cmp $0x80000000, %eax # any function > 80000000h?
jbe long_mode_unsupported
movl $(AMD_CPUID_EXTENDED), %eax # Extended function code 80000001
cpuid
bt $29, %edx # Test if long mode is supported.
jc long_mode_supported
long_mode_unsupported:
cli
hlt
long_mode_supported:
# Enable 64-bit page transaltion entries - CR4.PAE = 1.
# Paging is not enabled until after long mode is enabled
movl %cr4, %eax
btsl $5, %eax
movl %eax, %cr4
# Set up paging tables
leal ptl_0, %eax
movl %eax, %cr3
# Enable long mode
movl $EFER_MSR_NUM, %ecx # EFER MSR number
rdmsr # Read EFER
btsl $AMD_LME_FLAG, %eax # Set LME=1
wrmsr # Write EFER
# Enable paging to activate long mode (set CR0.PG=1)
movl %cr0, %eax
btsl $31, %eax
movl %eax, %cr0
# At this point we are in compatibility mode
jmpl $gdtselector(KTEXT_DES), $start64
.code64
start64:
movq $(PA2KA(START_STACK)), %rsp
movl grub_eax, %eax
movl grub_ebx, %ebx
cmpl $MULTIBOOT_LOADER_MAGIC, %eax # compare GRUB signature
je valid_boot
xorl %ecx, %ecx # no memory size or map available
movl %ecx, e801memorysize
movl %ecx, e820counter
jmp invalid_boot
valid_boot:
movl (%ebx), %eax # ebx = physical address of struct multiboot_info
bt $0, %eax # mbi->flags[0] (mem_lower, mem_upper valid)
jc mem_valid
xorl %ecx, %ecx
jmp mem_invalid
mem_valid:
movl 4(%ebx), %ecx # mbi->mem_lower
addl 8(%ebx), %ecx # mbi->mem_upper
mem_invalid:
movl %ecx, e801memorysize
bt $3, %eax # mbi->flags[3] (mods_count, mods_addr valid)
jc mods_valid
xorq %rcx, %rcx
movq %rcx, init
jmp mods_end
mods_valid:
xorq %rcx, %rcx
movl 20(%ebx), %ecx # mbi->mods_count
movq %rcx, init
cmpl $0, %ecx
je mods_end
movl 24(%ebx), %esi # mbi->mods_addr
movq $init, %rdi
mods_loop:
xorq %rdx, %rdx
movl 0(%esi), %edx # mods->mod_start
movq $0xffff800000000000, %r10
addq %r10, %rdx
movq %rdx, 8(%rdi)
xorq %rdx, %rdx
movl 4(%esi), %edx
subl 0(%esi), %edx # mods->mod_end - mods->mod_start
movq %rdx, 16(%rdi)
addl $16, %esi
addq $16, %rdi
loop mods_loop
mods_end:
bt $6, %eax # mbi->flags[6] (mmap_length, mmap_addr valid)
jc mmap_valid
xorl %edx, %edx
jmp mmap_invalid
mmap_valid:
movl 44(%ebx), %ecx # mbi->mmap_length
movl 48(%ebx), %esi # mbi->mmap_addr
movq $e820table, %rdi
xorl %edx, %edx
mmap_loop:
cmpl $0, %ecx
jle mmap_end
movl 4(%esi), %eax # mmap->base_addr_low
movl %eax, (%rdi)
movl 8(%esi), %eax # mmap->base_addr_high
movl %eax, 4(%rdi)
movl 12(%esi), %eax # mmap->length_low
movl %eax, 8(%rdi)
movl 16(%esi), %eax # mmap->length_high
movl %eax, 12(%rdi)
movl 20(%esi), %eax # mmap->type
movl %eax, 16(%rdi)
movl (%esi), %eax # mmap->size
addl $0x4, %eax
addl %eax, %esi
subl %eax, %ecx
addq $MEMMAP_E820_RECORD_SIZE, %rdi
incl %edx
jmp mmap_loop
mmap_end:
mmap_invalid:
movl %edx, e820counter
invalid_boot:
#ifdef CONFIG_SMP
# copy AP bootstrap routines below 1 MB
movq $BOOT_OFFSET, %rsi
movq $AP_BOOT_OFFSET, %rdi
movq $_hardcoded_unmapped_size, %rcx
cld
rep movsb
#endif
call main_bsp # never returns
cli
hlt
#ifdef CONFIG_FB
.code32
vesa_init:
jmp $gdtselector(VESA_INIT_DES), $vesa_init_real - vesa_init
.code16
vesa_init_real:
mov %cr0, %eax
and $~1, %eax
mov %eax, %cr0
jmp $VESA_INIT_SEGMENT, $vesa_init_real2 - vesa_init
vesa_init_real2:
mov $VESA_INIT_SEGMENT, %bx
mov %bx, %es
mov %bx, %fs
mov %bx, %gs
mov %bx, %ds
mov %bx, %ss
movl $0x0000fffc, %esp
movl $0x0000fffc, %ebp
#define VESA_INFO_SIZE 1024
#define VESA_MODE_LIST_PTR_OFFSET 14
#define VESA_MODE_WIDTH_OFFSET 18
#define VESA_MODE_HEIGHT_OFFSET 20
#define VESA_MODE_BPP_OFFSET 25
#define VESA_MODE_SCANLINE_OFFSET 16
#define VESA_MODE_PHADDR_OFFSET 40
#define VESA_END_OF_MODES 0xffff
#define VESA_OK 0x4f
#define VESA_GET_INFO 0x4f00
#define VESA_GET_MODE_INFO 0x4f01
#define VESA_SET_MODE 0x4f02
#define CONFIG_VESA_BPP_a 255
#if CONFIG_VESA_BPP == 24
#undef CONFIG_VESA_BPP_a
#define CONFIG_VESA_BPP_a 32
#endif
mov $VESA_GET_INFO, %ax
mov $e_vesa_init - vesa_init, %di
push %di
int $0x10
pop %di
cmp $VESA_OK, %al
jnz 0f
mov 2 + VESA_MODE_LIST_PTR_OFFSET(%di), %si
mov %si, %gs
mov VESA_MODE_LIST_PTR_OFFSET(%di), %si
add $VESA_INFO_SIZE, %di
1:# Try next mode
mov %gs:(%si), %cx
cmp $VESA_END_OF_MODES, %cx
jz 0f
inc %si
inc %si
push %cx
push %di
push %si
mov $VESA_GET_MODE_INFO, %ax
int $0x10
pop %si
pop %di
pop %cx
cmp $VESA_OK, %al
jnz 0f
mov $CONFIG_VESA_WIDTH, %ax
cmp VESA_MODE_WIDTH_OFFSET(%di), %ax
jnz 1b
mov $CONFIG_VESA_HEIGHT, %ax
cmp VESA_MODE_HEIGHT_OFFSET(%di), %ax
jnz 1b
mov $CONFIG_VESA_BPP, %al
cmp VESA_MODE_BPP_OFFSET(%di), %al
jz 2f
mov $CONFIG_VESA_BPP_a, %al
cmp VESA_MODE_BPP_OFFSET(%di), %al
jnz 1b
2:
mov %cx, %bx
or $0xc000, %bx
push %di
mov $VESA_SET_MODE, %ax
int $0x10
pop %di
cmp $VESA_OK, %al
jnz 0f
mov VESA_MODE_PHADDR_OFFSET(%di), %esi
mov VESA_MODE_WIDTH_OFFSET(%di), %ax
shl $16, %eax
mov VESA_MODE_HEIGHT_OFFSET(%di), %ax
mov VESA_MODE_BPP_OFFSET(%di), %bl
xor %bh, %bh
shl $16, %ebx
mov VESA_MODE_SCANLINE_OFFSET(%di), %bx
mov %eax, %edi
8:
mov %cr0, %eax
or $1, %eax
mov %eax, %cr0
jmp 9f
9:
ljmpl $gdtselector(KTEXT32_DES), $(vesa_init_protect - vesa_init + VESA_INIT_SEGMENT << 4)
0:# No prefered mode found
mov $0x111, %cx
push %di
push %cx
mov $VESA_GET_MODE_INFO, %ax
int $0x10
pop %cx
pop %di
cmp $VESA_OK, %al
jnz 1f
jz 2b # Force relative jump
1:
mov $0x0003, %ax
int $0x10
mov $0xffffffff, %edi # EGA text mode used, because of problems with VESA
xor %ax, %ax
jz 8b # Force relative jump
.code32
vesa_init_protect:
movw $gdtselector(KDATA_DES), %cx
movw %cx, %es
movw %cx, %ds # kernel data + stack
movw %cx, %ss
# Simics seems to remove hidden part of GS on entering user mode
# when _visible_ part of GS does not point to user-mode segment
movw $gdtselector(UDATA_DES), %cx
movw %cx, %fs
movw %cx, %gs
jmpl $gdtselector(KTEXT32_DES), $vesa_meeting_point
.align 4
e_vesa_init:
#endif
.section K_DATA_START, "aw", @progbits
.align 4096
# Identical mapping of first 64MB and the same of -2GB -> 0
.global ptl_2
ptl_2:
.quad 0x0 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x200000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x400000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x600000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x800000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0xa00000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0xc00000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0xe00000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x1000000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x1200000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x1400000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x1600000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x1800000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x1a00000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x1c00000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x1e00000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x2000000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x2200000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x2400000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x2600000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x2800000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x2a00000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x2c00000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x2e00000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x3000000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x3200000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x3400000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x3600000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x3800000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x3a00000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x3c00000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.quad 0x3e00000 | (PTL_WRITABLE | PTL_PRESENT | PTL_2MB_PAGE)
.align 4096
.global ptl_1
ptl_1:
.quad ptl_2 + (PTL_WRITABLE | PTL_PRESENT)
.fill 509,8,0
.quad ptl_2 + (PTL_WRITABLE | PTL_PRESENT)
.fill 1,8,0
.align 4096
.global ptl_0
ptl_0:
.quad ptl_1 + (PTL_WRITABLE | PTL_PRESENT)
.fill 255,8,0
.quad ptl_1 + (PTL_WRITABLE | PTL_PRESENT)
.fill 254,8,0
.quad ptl_1 + (PTL_WRITABLE | PTL_PRESENT)
.global bootstrap_gdtr
bootstrap_gdtr:
.word gdtselector(GDT_ITEMS)
.long KA2PA(gdt)
grub_eax:
.long 0
grub_ebx:
.long 0

/tags/0.2.0/kernel/arch/amd64/src/mm/page.c
0,0 → 1,208
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/page.h>
#include <genarch/mm/page_pt.h>
#include <arch/mm/frame.h>
#include <mm/page.h>
#include <mm/frame.h>
#include <mm/as.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <config.h>
#include <memstr.h>
#include <interrupt.h>
#include <print.h>
#include <panic.h>
#include <align.h>
/* Definitions for identity page mapper */
pte_t helper_ptl1[512] __attribute__((aligned (PAGE_SIZE)));
pte_t helper_ptl2[512] __attribute__((aligned (PAGE_SIZE)));
pte_t helper_ptl3[512] __attribute__((aligned (PAGE_SIZE)));
extern pte_t ptl_0; /* From boot.S */
#define PTL1_PRESENT(ptl0, page) (!(GET_PTL1_FLAGS_ARCH(ptl0, PTL0_INDEX_ARCH(page)) & PAGE_NOT_PRESENT))
#define PTL2_PRESENT(ptl1, page) (!(GET_PTL2_FLAGS_ARCH(ptl1, PTL1_INDEX_ARCH(page)) & PAGE_NOT_PRESENT))
#define PTL3_PRESENT(ptl2, page) (!(GET_PTL3_FLAGS_ARCH(ptl2, PTL2_INDEX_ARCH(page)) & PAGE_NOT_PRESENT))
#define PTL1_ADDR(ptl0, page) ((pte_t *)PA2KA(GET_PTL1_ADDRESS_ARCH(ptl0, PTL0_INDEX_ARCH(page))))
#define PTL2_ADDR(ptl1, page) ((pte_t *)PA2KA(GET_PTL2_ADDRESS_ARCH(ptl1, PTL1_INDEX_ARCH(page))))
#define PTL3_ADDR(ptl2, page) ((pte_t *)PA2KA(GET_PTL3_ADDRESS_ARCH(ptl2, PTL2_INDEX_ARCH(page))))
#define SETUP_PTL1(ptl0, page, tgt) { \
SET_PTL1_ADDRESS_ARCH(ptl0, PTL0_INDEX_ARCH(page), (__address)KA2PA(tgt)); \
SET_PTL1_FLAGS_ARCH(ptl0, PTL0_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \
}
#define SETUP_PTL2(ptl1, page, tgt) { \
SET_PTL2_ADDRESS_ARCH(ptl1, PTL1_INDEX_ARCH(page), (__address)KA2PA(tgt)); \
SET_PTL2_FLAGS_ARCH(ptl1, PTL1_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \
}
#define SETUP_PTL3(ptl2, page, tgt) { \
SET_PTL3_ADDRESS_ARCH(ptl2, PTL2_INDEX_ARCH(page), (__address)KA2PA(tgt)); \
SET_PTL3_FLAGS_ARCH(ptl2, PTL2_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \
}
#define SETUP_FRAME(ptl3, page, tgt) { \
SET_FRAME_ADDRESS_ARCH(ptl3, PTL3_INDEX_ARCH(page), (__address)KA2PA(tgt)); \
SET_FRAME_FLAGS_ARCH(ptl3, PTL3_INDEX_ARCH(page), PAGE_WRITE | PAGE_EXEC); \
}
void page_arch_init(void)
{
__address cur;
int i;
int identity_flags = PAGE_CACHEABLE | PAGE_EXEC | PAGE_GLOBAL;
if (config.cpu_active == 1) {
page_mapping_operations = &pt_mapping_operations;
/*
* PA2KA(identity) mapping for all frames.
*/
for (cur = 0; cur < last_frame; cur += FRAME_SIZE) {
/* Standard identity mapping */
page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, identity_flags);
}
/* Upper kernel mapping
* - from zero to top of kernel (include bottom addresses
* because some are needed for init )
*/
for (cur = PA2KA_CODE(0); cur < config.base+config.kernel_size; cur += FRAME_SIZE) {
page_mapping_insert(AS_KERNEL, cur, KA2PA(cur), identity_flags);
}
for (i=0; i < init.cnt; i++) {
for (cur=init.tasks[i].addr;cur < init.tasks[i].size; cur += FRAME_SIZE) {
page_mapping_insert(AS_KERNEL, PA2KA_CODE(KA2PA(cur)), KA2PA(cur), identity_flags);
}
}
exc_register(14, "page_fault", (iroutine)page_fault);
write_cr3((__address) AS_KERNEL->page_table);
}
else {
write_cr3((__address) AS_KERNEL->page_table);
}
}
/** Identity page mapper
*
* We need to map whole physical memory identically before the page subsystem
* is initializaed. This thing clears page table and fills in the specific
* items.
*/
void ident_page_fault(int n, istate_t *istate)
{
__address page;
static __address oldpage = 0;
pte_t *aptl_1, *aptl_2, *aptl_3;
page = read_cr2();
if (oldpage) {
/* Unmap old address */
aptl_1 = PTL1_ADDR(&ptl_0, oldpage);
aptl_2 = PTL2_ADDR(aptl_1, oldpage);
aptl_3 = PTL3_ADDR(aptl_2, oldpage);
SET_FRAME_FLAGS_ARCH(aptl_3, PTL3_INDEX_ARCH(oldpage), PAGE_NOT_PRESENT);
if (KA2PA(aptl_3) == KA2PA(helper_ptl3))
SET_PTL3_FLAGS_ARCH(aptl_2, PTL2_INDEX_ARCH(oldpage), PAGE_NOT_PRESENT);
if (KA2PA(aptl_2) == KA2PA(helper_ptl2))
SET_PTL2_FLAGS_ARCH(aptl_1, PTL1_INDEX_ARCH(oldpage), PAGE_NOT_PRESENT);
if (KA2PA(aptl_1) == KA2PA(helper_ptl1))
SET_PTL1_FLAGS_ARCH(&ptl_0, PTL0_INDEX_ARCH(oldpage), PAGE_NOT_PRESENT);
}
if (PTL1_PRESENT(&ptl_0, page))
aptl_1 = PTL1_ADDR(&ptl_0, page);
else {
SETUP_PTL1(&ptl_0, page, helper_ptl1);
aptl_1 = helper_ptl1;
}
if (PTL2_PRESENT(aptl_1, page))
aptl_2 = PTL2_ADDR(aptl_1, page);
else {
SETUP_PTL2(aptl_1, page, helper_ptl2);
aptl_2 = helper_ptl2;
}
if (PTL3_PRESENT(aptl_2, page))
aptl_3 = PTL3_ADDR(aptl_2, page);
else {
SETUP_PTL3(aptl_2, page, helper_ptl3);
aptl_3 = helper_ptl3;
}
SETUP_FRAME(aptl_3, page, page);
oldpage = page;
}
void page_fault(int n, istate_t *istate)
{
__address page;
pf_access_t access;
page = read_cr2();
if (istate->error_word & PFERR_CODE_RSVD)
panic("Reserved bit set in page table entry.\n");
if (istate->error_word & PFERR_CODE_RW)
access = PF_ACCESS_WRITE;
else if (istate->error_word & PFERR_CODE_ID)
access = PF_ACCESS_EXEC;
else
access = PF_ACCESS_READ;
if (as_page_fault(page, access, istate) == AS_PF_FAULT) {
fault_if_from_uspace(istate, "Page fault: %#x", page);
print_info_errcode(n, istate);
printf("Page fault address: %llX\n", page);
panic("page fault\n");
}
}
__address hw_map(__address physaddr, size_t size)
{
if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
panic("Unable to map physical memory %p (%d bytes)", physaddr, size)
__address virtaddr = PA2KA(last_frame);
pfn_t i;
for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++)
page_mapping_insert(AS_KERNEL, virtaddr + PFN2ADDR(i), physaddr + PFN2ADDR(i), PAGE_NOT_CACHEABLE);
last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE);
return virtaddr;
}

/tags/0.2.0/kernel/arch/amd64/src/mm/memory_init.c
0,0 → 1,71
/*
* Copyright (C) 2005 Josef Cejka
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/boot/memmap.h>
#include <arch/mm/memory_init.h>
#include <arch/mm/page.h>
#include <print.h>
__u8 e820counter = 0xff;
struct e820memmap_ e820table[MEMMAP_E820_MAX_RECORDS];
__u32 e801memorysize;
size_t get_memory_size(void)
{
return e801memorysize*1024;
}
void memory_print_map(void)
{
__u8 i;
for (i=0;i<e820counter;i++) {
printf("E820 base: %#llX size: %#llX type: ", e820table[i].base_address, e820table[i].size);
switch (e820table[i].type) {
case MEMMAP_MEMORY_AVAILABLE:
printf("available memory\n");
break;
case MEMMAP_MEMORY_RESERVED:
printf("reserved memory\n");
break;
case MEMMAP_MEMORY_ACPI:
printf("ACPI table\n");
break;
case MEMMAP_MEMORY_NVS:
printf("NVS\n");
break;
case MEMMAP_MEMORY_UNUSABLE:
printf("unusable memory\n");
break;
default:
printf("undefined memory type\n");
}
}
}

/tags/0.2.0/kernel/arch/amd64/src/mm/as.c
0,0 → 1,0
link ../../../ia32/src/mm/as.c
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/src/mm/tlb.c
0,0 → 1,0
link ../../../ia32/src/mm/tlb.c
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/src/mm/frame.c
0,0 → 1,0
link ../../../ia32/src/mm/frame.c
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/src/interrupt.c
0,0 → 1,176
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/interrupt.h>
#include <print.h>
#include <debug.h>
#include <panic.h>
#include <arch/drivers/i8259.h>
#include <func.h>
#include <cpu.h>
#include <arch/asm.h>
#include <mm/tlb.h>
#include <mm/as.h>
#include <arch.h>
#include <symtab.h>
#include <arch/asm.h>
#include <proc/scheduler.h>
#include <proc/thread.h>
#include <proc/task.h>
#include <synch/spinlock.h>
#include <arch/ddi/ddi.h>
#include <interrupt.h>
#include <ipc/irq.h>
void print_info_errcode(int n, istate_t *istate)
{
char *symbol;
/* __u64 *x = &istate->stack[0]; */
if (!(symbol=get_symtab_entry(istate->rip)))
symbol = "";
printf("-----EXCEPTION(%d) OCCURED----- ( %s )\n",n, __FUNCTION__);
printf("%%rip: %#llX (%s)\n",istate->rip, symbol);
printf("ERROR_WORD=%#llX\n", istate->error_word);
printf("%%rcs=%#llX, flags=%#llX, %%cr0=%#llX\n", istate->cs, istate->rflags,read_cr0());
printf("%%rax=%#llX, %%rcx=%#llX, %%rdx=%#llX\n",istate->rax,istate->rcx,istate->rdx);
printf("%%rsi=%#llX, %%rdi=%#llX, %%r8 =%#llX\n",istate->rsi,istate->rdi,istate->r8);
printf("%%r9 =%#llX, %%r10 =%#llX, %%r11=%#llX\n",istate->r9,istate->r10,istate->r11);
#ifdef CONFIG_DEBUG_ALLREGS
printf("%%r12=%#llX, %%r13=%#llX, %%r14=%#llX\n",istate->r12,istate->r13,istate->r14);
printf("%%r15=%#llX, %%rbx=%#llX, %%rbp=%#llX\n",istate->r15,istate->rbx,&istate->rbp);
#endif
printf("%%rsp=%#llX\n",&istate->stack[0]);
}
/*
* Interrupt and exception dispatching.
*/
void (* disable_irqs_function)(__u16 irqmask) = NULL;
void (* enable_irqs_function)(__u16 irqmask) = NULL;
void (* eoi_function)(void) = NULL;
void null_interrupt(int n, istate_t *istate)
{
fault_if_from_uspace(istate, "unserviced interrupt: %d", n);
print_info_errcode(n, istate);
panic("unserviced interrupt\n");
}
/** General Protection Fault. */
void gp_fault(int n, istate_t *istate)
{
if (TASK) {
count_t ver;
spinlock_lock(&TASK->lock);
ver = TASK->arch.iomapver;
spinlock_unlock(&TASK->lock);
if (CPU->arch.iomapver_copy != ver) {
/*
* This fault can be caused by an early access
* to I/O port because of an out-dated
* I/O Permission bitmap installed on CPU.
* Install the fresh copy and restart
* the instruction.
*/
io_perm_bitmap_install();
return;
}
fault_if_from_uspace(istate, "general protection fault");
}
print_info_errcode(n, istate);
panic("general protection fault\n");
}
void ss_fault(int n, istate_t *istate)
{
fault_if_from_uspace(istate, "stack fault");
print_info_errcode(n, istate);
panic("stack fault\n");
}
void nm_fault(int n, istate_t *istate)
{
#ifdef CONFIG_FPU_LAZY
scheduler_fpu_lazy_request();
#else
fault_if_from_uspace(istate, "fpu fault");
panic("fpu fault");
#endif
}
void tlb_shootdown_ipi(int n, istate_t *istate)
{
trap_virtual_eoi();
tlb_shootdown_ipi_recv();
}
void trap_virtual_enable_irqs(__u16 irqmask)
{
if (enable_irqs_function)
enable_irqs_function(irqmask);
else
panic("no enable_irqs_function\n");
}
void trap_virtual_disable_irqs(__u16 irqmask)
{
if (disable_irqs_function)
disable_irqs_function(irqmask);
else
panic("no disable_irqs_function\n");
}
void trap_virtual_eoi(void)
{
if (eoi_function)
eoi_function();
else
panic("no eoi_function\n");
}
static void ipc_int(int n, istate_t *istate)
{
trap_virtual_eoi();
ipc_irq_send_notif(n-IVT_IRQBASE);
}
/* Reregister irq to be IPC-ready */
void irq_ipc_bind_arch(__native irq)
{
if (irq == IRQ_CLK)
return;
exc_register(IVT_IRQBASE+irq, "ipc_int", ipc_int);
}

/tags/0.2.0/kernel/arch/amd64/src/proc/task.c
0,0 → 1,51
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <proc/task.h>
#include <mm/slab.h>
#include <arch/types.h>
/** Perform amd64 specific task initialization.
*
* @param t Task to be initialized.
*/
void task_create_arch(task_t *t)
{
t->arch.iomapver = 0;
bitmap_initialize(&t->arch.iomap, NULL, 0);
}
/** Perform amd64 specific task destruction.
*
* @param t Task to be initialized.
*/
void task_destroy_arch(task_t *t)
{
if (t->arch.iomap.map)
free(t->arch.iomap.map);
}

/tags/0.2.0/kernel/arch/amd64/src/proc/scheduler.c
0,0 → 1,75
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <proc/scheduler.h>
#include <cpu.h>
#include <proc/task.h>
#include <proc/thread.h>
#include <arch.h>
#include <arch/context.h> /* SP_DELTA */
#include <arch/asm.h>
#include <arch/debugger.h>
#include <print.h>
#include <arch/pm.h>
#include <arch/ddi/ddi.h>
/** Perform amd64 specific tasks needed before the new task is run.
*
* Interrupts are disabled.
*/
void before_task_runs_arch(void)
{
io_perm_bitmap_install();
}
/** Perform amd64 specific tasks needed before the new thread is scheduled. */
void before_thread_runs_arch(void)
{
CPU->arch.tss->rsp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
/* Syscall support - write address of thread stack pointer to
* hidden part of gs */
swapgs();
write_msr(AMD_MSR_GS, (__u64)&THREAD->kstack);
swapgs();
/* TLS support - set FS to thread local storage */
write_msr(AMD_MSR_FS, THREAD->arch.tls);
#ifdef CONFIG_DEBUG_AS_WATCHPOINT
/* Set watchpoint on AS to ensure that nobody sets it to zero */
if (CPU->id < BKPOINTS_MAX)
breakpoint_add(&((the_t *) THREAD->kstack)->as,
BKPOINT_WRITE | BKPOINT_CHECK_ZERO,
CPU->id);
#endif
}
void after_thread_ran_arch(void)
{
}

/tags/0.2.0/kernel/arch/amd64/src/proc/thread.c
0,0 → 1,38
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <proc/thread.h>
/** Perform amd64 specific thread initialization.
*
* @param t Thread to be initialized.
*/
void thread_create_arch(thread_t *t)
{
t->arch.tls = 0;
}

/tags/0.2.0/kernel/arch/amd64/src/amd64.c
0,0 → 1,203
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <arch/types.h>
#include <config.h>
#include <proc/thread.h>
#include <arch/drivers/ega.h>
#include <arch/drivers/vesa.h>
#include <genarch/i8042/i8042.h>
#include <arch/drivers/i8254.h>
#include <arch/drivers/i8259.h>
#include <arch/bios/bios.h>
#include <arch/mm/memory_init.h>
#include <arch/cpu.h>
#include <print.h>
#include <arch/cpuid.h>
#include <genarch/acpi/acpi.h>
#include <panic.h>
#include <interrupt.h>
#include <arch/syscall.h>
#include <arch/debugger.h>
#include <syscall/syscall.h>
#include <console/console.h>
/** Disable I/O on non-privileged levels
*
* Clean IOPL(12,13) and NT(14) flags in EFLAGS register
*/
static void clean_IOPL_NT_flags(void)
{
asm
(
"pushfq;"
"pop %%rax;"
"and $~(0x7000),%%rax;"
"pushq %%rax;"
"popfq;"
:
:
:"%rax"
);
}
/** Disable alignment check
*
* Clean AM(18) flag in CR0 register
*/
static void clean_AM_flag(void)
{
asm
(
"mov %%cr0,%%rax;"
"and $~(0x40000),%%rax;"
"mov %%rax,%%cr0;"
:
:
:"%rax"
);
}
void arch_pre_mm_init(void)
{
struct cpu_info cpuid_s;
cpuid(AMD_CPUID_EXTENDED,&cpuid_s);
if (! (cpuid_s.cpuid_edx & (1<<AMD_EXT_NOEXECUTE)))
panic("Processor does not support No-execute pages.\n");
cpuid(INTEL_CPUID_STANDARD,&cpuid_s);
if (! (cpuid_s.cpuid_edx & (1<<INTEL_FXSAVE)))
panic("Processor does not support FXSAVE/FXRESTORE.\n");
if (! (cpuid_s.cpuid_edx & (1<<INTEL_SSE2)))
panic("Processor does not support SSE2 instructions.\n");
/* Enable No-execute pages */
set_efer_flag(AMD_NXE_FLAG);
/* Enable FPU */
cpu_setup_fpu();
/* Initialize segmentation */
pm_init();
/* Disable I/O on nonprivileged levels
* clear the NT(nested-thread) flag
*/
clean_IOPL_NT_flags();
/* Disable alignment check */
clean_AM_flag();
if (config.cpu_active == 1) {
bios_init();
i8259_init(); /* PIC */
i8254_init(); /* hard clock */
#ifdef CONFIG_SMP
exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
tlb_shootdown_ipi);
#endif /* CONFIG_SMP */
}
}
void arch_post_mm_init(void)
{
if (config.cpu_active == 1) {
#ifdef CONFIG_FB
if (vesa_present())
vesa_init();
else
#endif
ega_init(); /* video */
/* Enable debugger */
debugger_init();
/* Merge all memory zones to 1 big zone */
zone_merge_all();
}
/* Setup fast SYSCALL/SYSRET */
syscall_setup_cpu();
}
void arch_pre_smp_init(void)
{
if (config.cpu_active == 1) {
memory_print_map();
#ifdef CONFIG_SMP
acpi_init();
#endif /* CONFIG_SMP */
}
}
void arch_post_smp_init(void)
{
i8042_init(); /* keyboard controller */
}
void calibrate_delay_loop(void)
{
i8254_calibrate_delay_loop();
i8254_normal_operation();
}
/** Set thread-local-storage pointer
*
* TLS pointer is set in FS register. Unfortunately the 64-bit
* part can be set only in CPL0 mode.
*
* The specs say, that on %fs:0 there is stored contents of %fs register,
* we need not to go to CPL0 to read it.
*/
__native sys_tls_set(__native addr)
{
THREAD->arch.tls = addr;
write_msr(AMD_MSR_FS, addr);
return 0;
}
/** Acquire console back for kernel
*
*/
void arch_grab_console(void)
{
i8042_grab();
}
/** Return console to userspace
*
*/
void arch_release_console(void)
{
i8042_release();
}

/tags/0.2.0/kernel/arch/amd64/src/pm.c
0,0 → 1,235
/*
* Copyright (C) 2001-2004 Jakub Jermar
* Copyright (C) 2005-2006 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/pm.h>
#include <arch/mm/page.h>
#include <arch/types.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <interrupt.h>
#include <mm/as.h>
#include <config.h>
#include <memstr.h>
#include <mm/slab.h>
#include <debug.h>
/*
* There is no segmentation in long mode so we set up flat mode. In this
* mode, we use, for each privilege level, two segments spanning the
* whole memory. One is for code and one is for data.
*/
descriptor_t gdt[GDT_ITEMS] = {
/* NULL descriptor */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
/* KTEXT descriptor */
{ .limit_0_15 = 0xffff,
.base_0_15 = 0,
.base_16_23 = 0,
.access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE ,
.limit_16_19 = 0xf,
.available = 0,
.longmode = 1,
.special = 0,
.granularity = 1,
.base_24_31 = 0 },
/* KDATA descriptor */
{ .limit_0_15 = 0xffff,
.base_0_15 = 0,
.base_16_23 = 0,
.access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
.limit_16_19 = 0xf,
.available = 0,
.longmode = 0,
.special = 0,
.granularity = 1,
.base_24_31 = 0 },
/* UDATA descriptor */
{ .limit_0_15 = 0xffff,
.base_0_15 = 0,
.base_16_23 = 0,
.access = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
.limit_16_19 = 0xf,
.available = 0,
.longmode = 0,
.special = 1,
.granularity = 1,
.base_24_31 = 0 },
/* UTEXT descriptor */
{ .limit_0_15 = 0xffff,
.base_0_15 = 0,
.base_16_23 = 0,
.access = AR_PRESENT | AR_CODE | DPL_USER,
.limit_16_19 = 0xf,
.available = 0,
.longmode = 1,
.special = 0,
.granularity = 1,
.base_24_31 = 0 },
/* KTEXT 32-bit protected, for protected mode before long mode */
{ .limit_0_15 = 0xffff,
.base_0_15 = 0,
.base_16_23 = 0,
.access = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
.limit_16_19 = 0xf,
.available = 0,
.longmode = 0,
.special = 1,
.granularity = 1,
.base_24_31 = 0 },
/* TSS descriptor - set up will be completed later,
* on AMD64 it is 64-bit - 2 items in table */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
/* VESA Init descriptor */
#ifdef CONFIG_FB
{ 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
#endif
};
idescriptor_t idt[IDT_ITEMS];
ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base= (__u64) gdt };
ptr_16_64_t idtr = {.limit = sizeof(idt), .base= (__u64) idt };
static tss_t tss;
tss_t *tss_p = NULL;
void gdt_tss_setbase(descriptor_t *d, __address base)
{
tss_descriptor_t *td = (tss_descriptor_t *) d;
td->base_0_15 = base & 0xffff;
td->base_16_23 = ((base) >> 16) & 0xff;
td->base_24_31 = ((base) >> 24) & 0xff;
td->base_32_63 = ((base) >> 32);
}
void gdt_tss_setlimit(descriptor_t *d, __u32 limit)
{
struct tss_descriptor *td = (tss_descriptor_t *) d;
td->limit_0_15 = limit & 0xffff;
td->limit_16_19 = (limit >> 16) & 0xf;
}
void idt_setoffset(idescriptor_t *d, __address offset)
{
/*
* Offset is a linear address.
*/
d->offset_0_15 = offset & 0xffff;
d->offset_16_31 = offset >> 16 & 0xffff;
d->offset_32_63 = offset >> 32;
}
void tss_initialize(tss_t *t)
{
memsetb((__address) t, sizeof(tss_t), 0);
}
/*
* This function takes care of proper setup of IDT and IDTR.
*/
void idt_init(void)
{
idescriptor_t *d;
int i;
for (i = 0; i < IDT_ITEMS; i++) {
d = &idt[i];
d->unused = 0;
d->selector = gdtselector(KTEXT_DES);
d->present = 1;
d->type = AR_INTERRUPT; /* masking interrupt */
idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
exc_register(i, "undef", (iroutine)null_interrupt);
}
exc_register( 7, "nm_fault", nm_fault);
exc_register(12, "ss_fault", ss_fault);
exc_register(13, "gp_fault", gp_fault);
exc_register(14, "ident_mapper", ident_page_fault);
}
/** Initialize segmentation - code/data/idt tables
*
*/
void pm_init(void)
{
descriptor_t *gdt_p = (struct descriptor *) gdtr.base;
tss_descriptor_t *tss_desc;
/*
* Each CPU has its private GDT and TSS.
* All CPUs share one IDT.
*/
if (config.cpu_active == 1) {
idt_init();
/*
* NOTE: bootstrap CPU has statically allocated TSS, because
* the heap hasn't been initialized so far.
*/
tss_p = &tss;
}
else {
/* We are going to use malloc, which may return
* non boot-mapped pointer, initialize the CR3 register
* ahead of page_init */
write_cr3((__address) AS_KERNEL->page_table);
tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);
if (!tss_p)
panic("could not allocate TSS\n");
}
tss_initialize(tss_p);
tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
tss_desc->present = 1;
tss_desc->type = AR_TSS;
tss_desc->dpl = PL_KERNEL;
gdt_tss_setbase(&gdt_p[TSS_DES], (__address) tss_p);
gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
gdtr_load(&gdtr);
idtr_load(&idtr);
/*
* As of this moment, the current CPU has its own GDT pointing
* to its own TSS. We just need to load the TR register.
*/
tr_load(gdtselector(TSS_DES));
}

/tags/0.2.0/kernel/arch/amd64/src/asm_utils.S
0,0 → 1,303
#
# Copyright (C) 2005 Ondrej Palkovsky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#define IREGISTER_SPACE 120
#define IOFFSET_RAX 0x0
#define IOFFSET_RBX 0x8
#define IOFFSET_RCX 0x10
#define IOFFSET_RDX 0x18
#define IOFFSET_RSI 0x20
#define IOFFSET_RDI 0x28
#define IOFFSET_R8 0x30
#define IOFFSET_R9 0x38
#define IOFFSET_R10 0x40
#define IOFFSET_R11 0x48
#define IOFFSET_R12 0x50
#define IOFFSET_R13 0x58
#define IOFFSET_R14 0x60
#define IOFFSET_R15 0x68
#define IOFFSET_RBP 0x70
# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
# and 1 means interrupt with error word
#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
#include <arch/pm.h>
#include <arch/mm/page.h>
.text
.global interrupt_handlers
.global syscall_entry
.global panic_printf
panic_printf:
movq $halt, (%rsp)
jmp printf
.global cpuid
.global has_cpuid
.global rdtsc
.global read_efer_flag
.global set_efer_flag
.global memcpy
.global memcpy_from_uspace
.global memcpy_to_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace_failover_address
#define MEMCPY_DST %rdi
#define MEMCPY_SRC %rsi
#define MEMCPY_SIZE %rdx
/**
* Copy memory from/to userspace.
*
* This is almost conventional memcpy().
* The difference is that there is a failover part
* to where control is returned from a page fault if
* the page fault occurs during copy_from_uspace()
* or copy_to_uspace().
*
* @param MEMCPY_DST Destination address.
* @param MEMCPY_SRC Source address.
* @param MEMCPY_SIZE Number of bytes to copy.
*
* @retrun MEMCPY_SRC on success, 0 on failure.
*/
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
movq MEMCPY_SRC, %rax
movq MEMCPY_SIZE, %rcx
shrq $3, %rcx /* size / 8 */
rep movsq /* copy as much as possible word by word */
movq MEMCPY_SIZE, %rcx
andq $7, %rcx /* size % 8 */
jz 0f
rep movsb /* copy the rest byte by byte */
0:
ret /* return MEMCPY_SRC, success */
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
xorq %rax, %rax /* return 0, failure */
ret
## Determine CPUID support
#
# Return 0 in EAX if CPUID is not support, 1 if supported.
#
has_cpuid:
pushfq # store flags
popq %rax # read flags
movq %rax,%rdx # copy flags
btcl $21,%edx # swap the ID bit
pushq %rdx
popfq # propagate the change into flags
pushfq
popq %rdx # read flags
andl $(1<<21),%eax # interested only in ID bit
andl $(1<<21),%edx
xorl %edx,%eax # 0 if not supported, 1 if supported
ret
cpuid:
movq %rbx, %r10 # we have to preserve rbx across function calls
movl %edi,%eax # load the command into %eax
cpuid
movl %eax,0(%rsi)
movl %ebx,4(%rsi)
movl %ecx,8(%rsi)
movl %edx,12(%rsi)
movq %r10, %rbx
ret
rdtsc:
xorq %rax,%rax
rdtsc
ret
set_efer_flag:
movq $0xc0000080, %rcx
rdmsr
btsl %edi, %eax
wrmsr
ret
read_efer_flag:
movq $0xc0000080, %rcx
rdmsr
ret
# Push all general purpose registers on stack except %rbp, %rsp
.macro save_all_gpr
movq %rax, IOFFSET_RAX(%rsp)
movq %rcx, IOFFSET_RCX(%rsp)
movq %rdx, IOFFSET_RDX(%rsp)
movq %rsi, IOFFSET_RSI(%rsp)
movq %rdi, IOFFSET_RDI(%rsp)
movq %r8, IOFFSET_R8(%rsp)
movq %r9, IOFFSET_R9(%rsp)
movq %r10, IOFFSET_R10(%rsp)
movq %r11, IOFFSET_R11(%rsp)
#ifdef CONFIG_DEBUG_ALLREGS
movq %rbx, IOFFSET_RBX(%rsp)
movq %rbp, IOFFSET_RBP(%rsp)
movq %r12, IOFFSET_R12(%rsp)
movq %r13, IOFFSET_R13(%rsp)
movq %r14, IOFFSET_R14(%rsp)
movq %r15, IOFFSET_R15(%rsp)
#endif
.endm
.macro restore_all_gpr
movq IOFFSET_RAX(%rsp), %rax
movq IOFFSET_RCX(%rsp), %rcx
movq IOFFSET_RDX(%rsp), %rdx
movq IOFFSET_RSI(%rsp), %rsi
movq IOFFSET_RDI(%rsp), %rdi
movq IOFFSET_R8(%rsp), %r8
movq IOFFSET_R9(%rsp), %r9
movq IOFFSET_R10(%rsp), %r10
movq IOFFSET_R11(%rsp), %r11
#ifdef CONFIG_DEBUG_ALLREGS
movq IOFFSET_RBX(%rsp), %rbx
movq IOFFSET_RBP(%rsp), %rbp
movq IOFFSET_R12(%rsp), %r12
movq IOFFSET_R13(%rsp), %r13
movq IOFFSET_R14(%rsp), %r14
movq IOFFSET_R15(%rsp), %r15
#endif
.endm
#ifdef CONFIG_DEBUG_ALLREGS
# define INTERRUPT_ALIGN 256
#else
# define INTERRUPT_ALIGN 128
#endif
## Declare interrupt handlers
#
# Declare interrupt handlers for n interrupt
# vectors starting at vector i.
#
# The handlers call exc_dispatch().
#
.macro handler i n
/*
* Choose between version with error code and version without error code.
* Both versions have to be of the same size. amd64 assembly is, however,
* a little bit tricky. For instance, subq $0x80, %rsp and subq $0x78, %rsp
* can result in two instructions with different op-code lengths.
* Therefore we align the interrupt handlers.
*/
.iflt \i-32
.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
/*
* Version with error word.
*/
subq $IREGISTER_SPACE, %rsp
.else
/*
* Version without error word,
*/
subq $(IREGISTER_SPACE+8), %rsp
.endif
.else
/*
* Version without error word,
*/
subq $(IREGISTER_SPACE+8), %rsp
.endif
save_all_gpr
movq $(\i), %rdi # %rdi - first parameter
movq %rsp, %rsi # %rsi - pointer to istate
call exc_dispatch # exc_dispatch(i, istate)
restore_all_gpr
# $8 = Skip error word
addq $(IREGISTER_SPACE+8), %rsp
iretq
.align INTERRUPT_ALIGN
.if (\n-\i)-1
handler "(\i+1)",\n
.endif
.endm
.align INTERRUPT_ALIGN
interrupt_handlers:
h_start:
handler 0 IDT_ITEMS
h_end:
syscall_entry:
# Switch to hidden gs
swapgs
# %gs:0 now points to pointer to stack page
mov %gs:0, %r10 # We have a ptr to stack page in r10
addq $PAGE_SIZE-16, %r10 # We need some space to store old %sp
movq %rsp, 0(%r10) # Save old stack pointer to stack
movq %r10, %rsp # Change to new stack
pushq %rcx # Return address
pushq %r11 # Save flags
# Switch back to remain consistent
swapgs
sti
movq %r9, %rcx # Exchange last parameter as a third
call syscall_handler
cli # We will be touching stack pointer
popq %r11
popq %rcx
movq 0(%rsp), %rsp
sysretq
.data
.global interrupt_handler_size
interrupt_handler_size: .quad (h_end-h_start)/IDT_ITEMS

/tags/0.2.0/kernel/arch/amd64/src/ddi/ddi.c
0,0 → 1,157
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <ddi/ddi.h>
#include <arch/ddi/ddi.h>
#include <proc/task.h>
#include <arch/types.h>
#include <typedefs.h>
#include <adt/bitmap.h>
#include <mm/slab.h>
#include <arch/pm.h>
#include <errno.h>
#include <arch/cpu.h>
#include <arch.h>
#include <align.h>
/** Enable I/O space range for task.
*
* Interrupts are disabled and task is locked.
*
* @param task Task.
* @param ioaddr Startign I/O space address.
* @param size Size of the enabled I/O range.
*
* @return 0 on success or an error code from errno.h.
*/
int ddi_iospace_enable_arch(task_t *task, __address ioaddr, size_t size)
{
count_t bits;
bits = ioaddr + size;
if (bits > IO_PORTS)
return ENOENT;
if (task->arch.iomap.bits < bits) {
bitmap_t oldiomap;
__u8 *newmap;
/*
* The I/O permission bitmap is too small and needs to be grown.
*/
newmap = (__u8 *) malloc(BITS2BYTES(bits), FRAME_ATOMIC);
if (!newmap)
return ENOMEM;
bitmap_initialize(&oldiomap, task->arch.iomap.map, task->arch.iomap.bits);
bitmap_initialize(&task->arch.iomap, newmap, bits);
/*
* Mark the new range inaccessible.
*/
bitmap_set_range(&task->arch.iomap, oldiomap.bits, bits - oldiomap.bits);
/*
* In case there really existed smaller iomap,
* copy its contents and deallocate it.
*/
if (oldiomap.bits) {
bitmap_copy(&task->arch.iomap, &oldiomap, oldiomap.bits);
free(oldiomap.map);
}
}
/*
* Enable the range and we are done.
*/
bitmap_clear_range(&task->arch.iomap, (index_t) ioaddr, (count_t) size);
/*
* Increment I/O Permission bitmap generation counter.
*/
task->arch.iomapver++;
return 0;
}
/** Install I/O Permission bitmap.
*
* Current task's I/O permission bitmap, if any, is installed
* in the current CPU's TSS.
*
* Interrupts must be disabled prior this call.
*/
void io_perm_bitmap_install(void)
{
count_t bits;
ptr_16_64_t cpugdtr;
descriptor_t *gdt_p;
tss_descriptor_t *tss_desc;
count_t ver;
/* First, copy the I/O Permission Bitmap. */
spinlock_lock(&TASK->lock);
ver = TASK->arch.iomapver;
if ((bits = TASK->arch.iomap.bits)) {
bitmap_t iomap;
ASSERT(TASK->arch.iomap.map);
bitmap_initialize(&iomap, CPU->arch.tss->iomap, TSS_IOMAP_SIZE * 8);
bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits);
/*
* It is safe to set the trailing eight bits because of the extra
* convenience byte in TSS_IOMAP_SIZE.
*/
bitmap_set_range(&iomap, ALIGN_UP(TASK->arch.iomap.bits, 8), 8);
}
spinlock_unlock(&TASK->lock);
/*
* Second, adjust TSS segment limit.
* Take the extra ending byte will all bits set into account.
*/
gdtr_store(&cpugdtr);
gdt_p = (descriptor_t *) cpugdtr.base;
gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits));
gdtr_load(&cpugdtr);
/*
* Before we load new TSS limit, the current TSS descriptor
* type must be changed to describe inactive TSS.
*/
tss_desc = (tss_descriptor_t *) &gdt_p[TSS_DES];
tss_desc->type = AR_TSS;
tr_load(gdtselector(TSS_DES));
/*
* Update the generation count so that faults caused by
* early accesses can be serviced.
*/
CPU->arch.iomapver_copy = ver;
}

/tags/0.2.0/kernel/arch/amd64/src/smp/ap.S
0,0 → 1,115
#
# Copyright (C) 2001-2004 Jakub Jermar
# Copyright (C) 2005-2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#
# Init code for application processors.
#
#include <arch/boot/boot.h>
#include <arch/boot/memmap.h>
#include <arch/mm/page.h>
#include <arch/pm.h>
#include <arch/cpu.h>
#include <arch/cpuid.h>
.section K_TEXT_START, "ax"
#ifdef CONFIG_SMP
.global unmapped_ap_boot
# This piece of code is real-mode and is meant to be alligned at 4K boundary.
# The requirement for such an alignment comes from MP Specification's STARTUP IPI
# requirements.
.align 4096
unmapped_ap_boot:
.code16
cli
xorw %ax, %ax
movw %ax, %ds
lgdtl ap_gdtr # initialize Global Descriptor Table register
movl %cr0, %eax
orl $1, %eax
movl %eax, %cr0 # switch to protected mode
jmpl $gdtselector(KTEXT32_DES), $jump_to_kernel - BOOT_OFFSET + AP_BOOT_OFFSET
jump_to_kernel:
.code32
movw $gdtselector(KDATA_DES), %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
movw $gdtselector(UDATA_DES), %ax
movw %ax, %gs
# Enable 64-bit page transaltion entries - CR4.PAE = 1.
# Paging is not enabled until after long mode is enabled
movl %cr4, %eax
btsl $5, %eax
movl %eax, %cr4
leal ptl_0, %eax
movl %eax, %cr3
# Enable long mode
movl $EFER_MSR_NUM, %ecx # EFER MSR number
rdmsr # Read EFER
btsl $AMD_LME_FLAG, %eax # Set LME=1
wrmsr # Write EFER
# Enable paging to activate long mode (set CR0.PG=1)
movl %cr0, %eax
btsl $31, %eax
movl %eax, %cr0
# At this point we are in compatibility mode
jmpl $gdtselector(KTEXT_DES), $start64 - BOOT_OFFSET + AP_BOOT_OFFSET
.code64
start64:
movq (ctx), %rsp
call main_ap - AP_BOOT_OFFSET + BOOT_OFFSET # never returns
#endif /* CONFIG_SMP */
.section K_DATA_START, "aw", @progbits
#ifdef CONFIG_SMP
.global unmapped_ap_gdtr
unmapped_ap_gdtr:
.word 0
.long 0
#endif /* CONFIG_SMP */

/tags/0.2.0/kernel/arch/amd64/src/smp/mps.c
0,0 → 1,0
link ../../../ia32/src/smp/mps.c
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/src/smp/smp.c
0,0 → 1,0
link ../../../ia32/src/smp/smp.c
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/src/smp/ipi.c
0,0 → 1,0
link ../../../ia32/src/smp/ipi.c
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/src/smp/apic.c
0,0 → 1,0
link ../../../ia32/src/smp/apic.c
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/src/debugger.c
0,0 → 1,377
/*
* Copyright (C) 2006 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/debugger.h>
#include <console/kconsole.h>
#include <console/cmd.h>
#include <symtab.h>
#include <print.h>
#include <panic.h>
#include <interrupt.h>
#include <arch/asm.h>
#include <arch/cpu.h>
#include <debug.h>
#include <func.h>
#include <smp/ipi.h>
typedef struct {
__address address; /**< Breakpoint address */
int flags; /**< Flags regarding breakpoint */
int counter; /**< How many times the exception occured */
} bpinfo_t;
static bpinfo_t breakpoints[BKPOINTS_MAX];
SPINLOCK_INITIALIZE(bkpoint_lock);
static int cmd_print_breakpoints(cmd_arg_t *argv);
static cmd_info_t bkpts_info = {
.name = "bkpts",
.description = "Print breakpoint table.",
.func = cmd_print_breakpoints,
.argc = 0,
};
#ifndef CONFIG_DEBUG_AS_WATCHPOINT
static int cmd_del_breakpoint(cmd_arg_t *argv);
static cmd_arg_t del_argv = {
.type = ARG_TYPE_INT
};
static cmd_info_t delbkpt_info = {
.name = "delbkpt",
.description = "delbkpt <number> - Delete breakpoint.",
.func = cmd_del_breakpoint,
.argc = 1,
.argv = &del_argv
};
static int cmd_add_breakpoint(cmd_arg_t *argv);
static cmd_arg_t add_argv = {
.type = ARG_TYPE_INT
};
static cmd_info_t addbkpt_info = {
.name = "addbkpt",
.description = "addbkpt <&symbol> - new breakpoint.",
.func = cmd_add_breakpoint,
.argc = 1,
.argv = &add_argv
};
static cmd_arg_t addw_argv = {
.type = ARG_TYPE_INT
};
static cmd_info_t addwatchp_info = {
.name = "addwatchp",
.description = "addbwatchp <&symbol> - new write watchpoint.",
.func = cmd_add_breakpoint,
.argc = 1,
.argv = &addw_argv
};
#endif
/** Print table of active breakpoints */
int cmd_print_breakpoints(cmd_arg_t *argv)
{
int i;
char *symbol;
printf("Breakpoint table.\n");
for (i=0; i < BKPOINTS_MAX; i++)
if (breakpoints[i].address) {
symbol = get_symtab_entry(breakpoints[i].address);
printf("%d. %p in %s\n",i,
breakpoints[i].address, symbol);
printf(" Count(%d) ", breakpoints[i].counter);
printf("\n");
}
return 1;
}
/* Setup DR register according to table */
static void setup_dr(int curidx)
{
__native dr7;
bpinfo_t *cur = &breakpoints[curidx];
int flags = breakpoints[curidx].flags;
/* Disable breakpoint in DR7 */
dr7 = read_dr7();
dr7 &= ~(0x2 << (curidx*2));
if (cur->address) { /* Setup DR register */
/* Set breakpoint to debug registers */
switch (curidx) {
case 0:
write_dr0(cur->address);
break;
case 1:
write_dr1(cur->address);
break;
case 2:
write_dr2(cur->address);
break;
case 3:
write_dr3(cur->address);
break;
}
/* Set type to requested breakpoint & length*/
dr7 &= ~ (0x3 << (16 + 4*curidx));
dr7 &= ~ (0x3 << (18 + 4*curidx));
if ((flags & BKPOINT_INSTR)) {
;
} else {
if (sizeof(int) == 4)
dr7 |= ((__native) 0x3) << (18 + 4*curidx);
else /* 8 */
dr7 |= ((__native) 0x2) << (18 + 4*curidx);
if ((flags & BKPOINT_WRITE))
dr7 |= ((__native) 0x1) << (16 + 4*curidx);
else if ((flags & BKPOINT_READ_WRITE))
dr7 |= ((__native) 0x3) << (16 + 4*curidx);
}
/* Enable global breakpoint */
dr7 |= 0x2 << (curidx*2);
write_dr7(dr7);
}
}
/** Enable hardware breakpoint
*
*
* @param where Address of HW breakpoint
* @param flags Type of breakpoint (EXECUTE, WRITE)
* @return Debug slot on success, -1 - no available HW breakpoint
*/
int breakpoint_add(void * where, int flags, int curidx)
{
ipl_t ipl;
int i;
bpinfo_t *cur;
ASSERT( flags & (BKPOINT_INSTR | BKPOINT_WRITE | BKPOINT_READ_WRITE));
ipl = interrupts_disable();
spinlock_lock(&bkpoint_lock);
if (curidx == -1) {
/* Find free space in slots */
for (i=0; i<BKPOINTS_MAX; i++)
if (!breakpoints[i].address) {
curidx = i;
break;
}
if (curidx == -1) {
/* Too many breakpoints */
spinlock_unlock(&bkpoint_lock);
interrupts_restore(ipl);
return -1;
}
}
cur = &breakpoints[curidx];
cur->address = (__address) where;
cur->flags = flags;
cur->counter = 0;
setup_dr(curidx);
spinlock_unlock(&bkpoint_lock);
interrupts_restore(ipl);
/* Send IPI */
#ifdef CONFIG_SMP
// ipi_broadcast(VECTOR_DEBUG_IPI);
#endif
return curidx;
}
#ifdef amd64
# define getip(x) ((x)->rip)
#else
# define getip(x) ((x)->eip)
#endif
static void handle_exception(int slot, istate_t *istate)
{
ASSERT(breakpoints[slot].address);
/* Handle zero checker */
if (! (breakpoints[slot].flags & BKPOINT_INSTR)) {
if ((breakpoints[slot].flags & BKPOINT_CHECK_ZERO)) {
if (*((__native *) breakpoints[slot].address) != 0)
return;
printf("**** Found ZERO on address %p ****\n",
slot, breakpoints[slot].address);
} else {
printf("Data watchpoint - new data: %p\n",
*((__native *) breakpoints[slot].address));
}
}
printf("Reached breakpoint %d:%p(%s)\n", slot, getip(istate),
get_symtab_entry(getip(istate)));
printf("***Type 'exit' to exit kconsole.\n");
atomic_set(&haltstate,1);
kconsole("debug");
atomic_set(&haltstate,0);
}
void breakpoint_del(int slot)
{
bpinfo_t *cur;
ipl_t ipl;
ipl = interrupts_disable();
spinlock_lock(&bkpoint_lock);
cur = &breakpoints[slot];
if (!cur->address) {
spinlock_unlock(&bkpoint_lock);
interrupts_restore(ipl);
return;
}
cur->address = NULL;
setup_dr(slot);
spinlock_unlock(&bkpoint_lock);
interrupts_restore(ipl);
#ifdef CONFIG_SMP
// ipi_broadcast(VECTOR_DEBUG_IPI);
#endif
}
#ifndef CONFIG_DEBUG_AS_WATCHPOINT
/** Remove breakpoint from table */
int cmd_del_breakpoint(cmd_arg_t *argv)
{
if (argv->intval < 0 || argv->intval > BKPOINTS_MAX) {
printf("Invalid breakpoint number.\n");
return 0;
}
breakpoint_del(argv->intval);
return 1;
}
/** Add new breakpoint to table */
static int cmd_add_breakpoint(cmd_arg_t *argv)
{
int flags;
int id;
if (argv == &add_argv) {
flags = BKPOINT_INSTR;
} else { /* addwatchp */
flags = BKPOINT_WRITE;
}
printf("Adding breakpoint on address: %p\n", argv->intval);
id = breakpoint_add((void *)argv->intval, flags, -1);
if (id < 0)
printf("Add breakpoint failed.\n");
else
printf("Added breakpoint %d.\n", id);
return 1;
}
#endif
static void debug_exception(int n, istate_t *istate)
{
__native dr6;
int i;
/* Set RF to restart the instruction */
#ifdef amd64
istate->rflags |= RFLAGS_RF;
#else
istate->eflags |= EFLAGS_RF;
#endif
dr6 = read_dr6();
for (i=0; i < BKPOINTS_MAX; i++) {
if (dr6 & (1 << i)) {
dr6 &= ~ (1 << i);
write_dr6(dr6);
handle_exception(i, istate);
}
}
}
#ifdef CONFIG_SMP
static void debug_ipi(int n, istate_t *istate)
{
int i;
spinlock_lock(&bkpoint_lock);
for (i=0; i < BKPOINTS_MAX; i++)
setup_dr(i);
spinlock_unlock(&bkpoint_lock);
}
#endif
/** Initialize debugger */
void debugger_init()
{
int i;
for (i=0; i<BKPOINTS_MAX; i++)
breakpoints[i].address = NULL;
cmd_initialize(&bkpts_info);
if (!cmd_register(&bkpts_info))
panic("could not register command %s\n", bkpts_info.name);
#ifndef CONFIG_DEBUG_AS_WATCHPOINT
cmd_initialize(&delbkpt_info);
if (!cmd_register(&delbkpt_info))
panic("could not register command %s\n", delbkpt_info.name);
cmd_initialize(&addbkpt_info);
if (!cmd_register(&addbkpt_info))
panic("could not register command %s\n", addbkpt_info.name);
cmd_initialize(&addwatchp_info);
if (!cmd_register(&addwatchp_info))
panic("could not register command %s\n", addwatchp_info.name);
#endif
exc_register(VECTOR_DEBUG, "debugger",
debug_exception);
#ifdef CONFIG_SMP
exc_register(VECTOR_DEBUG_IPI, "debugger_smp",
debug_ipi);
#endif
}

/tags/0.2.0/kernel/arch/amd64/src/cpu/cpu.c
0,0 → 1,159
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/cpu.h>
#include <arch/cpuid.h>
#include <arch/pm.h>
#include <arch.h>
#include <arch/types.h>
#include <print.h>
#include <typedefs.h>
#include <fpu_context.h>
/*
* Identification of CPUs.
* Contains only non-MP-Specification specific SMP code.
*/
#define AMD_CPUID_EBX 0x68747541
#define AMD_CPUID_ECX 0x444d4163
#define AMD_CPUID_EDX 0x69746e65
#define INTEL_CPUID_EBX 0x756e6547
#define INTEL_CPUID_ECX 0x6c65746e
#define INTEL_CPUID_EDX 0x49656e69
enum vendor {
VendorUnknown=0,
VendorAMD,
VendorIntel
};
static char *vendor_str[] = {
"Unknown Vendor",
"AuthenticAMD",
"GenuineIntel"
};
/** Setup flags on processor so that we can use the FPU
*
* cr0.osfxsr = 1 -> we do support fxstor/fxrestor
* cr0.em = 0 -> we do not emulate coprocessor
* cr0.mp = 1 -> we do want lazy context switch
*/
void cpu_setup_fpu(void)
{
__asm__ volatile (
"movq %%cr0, %%rax;"
"btsq $1, %%rax;" /* cr0.mp */
"btrq $2, %%rax;" /* cr0.em */
"movq %%rax, %%cr0;"
"movq %%cr4, %%rax;"
"bts $9, %%rax;" /* cr4.osfxsr */
"movq %%rax, %%cr4;"
:
:
:"%rax"
);
}
/** Set the TS flag to 1.
*
* If a thread accesses coprocessor, exception is run, which
* does a lazy fpu context switch.
*
*/
void fpu_disable(void)
{
__asm__ volatile (
"mov %%cr0,%%rax;"
"bts $3,%%rax;"
"mov %%rax,%%cr0;"
:
:
:"%rax"
);
}
void fpu_enable(void)
{
__asm__ volatile (
"mov %%cr0,%%rax;"
"btr $3,%%rax;"
"mov %%rax,%%cr0;"
:
:
:"%rax"
);
}
void cpu_arch_init(void)
{
CPU->arch.tss = tss_p;
CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((__u8 *) CPU->arch.tss);
CPU->fpu_owner = NULL;
}
void cpu_identify(void)
{
cpu_info_t info;
CPU->arch.vendor = VendorUnknown;
if (has_cpuid()) {
cpuid(0, &info);
/*
* Check for AMD processor.
*/
if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
CPU->arch.vendor = VendorAMD;
}
/*
* Check for Intel processor.
*/
if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
CPU->arch.vendor = VendorIntel;
}
cpuid(1, &info);
CPU->arch.family = (info.cpuid_eax>>8)&0xf;
CPU->arch.model = (info.cpuid_eax>>4)&0xf;
CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;
}
}
void cpu_print_report(cpu_t* m)
{
printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
m->frequency_mhz);
}

/tags/0.2.0/kernel/arch/amd64/src/userspace.c
0,0 → 1,72
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <userspace.h>
#include <arch/pm.h>
#include <arch/types.h>
#include <arch.h>
#include <proc/uarg.h>
#include <mm/as.h>
/** Enter userspace
*
* Change CPU protection level to 3, enter userspace.
*
*/
void userspace(uspace_arg_t *kernel_uarg)
{
ipl_t ipl;
ipl = interrupts_disable();
/* Clear CF,PF,AF,ZF,SF,DF,OF */
ipl &= ~(0xcd4);
__asm__ volatile (""
"pushq %0\n"
"pushq %1\n"
"pushq %2\n"
"pushq %3\n"
"pushq %4\n"
"movq %5, %%rax\n"
"iretq\n"
: :
"i" (gdtselector(UDATA_DES) | PL_USER),
"r" (kernel_uarg->uspace_stack+THREAD_STACK_SIZE),
"r" (ipl),
"i" (gdtselector(UTEXT_DES) | PL_USER),
"r" (kernel_uarg->uspace_entry),
"r" (kernel_uarg->uspace_uarg)
: "rax"
);
/* Unreachable */
for(;;)
;
}

/tags/0.2.0/kernel/arch/amd64/src/syscall.c
0,0 → 1,62
/*
* Copyright (C) 2006 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <syscall/syscall.h>
#include <arch/syscall.h>
#include <panic.h>
#include <arch/cpu.h>
#include <arch/pm.h>
#include <arch/asm.h>
#include <print.h>
#include <arch/cpu.h>
extern void syscall_entry(void);
/** Enable & setup support for SYSCALL/SYSRET */
void syscall_setup_cpu(void)
{
/* Enable SYSCALL/SYSRET */
set_efer_flag(AMD_SCE_FLAG);
/* Setup syscall entry address */
/* This is _mess_ - the 64-bit CS is argument+16,
* the SS is argument+8. The order is:
* +0(KDATA_DES), +8(UDATA_DES), +16(UTEXT_DES)
*/
write_msr(AMD_MSR_STAR,
((__u64)(gdtselector(KDATA_DES) | PL_USER)<<48) \
| ((__u64)(gdtselector(KTEXT_DES) | PL_KERNEL)<<32));
write_msr(AMD_MSR_LSTAR, (__u64)syscall_entry);
/* Mask RFLAGS on syscall
* - disable interrupts, until we exchange the stack register
* (mask the IE bit)
*/
write_msr(AMD_MSR_SFMASK, 0x200);
}

/tags/0.2.0/kernel/arch/amd64/src/fpu_context.c
0,0 → 1,58
/*
* Copyright (C) 2005 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <fpu_context.h>
#include <arch.h>
#include <cpu.h>
/** Save FPU (mmx, sse) context using fxsave instruction */
void fpu_context_save(fpu_context_t *fctx)
{
__asm__ volatile (
"fxsave %0"
: "=m"(*fctx)
);
}
/** Restore FPU (mmx,sse) context using fxrstor instruction */
void fpu_context_restore(fpu_context_t *fctx)
{
__asm__ volatile (
"fxrstor %0"
: "=m"(*fctx)
);
}
void fpu_init()
{
/* TODO: Zero all SSE, MMX etc. registers */
__asm__ volatile (
"fninit;"
);
}

/tags/0.2.0/kernel/arch/amd64/src/bios
0,0 → 1,0
link ../../ia32/src/bios
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/src/drivers
0,0 → 1,0
link ../../ia32/src/drivers
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/src/context.S
0,0 → 1,78
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
.global context_save_arch
.global context_restore_arch
#include <arch/context_offset.h>
## Save current CPU context
#
# Save CPU context to context_t variable
# pointed by the 1st argument. Returns 1 in EAX.
#
context_save_arch:
movq (%rsp), %rdx # the caller's return %eip
# In %edi is passed 1st argument
movq %rdx, OFFSET_PC(%rdi)
movq %rsp, OFFSET_SP(%rdi)
movq %rbx, OFFSET_RBX(%rdi)
movq %rbp, OFFSET_RBP(%rdi)
movq %r12, OFFSET_R12(%rdi)
movq %r13, OFFSET_R13(%rdi)
movq %r14, OFFSET_R14(%rdi)
movq %r15, OFFSET_R15(%rdi)
xorq %rax,%rax # context_save returns 1
incq %rax
ret
## Restore current CPU context
#
# Restore CPU context from context_t variable
# pointed by the 1st argument. Returns 0 in EAX.
#
context_restore_arch:
movq OFFSET_R15(%rdi), %r15
movq OFFSET_R14(%rdi), %r14
movq OFFSET_R13(%rdi), %r13
movq OFFSET_R12(%rdi), %r12
movq OFFSET_RBP(%rdi), %rbp
movq OFFSET_RBX(%rdi), %rbx
movq OFFSET_SP(%rdi), %rsp # ctx->sp -> %rsp
movq OFFSET_PC(%rdi), %rdx
movq %rdx,(%rsp)
xorq %rax,%rax # context_restore returns 0
ret

/tags/0.2.0/kernel/arch/amd64/src/delay.S
0,0 → 1,46
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#
# Micro second delay loop functions.
#
.text
.global asm_delay_loop
.global asm_fake_loop
asm_delay_loop:
0: dec %rdi
jnz 0b
ret
asm_fake_loop:
0: dec %rdi
jz 0b
ret

/tags/0.2.0/kernel/arch/amd64/include/interrupt.h
0,0 → 1,123
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_INTERRUPT_H__
#define __ia32_INTERRUPT_H__
#include <arch/types.h>
#include <arch/pm.h>
#define IVT_ITEMS IDT_ITEMS
#define EXC_COUNT 32
#define IRQ_COUNT 16
#define IVT_EXCBASE 0
#define IVT_IRQBASE (IVT_EXCBASE+EXC_COUNT)
#define IVT_FREEBASE (IVT_IRQBASE+IRQ_COUNT)
#define IRQ_CLK 0
#define IRQ_KBD 1
#define IRQ_PIC1 2
#define IRQ_PIC_SPUR 7
/* this one must have four least significant bits set to ones */
#define VECTOR_APIC_SPUR (IVT_ITEMS-1)
#if (((VECTOR_APIC_SPUR + 1)%16) || VECTOR_APIC_SPUR >= IVT_ITEMS)
#error Wrong definition of VECTOR_APIC_SPUR
#endif
#define VECTOR_DEBUG 1
#define VECTOR_PIC_SPUR (IVT_IRQBASE+IRQ_PIC_SPUR)
#define VECTOR_CLK (IVT_IRQBASE+IRQ_CLK)
#define VECTOR_KBD (IVT_IRQBASE+IRQ_KBD)
#define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE+0)
#define VECTOR_WAKEUP_IPI (IVT_FREEBASE+1)
#define VECTOR_DEBUG_IPI (IVT_FREEBASE+2)
/** This is passed to interrupt handlers */
struct istate {
__u64 rax;
__u64 rbx;
__u64 rcx;
__u64 rdx;
__u64 rsi;
__u64 rdi;
__u64 r8;
__u64 r9;
__u64 r10;
__u64 r11;
__u64 r12;
__u64 r13;
__u64 r14;
__u64 r15;
__u64 rbp;
__u64 error_word;
__u64 rip;
__u64 cs;
__u64 rflags;
__u64 stack[]; /* Additional data on stack */
};
/** Return true if exception happened while in userspace */
static inline int istate_from_uspace(istate_t *istate)
{
return !(istate->rip & 0x8000000000000000);
}
static inline void istate_set_retaddr(istate_t *istate, __address retaddr)
{
istate->rip = retaddr;
}
static inline __native istate_get_pc(istate_t *istate)
{
return istate->rip;
}
extern void (* disable_irqs_function)(__u16 irqmask);
extern void (* enable_irqs_function)(__u16 irqmask);
extern void (* eoi_function)(void);
extern void print_info_errcode(int n, istate_t *istate);
extern void null_interrupt(int n, istate_t *istate);
extern void gp_fault(int n, istate_t *istate);
extern void nm_fault(int n, istate_t *istate);
extern void ss_fault(int n, istate_t *istate);
extern void page_fault(int n, istate_t *istate);
extern void syscall(int n, istate_t *istate);
extern void tlb_shootdown_ipi(int n, istate_t *istate);
extern void trap_virtual_enable_irqs(__u16 irqmask);
extern void trap_virtual_disable_irqs(__u16 irqmask);
extern void trap_virtual_eoi(void);
/* AMD64 - specific page handler */
extern void ident_page_fault(int n, istate_t *istate);
#endif

/tags/0.2.0/kernel/arch/amd64/include/mm/as.h
0,0 → 1,45
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_AS_H__
#define __amd64_AS_H__
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0
#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0xffff800000000000
#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff
#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000
#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0x00007fffffffffff
#define USTACK_ADDRESS_ARCH (USER_ADDRESS_SPACE_END_ARCH-(PAGE_SIZE-1))
#define as_install_arch(as)
extern void as_arch_init(void);
#endif

/tags/0.2.0/kernel/arch/amd64/include/mm/page.h
0,0 → 1,192
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** Paging on AMD64
*
* The space is divided in positive numbers - userspace and
* negative numbers - kernel space. The 'negative' space starting
* with 0xffff800000000000 and ending with 0xffffffff80000000
* (-2GB) is identically mapped physical memory. The area
* (0xffffffff80000000 ... 0xffffffffffffffff is again identically
* mapped first 2GB.
*
* ATTENTION - PA2KA(KA2PA(x)) != x if 'x' is in kernel
*/
#ifndef __amd64_PAGE_H__
#define __amd64_PAGE_H__
#include <arch/mm/frame.h>
#define PAGE_WIDTH FRAME_WIDTH
#define PAGE_SIZE FRAME_SIZE
#ifdef KERNEL
#ifndef __ASM__
# include <mm/page.h>
# include <arch/types.h>
#endif
#ifndef __ASM__
static inline __address ka2pa(__address x)
{
if (x > 0xffffffff80000000)
return x - 0xffffffff80000000;
else
return x - 0xffff800000000000;
}
# define KA2PA(x) ka2pa((__address)x)
# define PA2KA_CODE(x) (((__address) (x)) + 0xffffffff80000000)
# define PA2KA(x) (((__address) (x)) + 0xffff800000000000)
#else
# define KA2PA(x) ((x) - 0xffffffff80000000)
# define PA2KA(x) ((x) + 0xffffffff80000000)
#endif
#define PTL0_ENTRIES_ARCH 512
#define PTL1_ENTRIES_ARCH 512
#define PTL2_ENTRIES_ARCH 512
#define PTL3_ENTRIES_ARCH 512
#define PTL0_INDEX_ARCH(vaddr) (((vaddr)>>39)&0x1ff)
#define PTL1_INDEX_ARCH(vaddr) (((vaddr)>>30)&0x1ff)
#define PTL2_INDEX_ARCH(vaddr) (((vaddr)>>21)&0x1ff)
#define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>12)&0x1ff)
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *) ((((__u64) ((pte_t *)(ptl0))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl0))[(i)].addr_32_51)<<32 )))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) ((pte_t *) ((((__u64) ((pte_t *)(ptl1))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl1))[(i)].addr_32_51)<<32 )))
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) ((pte_t *) ((((__u64) ((pte_t *)(ptl2))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl2))[(i)].addr_32_51)<<32 )))
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((__address *) ((((__u64) ((pte_t *)(ptl3))[(i)].addr_12_31)<<12) | (((__u64) ((pte_t *)(ptl3))[(i)].addr_32_51)<<32 )))
#define SET_PTL0_ADDRESS_ARCH(ptl0) (write_cr3((__address) (ptl0)))
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) set_pt_addr((pte_t *)(ptl0), (index_t)(i), a)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a) set_pt_addr((pte_t *)(ptl1), (index_t)(i), a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a) set_pt_addr((pte_t *)(ptl2), (index_t)(i), a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) set_pt_addr((pte_t *)(ptl3), (index_t)(i), a)
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) get_pt_flags((pte_t *)(ptl1), (index_t)(i))
#define GET_PTL3_FLAGS_ARCH(ptl2, i) get_pt_flags((pte_t *)(ptl2), (index_t)(i))
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i))
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x) set_pt_flags((pte_t *)(ptl1), (index_t)(i), (x))
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x) set_pt_flags((pte_t *)(ptl2), (index_t)(i), (x))
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
#define PTE_VALID_ARCH(p) (*((__u64 *) (p)) != 0)
#define PTE_PRESENT_ARCH(p) ((p)->present != 0)
#define PTE_GET_FRAME_ARCH(p) ((((__address)(p)->addr_12_31)<<12) | ((__address)(p)->addr_32_51<<32))
#define PTE_WRITABLE_ARCH(p) ((p)->writeable != 0)
#define PTE_EXECUTABLE_ARCH(p) ((p)->no_execute == 0)
#ifndef __ASM__
/* Page fault error codes. */
/** When bit on this position is 0, the page fault was caused by a not-present page. */
#define PFERR_CODE_P (1<<0)
/** When bit on this position is 1, the page fault was caused by a write. */
#define PFERR_CODE_RW (1<<1)
/** When bit on this position is 1, the page fault was caused in user mode. */
#define PFERR_CODE_US (1<<2)
/** When bit on this position is 1, a reserved bit was set in page directory. */
#define PFERR_CODE_RSVD (1<<3)
/** When bit on this position os 1, the page fault was caused during instruction fecth. */
#define PFERR_CODE_ID (1<<4)
/** Page Table Entry. */
struct page_specifier {
unsigned present : 1;
unsigned writeable : 1;
unsigned uaccessible : 1;
unsigned page_write_through : 1;
unsigned page_cache_disable : 1;
unsigned accessed : 1;
unsigned dirty : 1;
unsigned unused: 1;
unsigned global : 1;
unsigned soft_valid : 1; /**< Valid content even if present bit is cleared. */
unsigned avl : 2;
unsigned addr_12_31 : 30;
unsigned addr_32_51 : 21;
unsigned no_execute : 1;
} __attribute__ ((packed));
static inline int get_pt_flags(pte_t *pt, index_t i)
{
pte_t *p = &pt[i];
return (
(!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT |
(!p->present)<<PAGE_PRESENT_SHIFT |
p->uaccessible<<PAGE_USER_SHIFT |
1<<PAGE_READ_SHIFT |
p->writeable<<PAGE_WRITE_SHIFT |
(!p->no_execute)<<PAGE_EXEC_SHIFT |
p->global<<PAGE_GLOBAL_SHIFT
);
}
static inline void set_pt_addr(pte_t *pt, index_t i, __address a)
{
pte_t *p = &pt[i];
p->addr_12_31 = (a >> 12) & 0xfffff;
p->addr_32_51 = a >> 32;
}
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
{
pte_t *p = &pt[i];
p->page_cache_disable = !(flags & PAGE_CACHEABLE);
p->present = !(flags & PAGE_NOT_PRESENT);
p->uaccessible = (flags & PAGE_USER) != 0;
p->writeable = (flags & PAGE_WRITE) != 0;
p->no_execute = (flags & PAGE_EXEC) == 0;
p->global = (flags & PAGE_GLOBAL) != 0;
/*
* Ensure that there is at least one bit set even if the present bit is cleared.
*/
p->soft_valid = 1;
}
extern void page_arch_init(void);
#endif /* __ASM__ */
#endif /* KERNEL */
#endif

/tags/0.2.0/kernel/arch/amd64/include/mm/frame.h
0,0 → 1,45
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_FRAME_H__
#define __amd64_FRAME_H__
#ifndef __ASM__
#include <arch/types.h>
#endif /* __ASM__ */
#define FRAME_WIDTH 12 /* 4K */
#define FRAME_SIZE (1<<FRAME_WIDTH)
#ifndef __ASM__
extern __address last_frame;
extern void frame_arch_init(void);
#endif /* __ASM__ */
#endif

/tags/0.2.0/kernel/arch/amd64/include/mm/asid.h
0,0 → 1,0
link ../../../ia32/include/mm/asid.h
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/include/mm/tlb.h
0,0 → 1,35
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_TLB_H__
#define __amd64_TLB_H__
#define tlb_arch_init()
#define tlb_print()
#endif

/tags/0.2.0/kernel/arch/amd64/include/mm/memory_init.h
0,0 → 1,0
link ../../../ia32/include/mm/memory_init.h
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/include/mm/ptl.h
0,0 → 1,43
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_PTL_H_
#define __amd64_PTL_H_
#define PTL_NO_EXEC (1<<63)
#define PTL_ACCESSED (1<<5)
#define PTL_CACHE_DISABLE (1<<4)
#define PTL_CACHE_THROUGH (1<<3)
#define PTL_USER (1<<2)
#define PTL_WRITABLE (1<<1)
#define PTL_PRESENT 1
#define PTL_2MB_PAGE (1<<7)
#endif

/tags/0.2.0/kernel/arch/amd64/include/drivers/i8254.h
0,0 → 1,0
link ../../../ia32/include/drivers/i8254.h
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/include/drivers/vesa.h
0,0 → 1,37
/*
* Copyright (C) 2006-2006 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __VESA_H__
#define __VESA_H__
int vesa_present(void);
void vesa_init(void);
#endif

/tags/0.2.0/kernel/arch/amd64/include/drivers/i8259.h
0,0 → 1,0
link ../../../ia32/include/drivers/i8259.h
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/include/drivers/ega.h
0,0 → 1,0
link ../../../ia32/include/drivers/ega.h
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/include/drivers/i8042.h
0,0 → 1,0
link ../../../ia32/include/drivers/i8042.h
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/include/pm.h
0,0 → 1,189
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_PM_H__
#define __amd64_PM_H__
#ifndef __ASM__
# include <arch/types.h>
# include <typedefs.h>
# include <arch/context.h>
#endif
#define IDT_ITEMS 64
#define GDT_ITEMS 8
#define NULL_DES 0
/* Warning: Do not reorder next items, unless you look into syscall.c!!! */
#define KTEXT_DES 1
#define KDATA_DES 2
#define UDATA_DES 3
#define UTEXT_DES 4
#define KTEXT32_DES 5
/* EndOfWarning */
#define TSS_DES 6
#ifdef CONFIG_FB
#define VESA_INIT_DES 8
#define VESA_INIT_SEGMENT 0x8000
#undef GDT_ITEMS
#define GDT_ITEMS 9
#endif /*CONFIG_FB*/
#define gdtselector(des) ((des)<<3)
#define idtselector(des) ((des)<<4)
#define PL_KERNEL 0
#define PL_USER 3
#define AR_PRESENT (1<<7)
#define AR_DATA (2<<3)
#define AR_CODE (3<<3)
#define AR_WRITABLE (1<<1)
#define AR_READABLE (1<<1)
#define AR_TSS (0x9)
#define AR_INTERRUPT (0xe)
#define AR_TRAP (0xf)
#define DPL_KERNEL (PL_KERNEL<<5)
#define DPL_USER (PL_USER<<5)
#define TSS_BASIC_SIZE 104
#define TSS_IOMAP_SIZE (16*1024+1) /* 16K for bitmap + 1 terminating byte for convenience */
#define IO_PORTS (64*1024)
#ifndef __ASM__
struct descriptor {
unsigned limit_0_15: 16;
unsigned base_0_15: 16;
unsigned base_16_23: 8;
unsigned access: 8;
unsigned limit_16_19: 4;
unsigned available: 1;
unsigned longmode: 1;
unsigned special: 1;
unsigned granularity : 1;
unsigned base_24_31: 8;
} __attribute__ ((packed));
typedef struct descriptor descriptor_t;
struct tss_descriptor {
unsigned limit_0_15: 16;
unsigned base_0_15: 16;
unsigned base_16_23: 8;
unsigned type: 4;
unsigned : 1;
unsigned dpl : 2;
unsigned present : 1;
unsigned limit_16_19: 4;
unsigned available: 1;
unsigned : 2;
unsigned granularity : 1;
unsigned base_24_31: 8;
unsigned base_32_63 : 32;
unsigned : 32;
} __attribute__ ((packed));
typedef struct tss_descriptor tss_descriptor_t;
struct idescriptor {
unsigned offset_0_15: 16;
unsigned selector: 16;
unsigned ist:3;
unsigned unused: 5;
unsigned type: 5;
unsigned dpl: 2;
unsigned present : 1;
unsigned offset_16_31: 16;
unsigned offset_32_63: 32;
unsigned : 32;
} __attribute__ ((packed));
typedef struct idescriptor idescriptor_t;
struct ptr_16_64 {
__u16 limit;
__u64 base;
} __attribute__ ((packed));
typedef struct ptr_16_64 ptr_16_64_t;
struct ptr_16_32 {
__u16 limit;
__u32 base;
} __attribute__ ((packed));
typedef struct ptr_16_32 ptr_16_32_t;
struct tss {
__u32 reserve1;
__u64 rsp0;
__u64 rsp1;
__u64 rsp2;
__u64 reserve2;
__u64 ist1;
__u64 ist2;
__u64 ist3;
__u64 ist4;
__u64 ist5;
__u64 ist6;
__u64 ist7;
__u64 reserve3;
__u16 reserve4;
__u16 iomap_base;
__u8 iomap[TSS_IOMAP_SIZE];
} __attribute__ ((packed));
typedef struct tss tss_t;
extern tss_t *tss_p;
extern descriptor_t gdt[];
extern idescriptor_t idt[];
extern ptr_16_64_t gdtr;
extern ptr_16_32_t bootstrap_gdtr;
extern ptr_16_32_t protected_ap_gdtr;
extern void pm_init(void);
extern void gdt_tss_setbase(descriptor_t *d, __address base);
extern void gdt_tss_setlimit(descriptor_t *d, __u32 limit);
extern void idt_init(void);
extern void idt_setoffset(idescriptor_t *d, __address offset);
extern void tss_initialize(tss_t *t);
#endif /* __ASM__ */
#endif

/tags/0.2.0/kernel/arch/amd64/include/ddi/ddi.h
0,0 → 1,39
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file ddi.h
* @brief amd64 specific DDI declarations and macros.
*/
#ifndef __amd64_DDI_H__
#define __amd64_DDI_H__
extern void io_perm_bitmap_install(void);
#endif

/tags/0.2.0/kernel/arch/amd64/include/proc/task.h
0,0 → 1,41
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_TASK_H__
#define __amd64_TASK_H__
#include <typedefs.h>
#include <arch/types.h>
#include <adt/bitmap.h>
typedef struct {
count_t iomapver; /**< I/O Permission bitmap Generation counter. */
bitmap_t iomap; /**< I/O Permission bitmap. */
} task_arch_t;
#endif

/tags/0.2.0/kernel/arch/amd64/include/proc/thread.h
0,0 → 1,38
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_THREAD_H__
#define __amd64_THREAD_H__
#include <arch/types.h>
typedef struct {
__native tls;
} thread_arch_t;
#endif

/tags/0.2.0/kernel/arch/amd64/include/cpu.h
0,0 → 1,78
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_CPU_H__
#define __amd64_CPU_H__
#define RFLAGS_IF (1 << 9)
#define RFLAGS_RF (1 << 16)
#define EFER_MSR_NUM 0xc0000080
#define AMD_SCE_FLAG 0
#define AMD_LME_FLAG 8
#define AMD_LMA_FLAG 10
#define AMD_FFXSR_FLAG 14
#define AMD_NXE_FLAG 11
/* MSR registers */
#define AMD_MSR_STAR 0xc0000081
#define AMD_MSR_LSTAR 0xc0000082
#define AMD_MSR_SFMASK 0xc0000084
#define AMD_MSR_FS 0xc0000100
#define AMD_MSR_GS 0xc0000101
#ifndef __ASM__
#include <typedefs.h>
#include <arch/pm.h>
struct cpu_arch {
int vendor;
int family;
int model;
int stepping;
struct tss *tss;
count_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */
};
struct star_msr {
};
struct lstar_msr {
};
extern void set_efer_flag(int flag);
extern __u64 read_efer_flag(void);
void cpu_setup_fpu(void);
#endif /* __ASM__ */
#endif

/tags/0.2.0/kernel/arch/amd64/include/asm.h
0,0 → 1,275
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_ASM_H__
#define __amd64_ASM_H__
#include <arch/pm.h>
#include <arch/types.h>
#include <config.h>
extern void asm_delay_loop(__u32 t);
extern void asm_fake_loop(__u32 t);
/** Return base address of current stack.
*
* Return the base address of the current stack.
* The stack is assumed to be STACK_SIZE bytes long.
* The stack must start on page boundary.
*/
static inline __address get_stack_base(void)
{
__address v;
__asm__ volatile ("andq %%rsp, %0\n" : "=r" (v) : "0" (~((__u64)STACK_SIZE-1)));
return v;
}
static inline void cpu_sleep(void) { __asm__ volatile ("hlt\n"); };
static inline void cpu_halt(void) { __asm__ volatile ("hlt\n"); };
/** Byte from port
*
* Get byte from port
*
* @param port Port to read from
* @return Value read
*/
static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
/** Byte to port
*
* Output byte to port
*
* @param port Port to write to
* @param val Value to write
*/
static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
/** Swap Hidden part of GS register with visible one */
static inline void swapgs(void) { __asm__ volatile("swapgs"); }
/** Enable interrupts.
*
* Enable interrupts and return previous
* value of EFLAGS.
*
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_enable(void) {
ipl_t v;
__asm__ volatile (
"pushfq\n"
"popq %0\n"
"sti\n"
: "=r" (v)
);
return v;
}
/** Disable interrupts.
*
* Disable interrupts and return previous
* value of EFLAGS.
*
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_disable(void) {
ipl_t v;
__asm__ volatile (
"pushfq\n"
"popq %0\n"
"cli\n"
: "=r" (v)
);
return v;
}
/** Restore interrupt priority level.
*
* Restore EFLAGS.
*
* @param ipl Saved interrupt priority level.
*/
static inline void interrupts_restore(ipl_t ipl) {
__asm__ volatile (
"pushq %0\n"
"popfq\n"
: : "r" (ipl)
);
}
/** Return interrupt priority level.
*
* Return EFLAFS.
*
* @return Current interrupt priority level.
*/
static inline ipl_t interrupts_read(void) {
ipl_t v;
__asm__ volatile (
"pushfq\n"
"popq %0\n"
: "=r" (v)
);
return v;
}
/** Write to MSR */
static inline void write_msr(__u32 msr, __u64 value)
{
__asm__ volatile (
"wrmsr;" : : "c" (msr),
"a" ((__u32)(value)),
"d" ((__u32)(value >> 32))
);
}
static inline __native read_msr(__u32 msr)
{
__u32 ax, dx;
__asm__ volatile (
"rdmsr;" : "=a"(ax), "=d"(dx) : "c" (msr)
);
return ((__u64)dx << 32) | ax;
}
/** Enable local APIC
*
* Enable local APIC in MSR.
*/
static inline void enable_l_apic_in_msr()
{
__asm__ volatile (
"movl $0x1b, %%ecx\n"
"rdmsr\n"
"orl $(1<<11),%%eax\n"
"orl $(0xfee00000),%%eax\n"
"wrmsr\n"
:
:
:"%eax","%ecx","%edx"
);
}
static inline __address * get_ip()
{
__address *ip;
__asm__ volatile (
"mov %%rip, %0"
: "=r" (ip)
);
return ip;
}
/** Invalidate TLB Entry.
*
* @param addr Address on a page whose TLB entry is to be invalidated.
*/
static inline void invlpg(__address addr)
{
__asm__ volatile ("invlpg %0\n" :: "m" (*((__native *)addr)));
}
/** Load GDTR register from memory.
*
* @param gdtr_reg Address of memory from where to load GDTR.
*/
static inline void gdtr_load(struct ptr_16_64 *gdtr_reg)
{
__asm__ volatile ("lgdtq %0\n" : : "m" (*gdtr_reg));
}
/** Store GDTR register to memory.
*
* @param gdtr_reg Address of memory to where to load GDTR.
*/
static inline void gdtr_store(struct ptr_16_64 *gdtr_reg)
{
__asm__ volatile ("sgdtq %0\n" : : "m" (*gdtr_reg));
}
/** Load IDTR register from memory.
*
* @param idtr_reg Address of memory from where to load IDTR.
*/
static inline void idtr_load(struct ptr_16_64 *idtr_reg)
{
__asm__ volatile ("lidtq %0\n" : : "m" (*idtr_reg));
}
/** Load TR from descriptor table.
*
* @param sel Selector specifying descriptor of TSS segment.
*/
static inline void tr_load(__u16 sel)
{
__asm__ volatile ("ltr %0" : : "r" (sel));
}
#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
{ \
__native res; \
__asm__ volatile ("movq %%" #reg ", %0" : "=r" (res) ); \
return res; \
}
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
{ \
__asm__ volatile ("movq %0, %%" #reg : : "r" (regn)); \
}
GEN_READ_REG(cr0);
GEN_READ_REG(cr2);
GEN_READ_REG(cr3);
GEN_WRITE_REG(cr3);
GEN_READ_REG(dr0);
GEN_READ_REG(dr1);
GEN_READ_REG(dr2);
GEN_READ_REG(dr3);
GEN_READ_REG(dr6);
GEN_READ_REG(dr7);
GEN_WRITE_REG(dr0);
GEN_WRITE_REG(dr1);
GEN_WRITE_REG(dr2);
GEN_WRITE_REG(dr3);
GEN_WRITE_REG(dr6);
GEN_WRITE_REG(dr7);
extern size_t interrupt_handler_size;
extern void interrupt_handlers(void);
#endif

/tags/0.2.0/kernel/arch/amd64/include/atomic.h
0,0 → 1,122
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_ATOMIC_H__
#define __amd64_ATOMIC_H__
#include <arch/types.h>
#include <arch/barrier.h>
#include <preemption.h>
#include <typedefs.h>
static inline void atomic_inc(atomic_t *val) {
#ifdef CONFIG_SMP
__asm__ volatile ("lock incq %0\n" : "=m" (val->count));
#else
__asm__ volatile ("incq %0\n" : "=m" (val->count));
#endif /* CONFIG_SMP */
}
static inline void atomic_dec(atomic_t *val) {
#ifdef CONFIG_SMP
__asm__ volatile ("lock decq %0\n" : "=m" (val->count));
#else
__asm__ volatile ("decq %0\n" : "=m" (val->count));
#endif /* CONFIG_SMP */
}
static inline long atomic_postinc(atomic_t *val)
{
long r;
__asm__ volatile (
"movq $1, %0\n"
"lock xaddq %0, %1\n"
: "=r" (r), "=m" (val->count)
);
return r;
}
static inline long atomic_postdec(atomic_t *val)
{
long r;
__asm__ volatile (
"movq $-1, %0\n"
"lock xaddq %0, %1\n"
: "=r" (r), "=m" (val->count)
);
return r;
}
#define atomic_preinc(val) (atomic_postinc(val)+1)
#define atomic_predec(val) (atomic_postdec(val)-1)
static inline __u64 test_and_set(atomic_t *val) {
__u64 v;
__asm__ volatile (
"movq $1, %0\n"
"xchgq %0, %1\n"
: "=r" (v),"=m" (val->count)
);
return v;
}
/** amd64 specific fast spinlock */
static inline void atomic_lock_arch(atomic_t *val)
{
__u64 tmp;
preemption_disable();
__asm__ volatile (
"0:;"
#ifdef CONFIG_HT
"pause;"
#endif
"mov %0, %1;"
"testq %1, %1;"
"jnz 0b;" /* Lightweight looping on locked spinlock */
"incq %1;" /* now use the atomic operation */
"xchgq %0, %1;"
"testq %1, %1;"
"jnz 0b;"
: "=m"(val->count),"=r"(tmp)
);
/*
* Prevent critical section code from bleeding out this way up.
*/
CS_ENTER_BARRIER();
}
#endif

/tags/0.2.0/kernel/arch/amd64/include/syscall.h
0,0 → 1,36
/*
* Copyright (C) 2006 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_SYSCALL_H__
#define __amd64_SYSCALL_H__
#include <arch/types.h>
extern void syscall_setup_cpu(void);
#endif

/tags/0.2.0/kernel/arch/amd64/include/debugger.h
0,0 → 1,48
/*
* Copyright (C) 2006 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_DEBUGGER_H__
#define __amd64_DEBUGGER_H__
#include <arch/types.h>
#define BKPOINTS_MAX 4
/* Flags that are passed to breakpoint_add function */
#define BKPOINT_INSTR 0x1
#define BKPOINT_WRITE 0x2
#define BKPOINT_READ_WRITE 0x4
#define BKPOINT_CHECK_ZERO 0x8
extern void debugger_init(void);
extern int breakpoint_add(void * where, int flags, int curidx);
extern void breakpoint_del(int slot);
#endif

/tags/0.2.0/kernel/arch/amd64/include/context_offset.h
0,0 → 1,10
/* This file is automatically generated by gencontext.c. */
#define OFFSET_SP 0x0
#define OFFSET_PC 0x8
#define OFFSET_RBX 0x10
#define OFFSET_RBP 0x18
#define OFFSET_R12 0x20
#define OFFSET_R13 0x28
#define OFFSET_R14 0x30
#define OFFSET_R15 0x38
#define OFFSET_IPL 0x40

/tags/0.2.0/kernel/arch/amd64/include/context.h
0,0 → 1,61
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_CONTEXT_H__
#define __amd64_CONTEXT_H__
#ifndef __amd64_TYPES_H__
# include <arch/types.h>
#endif
/* According to ABI the stack MUST be aligned on
* 16-byte boundary. If it is not, the va_arg calling will
* panic sooner or later
*/
#define SP_DELTA 16
/* We include only registers that must be preserved
* during function call
*/
struct context {
__address sp;
__address pc;
__u64 rbx;
__u64 rbp;
__u64 r12;
__u64 r13;
__u64 r14;
__u64 r15;
ipl_t ipl;
} __attribute__ ((packed));
#endif

/tags/0.2.0/kernel/arch/amd64/include/types.h
0,0 → 1,55
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_TYPES_H__
#define __amd64_TYPES_H__
#define NULL 0
typedef signed char __s8;
typedef signed short __s16;
typedef signed int __s32;
typedef signed long long __s64;
typedef unsigned char __u8;
typedef unsigned short __u16;
typedef unsigned int __u32;
typedef unsigned long long __u64;
typedef __u64 __address;
typedef __u64 pfn_t;
/* Flags of processor (return value of interrupts_disable()) */
typedef __u64 ipl_t;
typedef __u64 __native;
typedef __s64 __snative;
typedef struct page_specifier pte_t;
#endif

/tags/0.2.0/kernel/arch/amd64/include/elf.h
0,0 → 1,36
/*
* Copyright (C) 2006 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_ELF_H__
#define __amd64_ELF_H__
#define ELF_MACHINE EM_X86_64
#define ELF_DATA_ENCODING ELFDATA2LSB
#define ELF_CLASS ELFCLASS64
#endif

/tags/0.2.0/kernel/arch/amd64/include/cpuid.h
0,0 → 1,58
/*
* Copyright (C) 2001-2004 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_CPUID_H__
#define __amd64_CPUID_H__
#define AMD_CPUID_EXTENDED 0x80000001
#define AMD_EXT_NOEXECUTE 20
#define INTEL_CPUID_STANDARD 0x1
#define INTEL_SSE2 26
#define INTEL_FXSAVE 24
#ifndef __ASM__
#include <arch/types.h>
struct cpu_info {
__u32 cpuid_eax;
__u32 cpuid_ebx;
__u32 cpuid_ecx;
__u32 cpuid_edx;
} __attribute__ ((packed));
extern int has_cpuid(void);
extern void cpuid(__u32 cmd, cpu_info_t *info);
extern __u64 rdtsc(void);
#endif /* __ASM__ */
#endif

/tags/0.2.0/kernel/arch/amd64/include/boot/boot.h
0,0 → 1,41
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_BOOT_H__
#define __amd64_BOOT_H__
#define BOOT_OFFSET 0x108000
#define AP_BOOT_OFFSET 0x8000
#define BOOT_STACK_SIZE 0x400
#define MULTIBOOT_HEADER_MAGIC 0x1BADB002
#define MULTIBOOT_HEADER_FLAGS 0x00010003
#define MULTIBOOT_LOADER_MAGIC 0x2BADB002
#endif

/tags/0.2.0/kernel/arch/amd64/include/boot/memmap.h
0,0 → 1,0
link ../../../ia32/include/boot/memmap.h
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/include/debug.h
0,0 → 1,0
link ../../ia32/include/debug.h
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/include/fpu_context.h
0,0 → 1,0
link ../../ia32/include/fpu_context.h
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/include/bios
0,0 → 1,0
link ../../ia32/include/bios
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/include/smp
0,0 → 1,0
link ../../ia32/include/smp
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/include/barrier.h
0,0 → 1,0
link ../../ia32/include/barrier.h
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/amd64/include/memstr.h
0,0 → 1,136
/*
* Copyright (C) 2005 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_MEMSTR_H__
#define __amd64_MEMSTR_H__
/** Copy memory
*
* Copy a given number of bytes (3rd argument)
* from the memory location defined by 2nd argument
* to the memory location defined by 1st argument.
* The memory areas cannot overlap.
*
* @param dst Destination
* @param src Source
* @param cnt Number of bytes
* @return Destination
*/
static inline void * memcpy(void * dst, const void * src, size_t cnt)
{
__native d0, d1, d2;
__asm__ __volatile__(
"rep movsq\n\t"
"movq %4, %%rcx\n\t"
"andq $7, %%rcx\n\t"
"jz 1f\n\t"
"rep movsb\n\t"
"1:\n"
: "=&c" (d0), "=&D" (d1), "=&S" (d2)
: "0" ((__native)(cnt / 8)), "g" ((__native)cnt), "1" ((__native) dst), "2" ((__native) src)
: "memory");
return dst;
}
/** Compare memory regions for equality
*
* Compare a given number of bytes (3rd argument)
* at memory locations defined by 1st and 2nd argument
* for equality. If bytes are equal function returns 0.
*
* @param src Region 1
* @param dst Region 2
* @param cnt Number of bytes
* @return Zero if bytes are equal, non-zero otherwise
*/
static inline int memcmp(const void * src, const void * dst, size_t cnt)
{
__native d0, d1, d2;
__native ret;
__asm__ (
"repe cmpsb\n\t"
"je 1f\n\t"
"movq %3, %0\n\t"
"addq $1, %0\n\t"
"1:\n"
: "=a" (ret), "=%S" (d0), "=&D" (d1), "=&c" (d2)
: "0" (0), "1" (src), "2" (dst), "3" ((__native)cnt)
);
return ret;
}
/** Fill memory with words
* Fill a given number of words (2nd argument)
* at memory defined by 1st argument with the
* word value defined by 3rd argument.
*
* @param dst Destination
* @param cnt Number of words
* @param x Value to fill
*/
static inline void memsetw(__address dst, size_t cnt, __u16 x)
{
__native d0, d1;
__asm__ __volatile__ (
"rep stosw\n\t"
: "=&D" (d0), "=&c" (d1), "=a" (x)
: "0" (dst), "1" ((__native)cnt), "2" (x)
: "memory"
);
}
/** Fill memory with bytes
* Fill a given number of bytes (2nd argument)
* at memory defined by 1st argument with the
* word value defined by 3rd argument.
*
* @param dst Destination
* @param cnt Number of bytes
* @param x Value to fill
*/
static inline void memsetb(__address dst, size_t cnt, __u8 x)
{
__native d0, d1;
__asm__ __volatile__ (
"rep stosb\n\t"
: "=&D" (d0), "=&c" (d1), "=a" (x)
: "0" (dst), "1" ((__native)cnt), "2" (x)
: "memory"
);
}
#endif

/tags/0.2.0/kernel/arch/amd64/include/byteorder.h
0,0 → 1,36
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_BYTEORDER_H__
#define __amd64_BYTEORDER_H__
/* AMD64 is little-endian */
#define __native_le2host(n) (n)
#define __u64_le2host(n) (n)
#endif

/tags/0.2.0/kernel/arch/amd64/include/arch.h
0,0 → 1,32
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_ARCH_H__
#define __amd64_ARCH_H__
#endif

/tags/0.2.0/kernel/arch/amd64/include/faddr.h
0,0 → 1,36
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_FADDR_H__
#define __amd64_FADDR_H__
#include <arch/types.h>
#define FADDR(fptr) ((__address) (fptr))
#endif

/tags/0.2.0/kernel/arch/amd64/include/arg.h
0,0 → 1,34
/*
* Copyright (C) 2005 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __amd64_ARG_H__
#define __amd64_ARG_H__
#include <stdarg.h>
#endif

/tags/0.2.0/kernel/arch/amd64/Makefile.inc
0,0 → 1,121
#
# Copyright (C) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
## Toolchain configuration
#
BFD_NAME = elf64-x86-64
BFD_ARCH = i386:x86-64
BFD = binary
TARGET = amd64-linux-gnu
TOOLCHAIN_DIR = /usr/local/amd64/bin
## Make some default assumptions
#
ifndef CPU
CPU = opteron
endif
CFLAGS += -fno-unwind-tables -m64 -mcmodel=kernel -mno-red-zone
DEFS += -D_CPU=${CPU} -D__64_BITS__
## Accepted CPUs
#
ifeq ($(CPU),opteron)
CFLAGS += -march=opteron
DEFS += -DFENCES=p4
endif
## Own configuration directives
#
CONFIG_ACPI = y
## Compile with hierarchical page tables support.
#
CONFIG_PAGE_PT = y
DEFS += -DCONFIG_PAGE_PT
## Compile with i8042 support.
#
CONFIG_I8042 = y
## Accepted configuration directives
#
ifeq ($(CONFIG_SMP),y)
DEFS += -DCONFIG_SMP
endif
ifeq ($(CONFIG_HT),y)
DEFS += -DCONFIG_HT
endif
ifeq ($(CONFIG_SIMICS_FIX),y)
DEFS += -DCONFIG_SIMICS_FIX
endif
ARCH_SOURCES = \
arch/$(ARCH)/src/fpu_context.c \
arch/$(ARCH)/src/boot/boot.S \
arch/$(ARCH)/src/pm.c \
arch/$(ARCH)/src/context.S \
arch/$(ARCH)/src/ddi/ddi.c \
arch/$(ARCH)/src/drivers/ega.c \
arch/$(ARCH)/src/drivers/vesa.c \
arch/$(ARCH)/src/drivers/i8254.c \
arch/$(ARCH)/src/drivers/i8259.c \
arch/$(ARCH)/src/delay.S \
arch/$(ARCH)/src/amd64.c \
arch/$(ARCH)/src/bios/bios.c \
arch/$(ARCH)/src/interrupt.c \
arch/$(ARCH)/src/mm/as.c \
arch/$(ARCH)/src/mm/frame.c \
arch/$(ARCH)/src/mm/page.c \
arch/$(ARCH)/src/mm/tlb.c \
arch/$(ARCH)/src/asm_utils.S \
arch/$(ARCH)/src/mm/memory_init.c \
arch/$(ARCH)/src/cpu/cpu.c \
arch/$(ARCH)/src/proc/scheduler.c \
arch/$(ARCH)/src/proc/task.c \
arch/$(ARCH)/src/proc/thread.c \
arch/$(ARCH)/src/userspace.c \
arch/$(ARCH)/src/syscall.c \
arch/$(ARCH)/src/debugger.c
ifeq ($(CONFIG_SMP),y)
ARCH_SOURCES += \
arch/$(ARCH)/src/smp/ap.S \
arch/$(ARCH)/src/smp/apic.c \
arch/$(ARCH)/src/smp/ipi.c \
arch/$(ARCH)/src/smp/mps.c \
arch/$(ARCH)/src/smp/smp.c
endif

/tags/0.2.0/kernel/arch/amd64/_link.ld.in
0,0 → 1,64
/** AMD64 linker script
*
* umapped section:
* kernel text
* kernel data
* mapped section:
* kernel text
* kernel data
*/
#define __ASM__
#include <arch/boot/boot.h>
#include <arch/mm/page.h>
SECTIONS {
.unmapped BOOT_OFFSET: AT (0) {
unmapped_ktext_start = .;
*(K_TEXT_START);
unmapped_ktext_end = .;
unmapped_kdata_start = .;
*(K_DATA_START);
unmapped_kdata_end = .;
}
.mapped (PA2KA(BOOT_OFFSET)+SIZEOF(.unmapped)) : AT (SIZEOF(.unmapped)) {
ktext_start = .;
*(.text);
ktext_end = .;
kdata_start = .;
*(.data); /* initialized data */
*(.rodata*); /* string literals */
hardcoded_load_address = .;
QUAD(PA2KA(BOOT_OFFSET));
hardcoded_ktext_size = .;
QUAD(ktext_end - ktext_start + (unmapped_ktext_end - unmapped_ktext_start));
hardcoded_kdata_size = .;
QUAD(kdata_end - kdata_start + (unmapped_kdata_end - unmapped_kdata_start));
hardcoded_unmapped_ktext_size = .;
QUAD(unmapped_ktext_end - unmapped_ktext_start);
hardcoded_unmapped_kdata_size = .;
QUAD(unmapped_kdata_end - unmapped_kdata_start);
*(COMMON); /* global variables */
*(.eh_frame);
symbol_table = .;
*(symtab.*); /* Symbol table, must be LAST symbol!*/
*(.bss); /* uninitialized static variables */
kdata_end = .;
}
#ifdef CONFIG_SMP
_hardcoded_unmapped_size = (unmapped_ktext_end - unmapped_ktext_start) + (unmapped_kdata_end - unmapped_kdata_start);
ap_boot = unmapped_ap_boot - BOOT_OFFSET + AP_BOOT_OFFSET;
ap_gdtr = unmapped_ap_gdtr - BOOT_OFFSET + AP_BOOT_OFFSET;
protected_ap_gdtr = PA2KA(ap_gdtr);
#endif /* CONFIG_SMP */
}

/tags/0.2.0/kernel/arch/ia32/src/boot/boot.S
0,0 → 1,431
#
# Copyright (C) 2001-2004 Jakub Jermar
# Copyright (C) 2005-2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/boot/boot.h>
#include <arch/boot/memmap.h>
#include <arch/mm/page.h>
#include <arch/pm.h>
#define START_STACK (BOOT_OFFSET - BOOT_STACK_SIZE)
.section K_TEXT_START, "ax"
KTEXT=8
KDATA=16
.code32
.align 4
.global multiboot_image_start
multiboot_header:
.long MULTIBOOT_HEADER_MAGIC
.long MULTIBOOT_HEADER_FLAGS
.long -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS) # checksum
.long multiboot_header
.long unmapped_ktext_start
.long 0
.long 0
.long multiboot_image_start
multiboot_image_start:
movl $START_STACK, %esp # initialize stack pointer
lgdt KA2PA(bootstrap_gdtr) # initialize Global Descriptor Table register
movw $KDATA, %cx
movw %cx, %es
movw %cx, %fs
movw %cx, %gs
movw %cx, %ds # kernel data + stack
movw %cx, %ss
jmpl $KTEXT, $multiboot_meeting_point
multiboot_meeting_point:
pushl %ebx # save parameters from GRUB
pushl %eax
#ifdef CONFIG_FB
mov $vesa_init, %esi
mov $VESA_INIT_SEGMENT << 4, %edi
mov $e_vesa_init - vesa_init, %ecx
cld
rep movsb
mov $VESA_INIT_SEGMENT << 4, %edi
jmpl %edi
vesa_meeting_point:
mov %esi, KA2PA(vesa_ph_addr)
mov %di, KA2PA(vesa_height)
shr $16, %edi
mov %di, KA2PA(vesa_width)
mov %bx, KA2PA(vesa_scanline)
shr $16, %ebx
mov %bx, KA2PA(vesa_bpp)
#endif
call map_kernel # map kernel and turn paging on
popl %eax
popl %ebx
cmpl $MULTIBOOT_LOADER_MAGIC, %eax # compare GRUB signature
je valid_boot
xorl %ecx, %ecx # no memory size or map available
movl %ecx, e801memorysize
movl %ecx, e820counter
jmp invalid_boot
valid_boot:
movl (%ebx), %eax # ebx = physical address of struct multiboot_info
bt $0, %eax # mbi->flags[0] (mem_lower, mem_upper valid)
jc mem_valid
xorl %ecx, %ecx
jmp mem_invalid
mem_valid:
movl 4(%ebx), %ecx # mbi->mem_lower
addl 8(%ebx), %ecx # mbi->mem_upper
mem_invalid:
movl %ecx, e801memorysize
bt $3, %eax # mbi->flags[3] (mods_count, mods_addr valid)
jc mods_valid
xorl %ecx, %ecx
movl %ecx, init
jmp mods_end
mods_valid:
movl 20(%ebx), %ecx # mbi->mods_count
movl %ecx, init
cmpl $0, %ecx
je mods_end
movl 24(%ebx), %esi # mbi->mods_addr
movl $init, %edi
mods_loop:
movl 0(%esi), %edx # mods->mod_start
addl $0x80000000, %edx
movl %edx, 4(%edi)
movl 4(%esi), %edx
subl 0(%esi), %edx # mods->mod_end - mods->mod_start
movl %edx, 8(%edi)
addl $16, %esi
addl $8 , %edi
loop mods_loop
mods_end:
bt $6, %eax # mbi->flags[6] (mmap_length, mmap_addr valid)
jc mmap_valid
xorl %edx, %edx
jmp mmap_invalid
mmap_valid:
movl 44(%ebx), %ecx # mbi->mmap_length
movl 48(%ebx), %esi # mbi->mmap_addr
movl $e820table, %edi
xorl %edx, %edx
mmap_loop:
cmpl $0, %ecx
jle mmap_end
movl 4(%esi), %eax # mmap->base_addr_low
movl %eax, (%edi)
movl 8(%esi), %eax # mmap->base_addr_high
movl %eax, 4(%edi)
movl 12(%esi), %eax # mmap->length_low
movl %eax, 8(%edi)
movl 16(%esi), %eax # mmap->length_high
movl %eax, 12(%edi)
movl 20(%esi), %eax # mmap->type
movl %eax, 16(%edi)
movl (%esi), %eax # mmap->size
addl $0x4, %eax
addl %eax, %esi
subl %eax, %ecx
addl $MEMMAP_E820_RECORD_SIZE, %edi
incl %edx
jmp mmap_loop
mmap_end:
mmap_invalid:
movl %edx, e820counter
invalid_boot:
#ifdef CONFIG_SMP
# copy AP bootstrap routines below 1 MB
movl $BOOT_OFFSET, %esi
movl $AP_BOOT_OFFSET, %edi
movl $_hardcoded_unmapped_size, %ecx
cld
rep movsb
#endif
call main_bsp # never returns
cli
hlt
.global map_kernel
map_kernel:
#
# Here we setup mapping for both the unmapped and mapped sections of the kernel.
# For simplicity, we map the entire 4G space.
#
movl %cr4, %ecx
orl $(1<<4), %ecx
movl %ecx, %cr4 # turn PSE on
movl $(page_directory+0), %esi
movl $(page_directory+2048), %edi
xorl %ecx, %ecx
xorl %ebx, %ebx
0:
movl $((1<<7)|(1<<0)), %eax
orl %ebx, %eax
movl %eax, (%esi,%ecx,4) # mapping 0x00000000+%ecx*4M => 0x00000000+%ecx*4M
movl %eax, (%edi,%ecx,4) # mapping 0x80000000+%ecx*4M => 0x00000000+%ecx*4M
addl $(4*1024*1024), %ebx
incl %ecx
cmpl $512, %ecx
jl 0b
movl %esi, %cr3
# turn paging on
movl %cr0, %ebx
orl $(1<<31), %ebx
movl %ebx, %cr0
ret
#ifdef CONFIG_FB
vesa_init:
jmp $selector(VESA_INIT_DES), $vesa_init_real - vesa_init
.code16
vesa_init_real:
mov %cr0, %eax
and $~1, %eax
mov %eax, %cr0
jmp $VESA_INIT_SEGMENT, $vesa_init_real2 - vesa_init
vesa_init_real2:
mov $VESA_INIT_SEGMENT, %bx
mov %bx, %es
mov %bx, %fs
mov %bx, %gs
mov %bx, %ds
mov %bx, %ss
movl %esp, %eax
movl $0x0000fffc, %esp
movl $0x0000fffc, %ebp
pushl %eax
#define VESA_INFO_SIZE 1024
#define VESA_MODE_LIST_PTR_OFFSET 14
#define VESA_MODE_WIDTH_OFFSET 18
#define VESA_MODE_HEIGHT_OFFSET 20
#define VESA_MODE_BPP_OFFSET 25
#define VESA_MODE_SCANLINE_OFFSET 16
#define VESA_MODE_PHADDR_OFFSET 40
#define VESA_END_OF_MODES 0xffff
#define VESA_OK 0x4f
#define VESA_GET_INFO 0x4f00
#define VESA_GET_MODE_INFO 0x4f01
#define VESA_SET_MODE 0x4f02
#define CONFIG_VESA_BPP_a 255
#if CONFIG_VESA_BPP == 24
#undef CONFIG_VESA_BPP_a
#define CONFIG_VESA_BPP_a 32
#endif
mov $VESA_GET_INFO, %ax
mov $e_vesa_init - vesa_init, %di
push %di
int $0x10
pop %di
cmp $VESA_OK, %al
jnz 0f
mov 2 + VESA_MODE_LIST_PTR_OFFSET(%di), %si
mov %si, %gs
mov VESA_MODE_LIST_PTR_OFFSET(%di), %si
add $VESA_INFO_SIZE, %di
1:# Try next mode
mov %gs:(%si), %cx
cmp $VESA_END_OF_MODES, %cx
jz 0f
inc %si
inc %si
push %cx
push %di
push %si
mov $VESA_GET_MODE_INFO, %ax
int $0x10
pop %si
pop %di
pop %cx
cmp $VESA_OK, %al
jnz 0f
mov $CONFIG_VESA_WIDTH, %ax
cmp VESA_MODE_WIDTH_OFFSET(%di), %ax
jnz 1b
mov $CONFIG_VESA_HEIGHT,%ax
cmp VESA_MODE_HEIGHT_OFFSET(%di), %ax
jnz 1b
mov $CONFIG_VESA_BPP, %al
cmp VESA_MODE_BPP_OFFSET(%di), %al
jz 2f
mov $CONFIG_VESA_BPP_a, %al
cmp VESA_MODE_BPP_OFFSET(%di), %al
jnz 1b
2:
mov %cx, %bx
or $0xc000, %bx
push %di
mov $VESA_SET_MODE, %ax
int $0x10
pop %di
cmp $VESA_OK, %al
jnz 0f
mov VESA_MODE_PHADDR_OFFSET(%di), %esi
mov VESA_MODE_WIDTH_OFFSET(%di), %ax
shl $16, %eax
mov VESA_MODE_HEIGHT_OFFSET(%di), %ax
mov VESA_MODE_BPP_OFFSET(%di), %bl
xor %bh, %bh
shl $16, %ebx
mov VESA_MODE_SCANLINE_OFFSET(%di), %bx
mov %eax, %edi
8:
mov %cr0, %eax
or $1, %eax
mov %eax, %cr0
jmp 9f
9:
ljmpl $KTEXT, $(vesa_init_protect - vesa_init + VESA_INIT_SEGMENT << 4)
0:# No prefered mode found
mov $0x111, %cx
push %di
push %cx
mov $VESA_GET_MODE_INFO, %ax
int $0x10
pop %cx
pop %di
cmp $VESA_OK, %al
jnz 1f
jz 2b # Force relative jump
1:
mov $0x0003, %ax
int $0x10
mov $0xffffffff, %edi # EGA text mode used, because of problems with VESA
xor %ax, %ax
jz 8b # Force relative jump
.code32
vesa_init_protect:
popl %esp
movw $KDATA, %cx
movw %cx, %es
movw %cx, %fs
movw %cx, %gs
movw %cx, %ds # kernel data + stack
movw %cx, %ss
jmpl $KTEXT, $vesa_meeting_point
.align 4
e_vesa_init:
#endif
.section K_DATA_START, "aw", @progbits
.align 4096
page_directory:
.space 4096, 0

/tags/0.2.0/kernel/arch/ia32/src/mm/page.c
0,0 → 1,112
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/page.h>
#include <genarch/mm/page_pt.h>
#include <arch/mm/frame.h>
#include <mm/frame.h>
#include <mm/page.h>
#include <mm/as.h>
#include <arch/types.h>
#include <align.h>
#include <config.h>
#include <func.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <debug.h>
#include <memstr.h>
#include <print.h>
#include <interrupt.h>
void page_arch_init(void)
{
__address cur;
int flags;
if (config.cpu_active == 1) {
page_mapping_operations = &pt_mapping_operations;
/*
* PA2KA(identity) mapping for all frames until last_frame.
*/
for (cur = 0; cur < last_frame; cur += FRAME_SIZE) {
flags = PAGE_CACHEABLE;
if ((PA2KA(cur) >= config.base) && (PA2KA(cur) < config.base + config.kernel_size))
flags |= PAGE_GLOBAL;
page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
}
exc_register(14, "page_fault", (iroutine) page_fault);
write_cr3((__address) AS_KERNEL->page_table);
}
else {
write_cr3((__address) AS_KERNEL->page_table);
}
paging_on();
}
__address hw_map(__address physaddr, size_t size)
{
if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
panic("Unable to map physical memory %p (%d bytes)", physaddr, size)
__address virtaddr = PA2KA(last_frame);
pfn_t i;
for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++)
page_mapping_insert(AS_KERNEL, virtaddr + PFN2ADDR(i), physaddr + PFN2ADDR(i), PAGE_NOT_CACHEABLE);
last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE);
return virtaddr;
}
void page_fault(int n, istate_t *istate)
{
__address page;
pf_access_t access;
page = read_cr2();
if (istate->error_word & PFERR_CODE_RSVD)
panic("Reserved bit set in page directory.\n");
if (istate->error_word & PFERR_CODE_RW)
access = PF_ACCESS_WRITE;
else
access = PF_ACCESS_READ;
if (as_page_fault(page, access, istate) == AS_PF_FAULT) {
fault_if_from_uspace(istate, "Page fault: %#x", page);
PRINT_INFO_ERRCODE(istate);
printf("page fault address: %#x\n", page);
panic("page fault\n");
}
}

/tags/0.2.0/kernel/arch/ia32/src/mm/frame.c
0,0 → 1,137
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <mm/frame.h>
#include <arch/mm/frame.h>
#include <mm/as.h>
#include <config.h>
#include <arch/boot/boot.h>
#include <arch/boot/memmap.h>
#include <panic.h>
#include <debug.h>
#include <align.h>
#include <macros.h>
#include <print.h>
#include <console/cmd.h>
#include <console/kconsole.h>
size_t hardcoded_unmapped_ktext_size = 0;
size_t hardcoded_unmapped_kdata_size = 0;
__address last_frame = 0;
static void init_e820_memory(pfn_t minconf)
{
int i;
pfn_t start, conf;
size_t size;
for (i = 0; i < e820counter; i++) {
if (e820table[i].type == MEMMAP_MEMORY_AVAILABLE) {
start = ADDR2PFN(ALIGN_UP(e820table[i].base_address,
FRAME_SIZE));
size = SIZE2FRAMES(ALIGN_DOWN(e820table[i].size,
FRAME_SIZE));
if (minconf < start || minconf >= start+size)
conf = start;
else
conf = minconf;
zone_create(start, size, conf, 0);
if (last_frame < ALIGN_UP(e820table[i].base_address + e820table[i].size, FRAME_SIZE))
last_frame = ALIGN_UP(e820table[i].base_address + e820table[i].size, FRAME_SIZE);
}
}
}
static int cmd_e820mem(cmd_arg_t *argv);
static cmd_info_t e820_info = {
.name = "e820list",
.description = "List e820 memory.",
.func = cmd_e820mem,
.argc = 0
};
static char *e820names[] = { "invalid", "available", "reserved",
"acpi", "nvs", "unusable" };
static int cmd_e820mem(cmd_arg_t *argv)
{
int i;
char *name;
for (i = 0; i < e820counter; i++) {
if (e820table[i].type <= MEMMAP_MEMORY_UNUSABLE)
name = e820names[e820table[i].type];
else
name = "invalid";
printf("%.*p %#.16llXB %s\n",
sizeof(__native) * 2,
(__native) e820table[i].base_address,
(__u64) e820table[i].size,
name);
}
return 0;
}
void frame_arch_init(void)
{
static pfn_t minconf;
if (config.cpu_active == 1) {
cmd_initialize(&e820_info);
cmd_register(&e820_info);
minconf = 1;
#ifdef CONFIG_SMP
minconf = max(minconf,
ADDR2PFN(AP_BOOT_OFFSET+hardcoded_unmapped_ktext_size + hardcoded_unmapped_kdata_size));
#endif
#ifdef CONFIG_SIMICS_FIX
minconf = max(minconf, ADDR2PFN(0x10000));
#endif
init_e820_memory(minconf);
/* Reserve frame 0 (BIOS data) */
frame_mark_unavailable(0, 1);
#ifdef CONFIG_SMP
/* Reserve AP real mode bootstrap memory */
frame_mark_unavailable(AP_BOOT_OFFSET >> FRAME_WIDTH,
(hardcoded_unmapped_ktext_size + hardcoded_unmapped_kdata_size) >> FRAME_WIDTH);
#ifdef CONFIG_SIMICS_FIX
/* Don't know why, but this addresses help */
frame_mark_unavailable(0xd000 >> FRAME_WIDTH,3);
#endif
#endif
}
}

/tags/0.2.0/kernel/arch/ia32/src/mm/memory_init.c
0,0 → 1,71
/*
* Copyright (C) 2005 Josef Cejka
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/boot/memmap.h>
#include <arch/mm/memory_init.h>
#include <arch/mm/page.h>
#include <print.h>
__u8 e820counter = 0xff;
struct e820memmap_ e820table[MEMMAP_E820_MAX_RECORDS];
__u32 e801memorysize;
size_t get_memory_size(void)
{
return e801memorysize*1024;
}
void memory_print_map(void)
{
__u8 i;
for (i=0;i<e820counter;i++) {
printf("E820 base: %#.16llx size: %#.16llx type: ", e820table[i].base_address, e820table[i].size);
switch (e820table[i].type) {
case MEMMAP_MEMORY_AVAILABLE:
printf("available memory\n");
break;
case MEMMAP_MEMORY_RESERVED:
printf("reserved memory\n");
break;
case MEMMAP_MEMORY_ACPI:
printf("ACPI table\n");
break;
case MEMMAP_MEMORY_NVS:
printf("NVS\n");
break;
case MEMMAP_MEMORY_UNUSABLE:
printf("unusable memory\n");
break;
default:
printf("undefined memory type\n");
}
}
}

/tags/0.2.0/kernel/arch/ia32/src/mm/as.c
0,0 → 1,36
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/as.h>
#include <genarch/mm/as_pt.h>
/** Architecture dependent address space init. */
void as_arch_init(void)
{
as_operations = &as_pt_operations;
}

/tags/0.2.0/kernel/arch/ia32/src/mm/tlb.c
0,0 → 1,61
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <mm/tlb.h>
#include <arch/mm/asid.h>
#include <arch/asm.h>
#include <arch/types.h>
/** Invalidate all entries in TLB. */
void tlb_invalidate_all(void)
{
write_cr3(read_cr3());
}
/** Invalidate all entries in TLB that belong to specified address space.
*
* @param asid This parameter is ignored as the architecture doesn't support it.
*/
void tlb_invalidate_asid(asid_t asid)
{
tlb_invalidate_all();
}
/** Invalidate TLB entries for specified page range belonging to specified address space.
*
* @param asid This parameter is ignored as the architecture doesn't support it.
* @param page Address of the first page whose entry is to be invalidated.
* @param cnt Number of entries to invalidate.
*/
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
int i;
for (i = 0; i < cnt; i++)
invlpg(page + i * PAGE_SIZE);
}

/tags/0.2.0/kernel/arch/ia32/src/interrupt.c
0,0 → 1,199
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/interrupt.h>
#include <syscall/syscall.h>
#include <print.h>
#include <debug.h>
#include <panic.h>
#include <arch/drivers/i8259.h>
#include <func.h>
#include <cpu.h>
#include <arch/asm.h>
#include <mm/tlb.h>
#include <mm/as.h>
#include <arch.h>
#include <symtab.h>
#include <proc/thread.h>
#include <proc/task.h>
#include <synch/spinlock.h>
#include <arch/ddi/ddi.h>
#include <ipc/sysipc.h>
#include <interrupt.h>
/*
* Interrupt and exception dispatching.
*/
void (* disable_irqs_function)(__u16 irqmask) = NULL;
void (* enable_irqs_function)(__u16 irqmask) = NULL;
void (* eoi_function)(void) = NULL;
void PRINT_INFO_ERRCODE(istate_t *istate)
{
char *symbol = get_symtab_entry(istate->eip);
if (!symbol)
symbol = "";
if (CPU)
printf("----------------EXCEPTION OCCURED (cpu%d)----------------\n", CPU->id);
else
printf("----------------EXCEPTION OCCURED----------------\n");
printf("%%eip: %#x (%s)\n",istate->eip,symbol);
printf("ERROR_WORD=%#x\n", istate->error_word);
printf("%%cs=%#x,flags=%#x\n", istate->cs, istate->eflags);
printf("%%eax=%#x, %%ecx=%#x, %%edx=%#x, %%esp=%#x\n", istate->eax,istate->ecx,istate->edx,&istate->stack[0]);
#ifdef CONFIG_DEBUG_ALLREGS
printf("%%esi=%#x, %%edi=%#x, %%ebp=%#x, %%ebx=%#x\n", istate->esi,istate->edi,istate->ebp,istate->ebx);
#endif
printf("stack: %#x, %#x, %#x, %#x\n", istate->stack[0], istate->stack[1], istate->stack[2], istate->stack[3]);
printf(" %#x, %#x, %#x, %#x\n", istate->stack[4], istate->stack[5], istate->stack[6], istate->stack[7]);
}
void null_interrupt(int n, istate_t *istate)
{
fault_if_from_uspace(istate, "unserviced interrupt: %d", n);
PRINT_INFO_ERRCODE(istate);
panic("unserviced interrupt: %d\n", n);
}
/** General Protection Fault. */
void gp_fault(int n, istate_t *istate)
{
if (TASK) {
count_t ver;
spinlock_lock(&TASK->lock);
ver = TASK->arch.iomapver;
spinlock_unlock(&TASK->lock);
if (CPU->arch.iomapver_copy != ver) {
/*
* This fault can be caused by an early access
* to I/O port because of an out-dated
* I/O Permission bitmap installed on CPU.
* Install the fresh copy and restart
* the instruction.
*/
io_perm_bitmap_install();
return;
}
fault_if_from_uspace(istate, "general protection fault");
}
PRINT_INFO_ERRCODE(istate);
panic("general protection fault\n");
}
void ss_fault(int n, istate_t *istate)
{
fault_if_from_uspace(istate, "stack fault");
PRINT_INFO_ERRCODE(istate);
panic("stack fault\n");
}
void simd_fp_exception(int n, istate_t *istate)
{
__u32 mxcsr;
asm
(
"stmxcsr %0;\n"
:"=m"(mxcsr)
);
fault_if_from_uspace(istate, "SIMD FP exception(19), MXCSR: %#zX",
(__native)mxcsr);
PRINT_INFO_ERRCODE(istate);
printf("MXCSR: %#zX\n",(__native)(mxcsr));
panic("SIMD FP exception(19)\n");
}
void nm_fault(int n, istate_t *istate)
{
#ifdef CONFIG_FPU_LAZY
scheduler_fpu_lazy_request();
#else
fault_if_from_uspace(istate, "fpu fault");
panic("fpu fault");
#endif
}
void syscall(int n, istate_t *istate)
{
panic("Obsolete syscall handler.");
}
void tlb_shootdown_ipi(int n, istate_t *istate)
{
trap_virtual_eoi();
tlb_shootdown_ipi_recv();
}
void trap_virtual_enable_irqs(__u16 irqmask)
{
if (enable_irqs_function)
enable_irqs_function(irqmask);
else
panic("no enable_irqs_function\n");
}
void trap_virtual_disable_irqs(__u16 irqmask)
{
if (disable_irqs_function)
disable_irqs_function(irqmask);
else
panic("no disable_irqs_function\n");
}
void trap_virtual_eoi(void)
{
if (eoi_function)
eoi_function();
else
panic("no eoi_function\n");
}
static void ipc_int(int n, istate_t *istate)
{
trap_virtual_eoi();
ipc_irq_send_notif(n-IVT_IRQBASE);
}
/* Reregister irq to be IPC-ready */
void irq_ipc_bind_arch(__native irq)
{
if (irq == IRQ_CLK)
return;
exc_register(IVT_IRQBASE+irq, "ipc_int", ipc_int);
}

/tags/0.2.0/kernel/arch/ia32/src/proc/task.c
0,0 → 1,52
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <proc/task.h>
#include <arch/types.h>
#include <adt/bitmap.h>
#include <mm/slab.h>
/** Perform ia32 specific task initialization.
*
* @param t Task to be initialized.
*/
void task_create_arch(task_t *t)
{
t->arch.iomapver = 0;
bitmap_initialize(&t->arch.iomap, NULL, 0);
}
/** Perform ia32 specific task destruction.
*
* @param t Task to be initialized.
*/
void task_destroy_arch(task_t *t)
{
if (t->arch.iomap.map)
free(t->arch.iomap.map);
}

/tags/0.2.0/kernel/arch/ia32/src/proc/scheduler.c
0,0 → 1,72
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <proc/scheduler.h>
#include <cpu.h>
#include <proc/task.h>
#include <proc/thread.h>
#include <arch.h>
#include <arch/context.h> /* SP_DELTA */
#include <arch/debugger.h>
#include <arch/pm.h>
#include <arch/asm.h>
#include <arch/ddi/ddi.h>
/** Perform ia32 specific tasks needed before the new task is run.
*
* Interrupts are disabled.
*/
void before_task_runs_arch(void)
{
io_perm_bitmap_install();
}
/** Perform ia32 specific tasks needed before the new thread is scheduled.
*
* THREAD is locked and interrupts are disabled.
*/
void before_thread_runs_arch(void)
{
CPU->arch.tss->esp0 = (__address) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA];
CPU->arch.tss->ss0 = selector(KDATA_DES);
/* Set up TLS in GS register */
set_tls_desc(THREAD->arch.tls);
#ifdef CONFIG_DEBUG_AS_WATCHPOINT
/* Set watchpoint on AS to ensure that nobody sets it to zero */
if (CPU->id < BKPOINTS_MAX)
breakpoint_add(&((the_t *) THREAD->kstack)->as,
BKPOINT_WRITE | BKPOINT_CHECK_ZERO,
CPU->id);
#endif
}
void after_thread_ran_arch(void)
{
}

/tags/0.2.0/kernel/arch/ia32/src/proc/thread.c
0,0 → 1,38
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <proc/thread.h>
/** Perform ia32 specific thread initialization.
*
* @param t Thread to be initialized.
*/
void thread_create_arch(thread_t *t)
{
t->arch.tls = 0;
}

/tags/0.2.0/kernel/arch/ia32/src/smp/mps.c
0,0 → 1,425
/*
* Copyright (C) 2001-2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifdef CONFIG_SMP
#include <config.h>
#include <print.h>
#include <debug.h>
#include <arch/smp/mps.h>
#include <arch/smp/apic.h>
#include <arch/smp/smp.h>
#include <func.h>
#include <arch/types.h>
#include <typedefs.h>
#include <cpu.h>
#include <arch/asm.h>
#include <arch/bios/bios.h>
#include <mm/frame.h>
/*
* MultiProcessor Specification detection code.
*/
#define FS_SIGNATURE 0x5f504d5f
#define CT_SIGNATURE 0x504d4350
int mps_fs_check(__u8 *base);
int mps_ct_check(void);
int configure_via_ct(void);
int configure_via_default(__u8 n);
int ct_processor_entry(struct __processor_entry *pr);
void ct_bus_entry(struct __bus_entry *bus);
void ct_io_apic_entry(struct __io_apic_entry *ioa);
void ct_io_intr_entry(struct __io_intr_entry *iointr);
void ct_l_intr_entry(struct __l_intr_entry *lintr);
void ct_extended_entries(void);
static struct mps_fs *fs;
static struct mps_ct *ct;
struct __processor_entry *processor_entries = NULL;
struct __bus_entry *bus_entries = NULL;
struct __io_apic_entry *io_apic_entries = NULL;
struct __io_intr_entry *io_intr_entries = NULL;
struct __l_intr_entry *l_intr_entries = NULL;
int processor_entry_cnt = 0;
int bus_entry_cnt = 0;
int io_apic_entry_cnt = 0;
int io_intr_entry_cnt = 0;
int l_intr_entry_cnt = 0;
waitq_t ap_completion_wq;
/*
* Implementation of IA-32 SMP configuration interface.
*/
static count_t get_cpu_count(void);
static bool is_cpu_enabled(index_t i);
static bool is_bsp(index_t i);
static __u8 get_cpu_apic_id(index_t i);
static int mps_irq_to_pin(int irq);
struct smp_config_operations mps_config_operations = {
.cpu_count = get_cpu_count,
.cpu_enabled = is_cpu_enabled,
.cpu_bootstrap = is_bsp,
.cpu_apic_id = get_cpu_apic_id,
.irq_to_pin = mps_irq_to_pin
};
count_t get_cpu_count(void)
{
return processor_entry_cnt;
}
bool is_cpu_enabled(index_t i)
{
ASSERT(i < processor_entry_cnt);
return processor_entries[i].cpu_flags & 0x1;
}
bool is_bsp(index_t i)
{
ASSERT(i < processor_entry_cnt);
return processor_entries[i].cpu_flags & 0x2;
}
__u8 get_cpu_apic_id(index_t i)
{
ASSERT(i < processor_entry_cnt);
return processor_entries[i].l_apic_id;
}
/*
* Used to check the integrity of the MP Floating Structure.
*/
int mps_fs_check(__u8 *base)
{
int i;
__u8 sum;
for (i = 0, sum = 0; i < 16; i++)
sum += base[i];
return !sum;
}
/*
* Used to check the integrity of the MP Configuration Table.
*/
int mps_ct_check(void)
{
__u8 *base = (__u8 *) ct;
__u8 *ext = base + ct->base_table_length;
__u8 sum;
int i;
/* count the checksum for the base table */
for (i=0,sum=0; i < ct->base_table_length; i++)
sum += base[i];
if (sum)
return 0;
/* count the checksum for the extended table */
for (i=0,sum=0; i < ct->ext_table_length; i++)
sum += ext[i];
return sum == ct->ext_table_checksum;
}
void mps_init(void)
{
__u8 *addr[2] = { NULL, (__u8 *) PA2KA(0xf0000) };
int i, j, length[2] = { 1024, 64*1024 };
/*
* Find MP Floating Pointer Structure
* 1a. search first 1K of EBDA
* 1b. if EBDA is undefined, search last 1K of base memory
* 2. search 64K starting at 0xf0000
*/
addr[0] = (__u8 *) PA2KA(ebda ? ebda : 639 * 1024);
for (i = 0; i < 2; i++) {
for (j = 0; j < length[i]; j += 16) {
if (*((__u32 *) &addr[i][j]) == FS_SIGNATURE && mps_fs_check(&addr[i][j])) {
fs = (struct mps_fs *) &addr[i][j];
goto fs_found;
}
}
}
return;
fs_found:
printf("%p: MPS Floating Pointer Structure\n", fs);
if (fs->config_type == 0 && fs->configuration_table) {
if (fs->mpfib2 >> 7) {
printf("%s: PIC mode not supported\n", __FUNCTION__);
return;
}
ct = (struct mps_ct *)PA2KA((__address)fs->configuration_table);
config.cpu_count = configure_via_ct();
}
else
config.cpu_count = configure_via_default(fs->config_type);
return;
}
int configure_via_ct(void)
{
__u8 *cur;
int i, cnt;
if (ct->signature != CT_SIGNATURE) {
printf("%s: bad ct->signature\n", __FUNCTION__);
return 1;
}
if (!mps_ct_check()) {
printf("%s: bad ct checksum\n", __FUNCTION__);
return 1;
}
if (ct->oem_table) {
printf("%s: ct->oem_table not supported\n", __FUNCTION__);
return 1;
}
l_apic = (__u32 *)(__address)ct->l_apic;
cnt = 0;
cur = &ct->base_table[0];
for (i=0; i < ct->entry_count; i++) {
switch (*cur) {
/* Processor entry */
case 0:
processor_entries = processor_entries ? processor_entries : (struct __processor_entry *) cur;
processor_entry_cnt++;
cnt += ct_processor_entry((struct __processor_entry *) cur);
cur += 20;
break;
/* Bus entry */
case 1:
bus_entries = bus_entries ? bus_entries : (struct __bus_entry *) cur;
bus_entry_cnt++;
ct_bus_entry((struct __bus_entry *) cur);
cur += 8;
break;
/* I/O Apic */
case 2:
io_apic_entries = io_apic_entries ? io_apic_entries : (struct __io_apic_entry *) cur;
io_apic_entry_cnt++;
ct_io_apic_entry((struct __io_apic_entry *) cur);
cur += 8;
break;
/* I/O Interrupt Assignment */
case 3:
io_intr_entries = io_intr_entries ? io_intr_entries : (struct __io_intr_entry *) cur;
io_intr_entry_cnt++;
ct_io_intr_entry((struct __io_intr_entry *) cur);
cur += 8;
break;
/* Local Interrupt Assignment */
case 4:
l_intr_entries = l_intr_entries ? l_intr_entries : (struct __l_intr_entry *) cur;
l_intr_entry_cnt++;
ct_l_intr_entry((struct __l_intr_entry *) cur);
cur += 8;
break;
default:
/*
* Something is wrong. Fallback to UP mode.
*/
printf("%s: ct badness\n", __FUNCTION__);
return 1;
}
}
/*
* Process extended entries.
*/
ct_extended_entries();
return cnt;
}
int configure_via_default(__u8 n)
{
/*
* Not yet implemented.
*/
printf("%s: not supported\n", __FUNCTION__);
return 1;
}
int ct_processor_entry(struct __processor_entry *pr)
{
/*
* Ignore processors which are not marked enabled.
*/
if ((pr->cpu_flags & (1<<0)) == 0)
return 0;
apic_id_mask |= (1<<pr->l_apic_id);
return 1;
}
void ct_bus_entry(struct __bus_entry *bus)
{
#ifdef MPSCT_VERBOSE
char buf[7];
memcpy((void *) buf, (void *) bus->bus_type, 6);
buf[6] = 0;
printf("bus%d: %s\n", bus->bus_id, buf);
#endif
}
void ct_io_apic_entry(struct __io_apic_entry *ioa)
{
static int io_apic_count = 0;
/* this ioapic is marked unusable */
if ((ioa->io_apic_flags & 1) == 0)
return;
if (io_apic_count++ > 0) {
/*
* Multiple IO APIC's are currently not supported.
*/
return;
}
io_apic = (__u32 *)(__address)ioa->io_apic;
}
//#define MPSCT_VERBOSE
void ct_io_intr_entry(struct __io_intr_entry *iointr)
{
#ifdef MPSCT_VERBOSE
switch (iointr->intr_type) {
case 0: printf("INT"); break;
case 1: printf("NMI"); break;
case 2: printf("SMI"); break;
case 3: printf("ExtINT"); break;
}
putchar(',');
switch (iointr->poel&3) {
case 0: printf("bus-like"); break;
case 1: printf("active high"); break;
case 2: printf("reserved"); break;
case 3: printf("active low"); break;
}
putchar(',');
switch ((iointr->poel>>2)&3) {
case 0: printf("bus-like"); break;
case 1: printf("edge-triggered"); break;
case 2: printf("reserved"); break;
case 3: printf("level-triggered"); break;
}
putchar(',');
printf("bus%d,irq%d", iointr->src_bus_id, iointr->src_bus_irq);
putchar(',');
printf("io_apic%d,pin%d", iointr->dst_io_apic_id, iointr->dst_io_apic_pin);
putchar('\n');
#endif
}
void ct_l_intr_entry(struct __l_intr_entry *lintr)
{
#ifdef MPSCT_VERBOSE
switch (lintr->intr_type) {
case 0: printf("INT"); break;
case 1: printf("NMI"); break;
case 2: printf("SMI"); break;
case 3: printf("ExtINT"); break;
}
putchar(',');
switch (lintr->poel&3) {
case 0: printf("bus-like"); break;
case 1: printf("active high"); break;
case 2: printf("reserved"); break;
case 3: printf("active low"); break;
}
putchar(',');
switch ((lintr->poel>>2)&3) {
case 0: printf("bus-like"); break;
case 1: printf("edge-triggered"); break;
case 2: printf("reserved"); break;
case 3: printf("level-triggered"); break;
}
putchar(',');
printf("bus%d,irq%d", lintr->src_bus_id, lintr->src_bus_irq);
putchar(',');
printf("l_apic%d,pin%d", lintr->dst_l_apic_id, lintr->dst_l_apic_pin);
putchar('\n');
#endif
}
void ct_extended_entries(void)
{
__u8 *ext = (__u8 *) ct + ct->base_table_length;
__u8 *cur;
for (cur = ext; cur < ext + ct->ext_table_length; cur += cur[CT_EXT_ENTRY_LEN]) {
switch (cur[CT_EXT_ENTRY_TYPE]) {
default:
printf("%p: skipping MP Configuration Table extended entry type %d\n", cur, cur[CT_EXT_ENTRY_TYPE]);
break;
}
}
}
int mps_irq_to_pin(int irq)
{
int i;
for(i=0;i<io_intr_entry_cnt;i++) {
if (io_intr_entries[i].src_bus_irq == irq && io_intr_entries[i].intr_type == 0)
return io_intr_entries[i].dst_io_apic_pin;
}
return -1;
}
#endif /* CONFIG_SMP */

/tags/0.2.0/kernel/arch/ia32/src/smp/smp.c
0,0 → 1,176
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <smp/smp.h>
#include <arch/smp/smp.h>
#include <arch/smp/mps.h>
#include <arch/smp/ap.h>
#include <arch/boot/boot.h>
#include <genarch/acpi/acpi.h>
#include <genarch/acpi/madt.h>
#include <config.h>
#include <synch/waitq.h>
#include <synch/synch.h>
#include <arch/pm.h>
#include <func.h>
#include <panic.h>
#include <debug.h>
#include <arch/asm.h>
#include <mm/frame.h>
#include <mm/page.h>
#include <mm/slab.h>
#include <mm/as.h>
#include <print.h>
#include <memstr.h>
#include <arch/drivers/i8259.h>
#ifdef CONFIG_SMP
static struct smp_config_operations *ops = NULL;
void smp_init(void)
{
int status;
__address l_apic_address, io_apic_address;
if (acpi_madt) {
acpi_madt_parse();
ops = &madt_config_operations;
}
if (config.cpu_count == 1) {
mps_init();
ops = &mps_config_operations;
}
l_apic_address = PA2KA(PFN2ADDR(frame_alloc_rc(ONE_FRAME, FRAME_ATOMIC | FRAME_KA, &status)));
if (status != FRAME_OK)
panic("cannot allocate address for l_apic\n");
io_apic_address = PA2KA(PFN2ADDR(frame_alloc_rc(ONE_FRAME, FRAME_ATOMIC | FRAME_KA, &status)));
if (status != FRAME_OK)
panic("cannot allocate address for io_apic\n");
if (config.cpu_count > 1) {
page_mapping_insert(AS_KERNEL, l_apic_address, (__address) l_apic,
PAGE_NOT_CACHEABLE);
page_mapping_insert(AS_KERNEL, io_apic_address, (__address) io_apic,
PAGE_NOT_CACHEABLE);
l_apic = (__u32 *) l_apic_address;
io_apic = (__u32 *) io_apic_address;
}
}
/*
* Kernel thread for bringing up application processors. It becomes clear
* that we need an arrangement like this (AP's being initialized by a kernel
* thread), for a thread has its dedicated stack. (The stack used during the
* BSP initialization (prior the very first call to scheduler()) will be used
* as an initialization stack for each AP.)
*/
void kmp(void *arg)
{
int i;
ASSERT(ops != NULL);
waitq_initialize(&ap_completion_wq);
/*
* We need to access data in frame 0.
* We boldly make use of kernel address space mapping.
*/
/*
* Set the warm-reset vector to the real-mode address of 4K-aligned ap_boot()
*/
*((__u16 *) (PA2KA(0x467+0))) = ((__address) ap_boot) >> 4; /* segment */
*((__u16 *) (PA2KA(0x467+2))) = 0; /* offset */
/*
* Save 0xa to address 0xf of the CMOS RAM.
* BIOS will not do the POST after the INIT signal.
*/
outb(0x70,0xf);
outb(0x71,0xa);
pic_disable_irqs(0xffff);
apic_init();
for (i = 0; i < ops->cpu_count(); i++) {
struct descriptor *gdt_new;
/*
* Skip processors marked unusable.
*/
if (!ops->cpu_enabled(i))
continue;
/*
* The bootstrap processor is already up.
*/
if (ops->cpu_bootstrap(i))
continue;
if (ops->cpu_apic_id(i) == l_apic_id()) {
printf("%s: bad processor entry #%d, will not send IPI to myself\n", __FUNCTION__, i);
continue;
}
/*
* Prepare new GDT for CPU in question.
*/
if (!(gdt_new = (struct descriptor *) malloc(GDT_ITEMS*sizeof(struct descriptor), FRAME_ATOMIC)))
panic("couldn't allocate memory for GDT\n");
memcpy(gdt_new, gdt, GDT_ITEMS * sizeof(struct descriptor));
memsetb((__address)(&gdt_new[TSS_DES]), sizeof(struct descriptor), 0);
protected_ap_gdtr.limit = GDT_ITEMS * sizeof(struct descriptor);
protected_ap_gdtr.base = KA2PA((__address) gdt_new);
gdtr.base = (__address) gdt_new;
if (l_apic_send_init_ipi(ops->cpu_apic_id(i))) {
/*
* There may be just one AP being initialized at
* the time. After it comes completely up, it is
* supposed to wake us up.
*/
if (waitq_sleep_timeout(&ap_completion_wq, 1000000, SYNCH_FLAGS_NONE) == ESYNCH_TIMEOUT)
printf("%s: waiting for cpu%d (APIC ID = %d) timed out\n", __FUNCTION__, config.cpu_active > i ? config.cpu_active : i, ops->cpu_apic_id(i));
} else
printf("INIT IPI for l_apic%d failed\n", ops->cpu_apic_id(i));
}
}
int smp_irq_to_pin(int irq)
{
ASSERT(ops != NULL);
return ops->irq_to_pin(irq);
}
#endif /* CONFIG_SMP */

/tags/0.2.0/kernel/arch/ia32/src/smp/apic.c
0,0 → 1,563
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/types.h>
#include <arch/smp/apic.h>
#include <arch/smp/ap.h>
#include <arch/smp/mps.h>
#include <arch/boot/boot.h>
#include <mm/page.h>
#include <time/delay.h>
#include <interrupt.h>
#include <arch/interrupt.h>
#include <print.h>
#include <arch/asm.h>
#include <arch.h>
#ifdef CONFIG_SMP
/*
* Advanced Programmable Interrupt Controller for SMP systems.
* Tested on:
* Bochs 2.0.2 - Bochs 2.2.6 with 2-8 CPUs
* Simics 2.0.28 - Simics 2.2.19 2-15 CPUs
* VMware Workstation 5.5 with 2 CPUs
* QEMU 0.8.0 with 2-15 CPUs
* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
* ASUS PCH-DL with 2x 3000Mhz Pentium 4 Xeon (HT) CPUs
* MSI K7D Master-L with 2x 2100MHz Athlon MP CPUs
*/
/*
* These variables either stay configured as initilalized, or are changed by
* the MP configuration code.
*
* Pay special attention to the volatile keyword. Without it, gcc -O2 would
* optimize the code too much and accesses to l_apic and io_apic, that must
* always be 32-bit, would use byte oriented instructions.
*/
volatile __u32 *l_apic = (__u32 *) 0xfee00000;
volatile __u32 *io_apic = (__u32 *) 0xfec00000;
__u32 apic_id_mask = 0;
static int apic_poll_errors(void);
#ifdef LAPIC_VERBOSE
static char *delmod_str[] = {
"Fixed",
"Lowest Priority",
"SMI",
"Reserved",
"NMI",
"INIT",
"STARTUP",
"ExtInt"
};
static char *destmod_str[] = {
"Physical",
"Logical"
};
static char *trigmod_str[] = {
"Edge",
"Level"
};
static char *mask_str[] = {
"Unmasked",
"Masked"
};
static char *delivs_str[] = {
"Idle",
"Send Pending"
};
static char *tm_mode_str[] = {
"One-shot",
"Periodic"
};
static char *intpol_str[] = {
"Polarity High",
"Polarity Low"
};
#endif /* LAPIC_VERBOSE */
static void apic_spurious(int n, istate_t *istate);
static void l_apic_timer_interrupt(int n, istate_t *istate);
/** Initialize APIC on BSP. */
void apic_init(void)
{
io_apic_id_t idreg;
int i;
exc_register(VECTOR_APIC_SPUR, "apic_spurious", (iroutine) apic_spurious);
enable_irqs_function = io_apic_enable_irqs;
disable_irqs_function = io_apic_disable_irqs;
eoi_function = l_apic_eoi;
/*
* Configure interrupt routing.
* IRQ 0 remains masked as the time signal is generated by l_apic's themselves.
* Other interrupts will be forwarded to the lowest priority CPU.
*/
io_apic_disable_irqs(0xffff);
exc_register(VECTOR_CLK, "l_apic_timer", (iroutine) l_apic_timer_interrupt);
for (i = 0; i < IRQ_COUNT; i++) {
int pin;
if ((pin = smp_irq_to_pin(i)) != -1) {
io_apic_change_ioredtbl(pin, DEST_ALL, IVT_IRQBASE+i, LOPRI);
}
}
/*
* Ensure that io_apic has unique ID.
*/
idreg.value = io_apic_read(IOAPICID);
if ((1<<idreg.apic_id) & apic_id_mask) { /* see if IO APIC ID is used already */
for (i = 0; i < APIC_ID_COUNT; i++) {
if (!((1<<i) & apic_id_mask)) {
idreg.apic_id = i;
io_apic_write(IOAPICID, idreg.value);
break;
}
}
}
/*
* Configure the BSP's lapic.
*/
l_apic_init();
l_apic_debug();
}
/** APIC spurious interrupt handler.
*
* @param n Interrupt vector.
* @param stack Interrupted stack.
*/
void apic_spurious(int n, istate_t *istate)
{
printf("cpu%d: APIC spurious interrupt\n", CPU->id);
}
/** Poll for APIC errors.
*
* Examine Error Status Register and report all errors found.
*
* @return 0 on error, 1 on success.
*/
int apic_poll_errors(void)
{
esr_t esr;
esr.value = l_apic[ESR];
if (esr.send_checksum_error)
printf("Send Checksum Error\n");
if (esr.receive_checksum_error)
printf("Receive Checksum Error\n");
if (esr.send_accept_error)
printf("Send Accept Error\n");
if (esr.receive_accept_error)
printf("Receive Accept Error\n");
if (esr.send_illegal_vector)
printf("Send Illegal Vector\n");
if (esr.received_illegal_vector)
printf("Received Illegal Vector\n");
if (esr.illegal_register_address)
printf("Illegal Register Address\n");
return !esr.err_bitmap;
}
/** Send all CPUs excluding CPU IPI vector.
*
* @param vector Interrupt vector to be sent.
*
* @return 0 on failure, 1 on success.
*/
int l_apic_broadcast_custom_ipi(__u8 vector)
{
icr_t icr;
icr.lo = l_apic[ICRlo];
icr.delmod = DELMOD_FIXED;
icr.destmod = DESTMOD_LOGIC;
icr.level = LEVEL_ASSERT;
icr.shorthand = SHORTHAND_ALL_EXCL;
icr.trigger_mode = TRIGMOD_LEVEL;
icr.vector = vector;
l_apic[ICRlo] = icr.lo;
icr.lo = l_apic[ICRlo];
if (icr.delivs == DELIVS_PENDING)
printf("IPI is pending.\n");
return apic_poll_errors();
}
/** Universal Start-up Algorithm for bringing up the AP processors.
*
* @param apicid APIC ID of the processor to be brought up.
*
* @return 0 on failure, 1 on success.
*/
int l_apic_send_init_ipi(__u8 apicid)
{
icr_t icr;
int i;
/*
* Read the ICR register in and zero all non-reserved fields.
*/
icr.lo = l_apic[ICRlo];
icr.hi = l_apic[ICRhi];
icr.delmod = DELMOD_INIT;
icr.destmod = DESTMOD_PHYS;
icr.level = LEVEL_ASSERT;
icr.trigger_mode = TRIGMOD_LEVEL;
icr.shorthand = SHORTHAND_NONE;
icr.vector = 0;
icr.dest = apicid;
l_apic[ICRhi] = icr.hi;
l_apic[ICRlo] = icr.lo;
/*
* According to MP Specification, 20us should be enough to
* deliver the IPI.
*/
delay(20);
if (!apic_poll_errors()) return 0;
icr.lo = l_apic[ICRlo];
if (icr.delivs == DELIVS_PENDING)
printf("IPI is pending.\n");
icr.delmod = DELMOD_INIT;
icr.destmod = DESTMOD_PHYS;
icr.level = LEVEL_DEASSERT;
icr.shorthand = SHORTHAND_NONE;
icr.trigger_mode = TRIGMOD_LEVEL;
icr.vector = 0;
l_apic[ICRlo] = icr.lo;
/*
* Wait 10ms as MP Specification specifies.
*/
delay(10000);
if (!is_82489DX_apic(l_apic[LAVR])) {
/*
* If this is not 82489DX-based l_apic we must send two STARTUP IPI's.
*/
for (i = 0; i<2; i++) {
icr.lo = l_apic[ICRlo];
icr.vector = ((__address) ap_boot) / 4096; /* calculate the reset vector */
icr.delmod = DELMOD_STARTUP;
icr.destmod = DESTMOD_PHYS;
icr.level = LEVEL_ASSERT;
icr.shorthand = SHORTHAND_NONE;
icr.trigger_mode = TRIGMOD_LEVEL;
l_apic[ICRlo] = icr.lo;
delay(200);
}
}
return apic_poll_errors();
}
/** Initialize Local APIC. */
void l_apic_init(void)
{
lvt_error_t error;
lvt_lint_t lint;
tpr_t tpr;
svr_t svr;
icr_t icr;
tdcr_t tdcr;
lvt_tm_t tm;
ldr_t ldr;
dfr_t dfr;
__u32 t1, t2;
/* Initialize LVT Error register. */
error.value = l_apic[LVT_Err];
error.masked = true;
l_apic[LVT_Err] = error.value;
/* Initialize LVT LINT0 register. */
lint.value = l_apic[LVT_LINT0];
lint.masked = true;
l_apic[LVT_LINT0] = lint.value;
/* Initialize LVT LINT1 register. */
lint.value = l_apic[LVT_LINT1];
lint.masked = true;
l_apic[LVT_LINT1] = lint.value;
/* Task Priority Register initialization. */
tpr.value = l_apic[TPR];
tpr.pri_sc = 0;
tpr.pri = 0;
l_apic[TPR] = tpr.value;
/* Spurious-Interrupt Vector Register initialization. */
svr.value = l_apic[SVR];
svr.vector = VECTOR_APIC_SPUR;
svr.lapic_enabled = true;
svr.focus_checking = true;
l_apic[SVR] = svr.value;
if (CPU->arch.family >= 6)
enable_l_apic_in_msr();
/* Interrupt Command Register initialization. */
icr.lo = l_apic[ICRlo];
icr.delmod = DELMOD_INIT;
icr.destmod = DESTMOD_PHYS;
icr.level = LEVEL_DEASSERT;
icr.shorthand = SHORTHAND_ALL_INCL;
icr.trigger_mode = TRIGMOD_LEVEL;
l_apic[ICRlo] = icr.lo;
/* Timer Divide Configuration Register initialization. */
tdcr.value = l_apic[TDCR];
tdcr.div_value = DIVIDE_1;
l_apic[TDCR] = tdcr.value;
/* Program local timer. */
tm.value = l_apic[LVT_Tm];
tm.vector = VECTOR_CLK;
tm.mode = TIMER_PERIODIC;
tm.masked = false;
l_apic[LVT_Tm] = tm.value;
/*
* Measure and configure the timer to generate timer
* interrupt with period 1s/HZ seconds.
*/
t1 = l_apic[CCRT];
l_apic[ICRT] = 0xffffffff;
while (l_apic[CCRT] == t1)
;
t1 = l_apic[CCRT];
delay(1000000/HZ);
t2 = l_apic[CCRT];
l_apic[ICRT] = t1-t2;
/* Program Logical Destination Register. */
ldr.value = l_apic[LDR];
if (CPU->id < sizeof(CPU->id)*8) /* size in bits */
ldr.id = (1<<CPU->id);
l_apic[LDR] = ldr.value;
/* Program Destination Format Register for Flat mode. */
dfr.value = l_apic[DFR];
dfr.model = MODEL_FLAT;
l_apic[DFR] = dfr.value;
}
/** Local APIC End of Interrupt. */
void l_apic_eoi(void)
{
l_apic[EOI] = 0;
}
/** Dump content of Local APIC registers. */
void l_apic_debug(void)
{
#ifdef LAPIC_VERBOSE
lvt_tm_t tm;
lvt_lint_t lint;
lvt_error_t error;
printf("LVT on cpu%d, LAPIC ID: %d\n", CPU->id, l_apic_id());
tm.value = l_apic[LVT_Tm];
printf("LVT Tm: vector=%hhd, %s, %s, %s\n", tm.vector, delivs_str[tm.delivs], mask_str[tm.masked], tm_mode_str[tm.mode]);
lint.value = l_apic[LVT_LINT0];
printf("LVT LINT0: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
lint.value = l_apic[LVT_LINT1];
printf("LVT LINT1: vector=%hhd, %s, %s, %s, irr=%d, %s, %s\n", tm.vector, delmod_str[lint.delmod], delivs_str[lint.delivs], intpol_str[lint.intpol], lint.irr, trigmod_str[lint.trigger_mode], mask_str[lint.masked]);
error.value = l_apic[LVT_Err];
printf("LVT Err: vector=%hhd, %s, %s\n", error.vector, delivs_str[error.delivs], mask_str[error.masked]);
#endif
}
/** Local APIC Timer Interrupt.
*
* @param n Interrupt vector number.
* @param stack Interrupted stack.
*/
void l_apic_timer_interrupt(int n, istate_t *istate)
{
l_apic_eoi();
clock();
}
/** Get Local APIC ID.
*
* @return Local APIC ID.
*/
__u8 l_apic_id(void)
{
l_apic_id_t idreg;
idreg.value = l_apic[L_APIC_ID];
return idreg.apic_id;
}
/** Read from IO APIC register.
*
* @param address IO APIC register address.
*
* @return Content of the addressed IO APIC register.
*/
__u32 io_apic_read(__u8 address)
{
io_regsel_t regsel;
regsel.value = io_apic[IOREGSEL];
regsel.reg_addr = address;
io_apic[IOREGSEL] = regsel.value;
return io_apic[IOWIN];
}
/** Write to IO APIC register.
*
* @param address IO APIC register address.
* @param Content to be written to the addressed IO APIC register.
*/
void io_apic_write(__u8 address, __u32 x)
{
io_regsel_t regsel;
regsel.value = io_apic[IOREGSEL];
regsel.reg_addr = address;
io_apic[IOREGSEL] = regsel.value;
io_apic[IOWIN] = x;
}
/** Change some attributes of one item in I/O Redirection Table.
*
* @param pin IO APIC pin number.
* @param dest Interrupt destination address.
* @param v Interrupt vector to trigger.
* @param flags Flags.
*/
void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags)
{
io_redirection_reg_t reg;
int dlvr = DELMOD_FIXED;
if (flags & LOPRI)
dlvr = DELMOD_LOWPRI;
reg.lo = io_apic_read(IOREDTBL + pin*2);
reg.hi = io_apic_read(IOREDTBL + pin*2 + 1);
reg.dest = dest;
reg.destmod = DESTMOD_LOGIC;
reg.trigger_mode = TRIGMOD_EDGE;
reg.intpol = POLARITY_HIGH;
reg.delmod = dlvr;
reg.intvec = v;
io_apic_write(IOREDTBL + pin*2, reg.lo);
io_apic_write(IOREDTBL + pin*2 + 1, reg.hi);
}
/** Mask IRQs in IO APIC.
*
* @param irqmask Bitmask of IRQs to be masked (0 = do not mask, 1 = mask).
*/
void io_apic_disable_irqs(__u16 irqmask)
{
io_redirection_reg_t reg;
int i, pin;
for (i=0;i<16;i++) {
if (irqmask & (1<<i)) {
/*
* Mask the signal input in IO APIC if there is a
* mapping for the respective IRQ number.
*/
pin = smp_irq_to_pin(i);
if (pin != -1) {
reg.lo = io_apic_read(IOREDTBL + pin*2);
reg.masked = true;
io_apic_write(IOREDTBL + pin*2, reg.lo);
}
}
}
}
/** Unmask IRQs in IO APIC.
*
* @param irqmask Bitmask of IRQs to be unmasked (0 = do not unmask, 1 = unmask).
*/
void io_apic_enable_irqs(__u16 irqmask)
{
int i, pin;
io_redirection_reg_t reg;
for (i=0;i<16;i++) {
if (irqmask & (1<<i)) {
/*
* Unmask the signal input in IO APIC if there is a
* mapping for the respective IRQ number.
*/
pin = smp_irq_to_pin(i);
if (pin != -1) {
reg.lo = io_apic_read(IOREDTBL + pin*2);
reg.masked = false;
io_apic_write(IOREDTBL + pin*2, reg.lo);
}
}
}
}
#endif /* CONFIG_SMP */

/tags/0.2.0/kernel/arch/ia32/src/smp/ap.S
0,0 → 1,95
#
# Copyright (C) 2001-2004 Jakub Jermar
# Copyright (C) 2005-2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#
# Init code for application processors.
#
#include <arch/boot/boot.h>
#include <arch/boot/memmap.h>
#include <arch/mm/page.h>
#include <arch/pm.h>
.section K_TEXT_START, "ax"
#ifdef CONFIG_SMP
.global unmapped_ap_boot
KTEXT=8
KDATA=16
# This piece of code is real-mode and is meant to be alligned at 4K boundary.
# The requirement for such an alignment comes from MP Specification's STARTUP IPI
# requirements.
.align 4096
unmapped_ap_boot:
.code16
cli
xorw %ax, %ax
movw %ax, %ds
lgdtl ap_gdtr # initialize Global Descriptor Table register
movl %cr0, %eax
orl $1, %eax
movl %eax, %cr0 # switch to protected mode
jmpl $KTEXT, $jump_to_kernel - BOOT_OFFSET + AP_BOOT_OFFSET
jump_to_kernel:
.code32
movw $KDATA, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
movl $KA2PA(ctx), %eax # KA2PA((__address) &ctx)
movl (%eax), %esp
subl $0x80000000, %esp # KA2PA(ctx.sp)
call map_kernel # map kernel and turn paging on
addl $0x80000000, %esp # PA2KA(ctx.sp)
jmpl $KTEXT, $main_ap
#endif /* CONFIG_SMP */
.section K_DATA_START, "aw", @progbits
#ifdef CONFIG_SMP
.global unmapped_ap_gdtr
unmapped_ap_gdtr:
.word 0
.long 0
#endif /* CONFIG_SMP */

/tags/0.2.0/kernel/arch/ia32/src/smp/ipi.c
0,0 → 1,39
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifdef CONFIG_SMP
#include <smp/ipi.h>
#include <arch/smp/apic.h>
void ipi_broadcast_arch(int ipi)
{
(void) l_apic_broadcast_custom_ipi((__u8) ipi);
}
#endif /* CONFIG_SMP */

/tags/0.2.0/kernel/arch/ia32/src/ia32.c
0,0 → 1,150
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <arch/types.h>
#include <typedefs.h>
#include <arch/pm.h>
#include <arch/drivers/ega.h>
#include <arch/drivers/vesa.h>
#include <genarch/i8042/i8042.h>
#include <arch/drivers/i8254.h>
#include <arch/drivers/i8259.h>
#include <arch/context.h>
#include <config.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <genarch/acpi/acpi.h>
#include <arch/bios/bios.h>
#include <arch/mm/memory_init.h>
#include <interrupt.h>
#include <arch/debugger.h>
#include <proc/thread.h>
#include <syscall/syscall.h>
#include <console/console.h>
void arch_pre_mm_init(void)
{
pm_init();
if (config.cpu_active == 1) {
bios_init();
i8259_init(); /* PIC */
i8254_init(); /* hard clock */
exc_register(VECTOR_SYSCALL, "syscall", (iroutine) syscall);
#ifdef CONFIG_SMP
exc_register(VECTOR_TLB_SHOOTDOWN_IPI, "tlb_shootdown",
(iroutine) tlb_shootdown_ipi);
#endif /* CONFIG_SMP */
}
}
void arch_post_mm_init(void)
{
if (config.cpu_active == 1) {
#ifdef CONFIG_FB
if (vesa_present())
vesa_init();
else
#endif
ega_init(); /* video */
/* Enable debugger */
debugger_init();
/* Merge all memory zones to 1 big zone */
zone_merge_all();
}
}
void arch_pre_smp_init(void)
{
if (config.cpu_active == 1) {
memory_print_map();
#ifdef CONFIG_SMP
acpi_init();
#endif /* CONFIG_SMP */
}
}
void arch_post_smp_init(void)
{
i8042_init(); /* keyboard controller */
}
void calibrate_delay_loop(void)
{
i8254_calibrate_delay_loop();
if (config.cpu_active == 1) {
/*
* This has to be done only on UP.
* On SMP, i8254 is not used for time keeping and its interrupt pin remains masked.
*/
i8254_normal_operation();
}
}
/** Set thread-local-storage pointer
*
* TLS pointer is set in GS register. That means, the GS contains
* selector, and the descriptor->base is the correct address.
*/
__native sys_tls_set(__native addr)
{
THREAD->arch.tls = addr;
set_tls_desc(addr);
return 0;
}
/** Acquire console back for kernel
*
*/
void arch_grab_console(void)
{
i8042_grab();
}
/** Return console to userspace
*
*/
void arch_release_console(void)
{
i8042_release();
}

/tags/0.2.0/kernel/arch/ia32/src/drivers/vesa.c
0,0 → 1,65
/*
* Copyright (C) 2006 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifdef CONFIG_FB
#include <genarch/fb/fb.h>
#include <arch/drivers/vesa.h>
#include <putchar.h>
#include <mm/page.h>
#include <mm/frame.h>
#include <mm/as.h>
#include <arch/mm/page.h>
#include <synch/spinlock.h>
#include <arch/asm.h>
#include <arch/types.h>
#include <typedefs.h>
#include <memstr.h>
#include <bitops.h>
__u32 vesa_ph_addr;
__u16 vesa_width;
__u16 vesa_height;
__u16 vesa_bpp;
__u16 vesa_scanline;
int vesa_present(void)
{
if (vesa_width != 0xffff)
return true;
if (vesa_height != 0xffff)
return true;
return false;
}
void vesa_init(void)
{
fb_init(vesa_ph_addr, vesa_width, vesa_height, vesa_bpp, vesa_scanline);
}
#endif

/tags/0.2.0/kernel/arch/ia32/src/drivers/i8259.c
0,0 → 1,124
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/drivers/i8259.h>
#include <cpu.h>
#include <arch/types.h>
#include <arch/asm.h>
#include <arch.h>
#include <print.h>
#include <interrupt.h>
/*
* This is the PIC driver.
* Programmable Interrupt Controller for UP systems.
*/
static void pic_spurious(int n, istate_t *istate);
void i8259_init(void)
{
/* ICW1: this is ICW1, ICW4 to follow */
outb(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4);
/* ICW2: IRQ 0 maps to INT IRQBASE */
outb(PIC_PIC0PORT2, IVT_IRQBASE);
/* ICW3: pic1 using IRQ IRQ_PIC1 */
outb(PIC_PIC0PORT2, 1 << IRQ_PIC1);
/* ICW4: i8086 mode */
outb(PIC_PIC0PORT2, 1);
/* ICW1: ICW1, ICW4 to follow */
outb(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4);
/* ICW2: IRQ 8 maps to INT (IVT_IRQBASE + 8) */
outb(PIC_PIC1PORT2, IVT_IRQBASE + 8);
/* ICW3: pic1 is known as IRQ_PIC1 */
outb(PIC_PIC1PORT2, IRQ_PIC1);
/* ICW4: i8086 mode */
outb(PIC_PIC1PORT2, 1);
/*
* Register interrupt handler for the PIC spurious interrupt.
*/
exc_register(VECTOR_PIC_SPUR, "pic_spurious", (iroutine) pic_spurious);
/*
* Set the enable/disable IRQs handlers.
* Set the End-of-Interrupt handler.
*/
enable_irqs_function = pic_enable_irqs;
disable_irqs_function = pic_disable_irqs;
eoi_function = pic_eoi;
pic_disable_irqs(0xffff); /* disable all irq's */
pic_enable_irqs(1<<IRQ_PIC1); /* but enable pic1 */
}
void pic_enable_irqs(__u16 irqmask)
{
__u8 x;
if (irqmask & 0xff) {
x = inb(PIC_PIC0PORT2);
outb(PIC_PIC0PORT2, x & (~(irqmask & 0xff)));
}
if (irqmask >> 8) {
x = inb(PIC_PIC1PORT2);
outb(PIC_PIC1PORT2, x & (~(irqmask >> 8)));
}
}
void pic_disable_irqs(__u16 irqmask)
{
__u8 x;
if (irqmask & 0xff) {
x = inb(PIC_PIC0PORT2);
outb(PIC_PIC0PORT2, x | (irqmask & 0xff));
}
if (irqmask >> 8) {
x = inb(PIC_PIC1PORT2);
outb(PIC_PIC1PORT2, x | (irqmask >> 8));
}
}
void pic_eoi(void)
{
outb(0x20,0x20);
outb(0xa0,0x20);
}
void pic_spurious(int n, istate_t *istate)
{
printf("cpu%d: PIC spurious interrupt\n", CPU->id);
}

/tags/0.2.0/kernel/arch/ia32/src/drivers/i8254.c
0,0 → 1,132
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/types.h>
#include <time/clock.h>
#include <time/delay.h>
#include <arch/interrupt.h>
#include <arch/drivers/i8259.h>
#include <arch/drivers/i8254.h>
#include <cpu.h>
#include <config.h>
#include <arch/pm.h>
#include <arch/asm.h>
#include <arch/cpuid.h>
#include <arch.h>
#include <time/delay.h>
#include <interrupt.h>
/*
* i8254 chip driver.
* Low level time functions.
*/
#define CLK_PORT1 0x40
#define CLK_PORT4 0x43
#define CLK_CONST 1193180
#define MAGIC_NUMBER 1194
static void i8254_interrupt(int n, istate_t *istate);
void i8254_init(void)
{
i8254_normal_operation();
}
void i8254_normal_operation(void)
{
outb(CLK_PORT4, 0x36);
pic_disable_irqs(1<<IRQ_CLK);
outb(CLK_PORT1, (CLK_CONST/HZ) & 0xf);
outb(CLK_PORT1, (CLK_CONST/HZ) >> 8);
pic_enable_irqs(1<<IRQ_CLK);
exc_register(VECTOR_CLK, "i8254_clock", (iroutine) i8254_interrupt);
}
#define LOOPS 150000
#define SHIFT 11
void i8254_calibrate_delay_loop(void)
{
__u64 clk1, clk2;
__u32 t1, t2, o1, o2;
__u8 not_ok;
/*
* One-shot timer. Count-down from 0xffff at 1193180Hz
* MAGIC_NUMBER is the magic value for 1ms.
*/
outb(CLK_PORT4, 0x30);
outb(CLK_PORT1, 0xff);
outb(CLK_PORT1, 0xff);
do {
/* will read both status and count */
outb(CLK_PORT4, 0xc2);
not_ok = (inb(CLK_PORT1)>>6)&1;
t1 = inb(CLK_PORT1);
t1 |= inb(CLK_PORT1) << 8;
} while (not_ok);
asm_delay_loop(LOOPS);
outb(CLK_PORT4, 0xd2);
t2 = inb(CLK_PORT1);
t2 |= inb(CLK_PORT1) << 8;
/*
* We want to determine the overhead of the calibrating mechanism.
*/
outb(CLK_PORT4, 0xd2);
o1 = inb(CLK_PORT1);
o1 |= inb(CLK_PORT1) << 8;
asm_fake_loop(LOOPS);
outb(CLK_PORT4, 0xd2);
o2 = inb(CLK_PORT1);
o2 |= inb(CLK_PORT1) << 8;
CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) + (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0);
clk1 = rdtsc();
delay(1<<SHIFT);
clk2 = rdtsc();
CPU->frequency_mhz = (clk2-clk1)>>SHIFT;
return;
}
void i8254_interrupt(int n, istate_t *istate)
{
trap_virtual_eoi();
clock();
}

/tags/0.2.0/kernel/arch/ia32/src/drivers/ega.c
0,0 → 1,139
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/drivers/ega.h>
#include <putchar.h>
#include <mm/page.h>
#include <mm/as.h>
#include <arch/mm/page.h>
#include <synch/spinlock.h>
#include <arch/types.h>
#include <arch/asm.h>
#include <memstr.h>
#include <console/chardev.h>
#include <console/console.h>
#include <sysinfo/sysinfo.h>
/*
* The EGA driver.
* Simple and short. Function for displaying characters and "scrolling".
*/
SPINLOCK_INITIALIZE(egalock);
static __u32 ega_cursor;
static __u8 *videoram;
static void ega_putchar(chardev_t *d, const char ch);
chardev_t ega_console;
static chardev_operations_t ega_ops = {
.write = ega_putchar
};
void ega_move_cursor(void);
void ega_init(void)
{
__u8 hi, lo;
videoram = (__u8 *) hw_map(VIDEORAM, SCREEN * 2);
outb(0x3d4, 0xe);
hi = inb(0x3d5);
outb(0x3d4, 0xf);
lo = inb(0x3d5);
ega_cursor = (hi << 8) | lo;
chardev_initialize("ega_out", &ega_console, &ega_ops);
stdout = &ega_console;
sysinfo_set_item_val("fb", NULL, true);
sysinfo_set_item_val("fb.kind", NULL, 2);
sysinfo_set_item_val("fb.width", NULL, ROW);
sysinfo_set_item_val("fb.height", NULL, ROWS);
sysinfo_set_item_val("fb.address.physical", NULL, VIDEORAM);
#ifndef CONFIG_FB
putchar('\n');
#endif
}
static void ega_display_char(char ch)
{
videoram[ega_cursor * 2] = ch;
}
/*
* This function takes care of scrolling.
*/
static void ega_check_cursor(void)
{
if (ega_cursor < SCREEN)
return;
memcpy((void *) videoram, (void *) (videoram + ROW * 2), (SCREEN - ROW) * 2);
memsetw((__address) (videoram + (SCREEN - ROW) * 2), ROW, 0x0720);
ega_cursor = ega_cursor - ROW;
}
void ega_putchar(chardev_t *d, const char ch)
{
ipl_t ipl;
ipl = interrupts_disable();
spinlock_lock(&egalock);
switch (ch) {
case '\n':
ega_cursor = (ega_cursor + ROW) - ega_cursor % ROW;
break;
case '\t':
ega_cursor = (ega_cursor + 8) - ega_cursor % 8;
break;
case '\b':
if (ega_cursor % ROW)
ega_cursor--;
break;
default:
ega_display_char(ch);
ega_cursor++;
break;
}
ega_check_cursor();
ega_move_cursor();
spinlock_unlock(&egalock);
interrupts_restore(ipl);
}
void ega_move_cursor(void)
{
outb(0x3d4, 0xe);
outb(0x3d5, (ega_cursor >> 8) & 0xff);
outb(0x3d4, 0xf);
outb(0x3d5, ega_cursor & 0xff);
}

/tags/0.2.0/kernel/arch/ia32/src/pm.c
0,0 → 1,231
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/pm.h>
#include <config.h>
#include <arch/types.h>
#include <typedefs.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <arch/context.h>
#include <panic.h>
#include <arch/mm/page.h>
#include <mm/slab.h>
#include <memstr.h>
#include <arch/boot/boot.h>
#include <interrupt.h>
/*
* Early ia32 configuration functions and data structures.
*/
/*
* We have no use for segmentation so we set up flat mode. In this
* mode, we use, for each privilege level, two segments spanning the
* whole memory. One is for code and one is for data.
*
* One is for GS register which holds pointer to the TLS thread
* structure in it's base.
*/
descriptor_t gdt[GDT_ITEMS] = {
/* NULL descriptor */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
/* KTEXT descriptor */
{ 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
/* KDATA descriptor */
{ 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL, 0xf, 0, 0, 1, 1, 0 },
/* UTEXT descriptor */
{ 0xffff, 0, 0, AR_PRESENT | AR_CODE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
/* UDATA descriptor */
{ 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
/* TSS descriptor - set up will be completed later */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
/* TLS descriptor */
{ 0xffff, 0, 0, AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER, 0xf, 0, 0, 1, 1, 0 },
/* VESA Init descriptor */
#ifdef CONFIG_FB
{ 0xffff, 0, VESA_INIT_SEGMENT>>12, AR_PRESENT | AR_CODE | DPL_KERNEL, 0xf, 0, 0, 0, 0, 0 }
#endif
};
static idescriptor_t idt[IDT_ITEMS];
static tss_t tss;
tss_t *tss_p = NULL;
/* gdtr is changed by kmp before next CPU is initialized */
ptr_16_32_t bootstrap_gdtr = { .limit = sizeof(gdt), .base = KA2PA((__address) gdt) };
ptr_16_32_t gdtr = { .limit = sizeof(gdt), .base = (__address) gdt };
void gdt_setbase(descriptor_t *d, __address base)
{
d->base_0_15 = base & 0xffff;
d->base_16_23 = ((base) >> 16) & 0xff;
d->base_24_31 = ((base) >> 24) & 0xff;
}
void gdt_setlimit(descriptor_t *d, __u32 limit)
{
d->limit_0_15 = limit & 0xffff;
d->limit_16_19 = (limit >> 16) & 0xf;
}
void idt_setoffset(idescriptor_t *d, __address offset)
{
/*
* Offset is a linear address.
*/
d->offset_0_15 = offset & 0xffff;
d->offset_16_31 = offset >> 16;
}
void tss_initialize(tss_t *t)
{
memsetb((__address) t, sizeof(struct tss), 0);
}
/*
* This function takes care of proper setup of IDT and IDTR.
*/
void idt_init(void)
{
idescriptor_t *d;
int i;
for (i = 0; i < IDT_ITEMS; i++) {
d = &idt[i];
d->unused = 0;
d->selector = selector(KTEXT_DES);
d->access = AR_PRESENT | AR_INTERRUPT; /* masking interrupt */
if (i == VECTOR_SYSCALL) {
/*
* The syscall interrupt gate must be calleable from userland.
*/
d->access |= DPL_USER;
}
idt_setoffset(d, ((__address) interrupt_handlers) + i*interrupt_handler_size);
exc_register(i, "undef", (iroutine) null_interrupt);
}
exc_register(13, "gp_fault", (iroutine) gp_fault);
exc_register( 7, "nm_fault", (iroutine) nm_fault);
exc_register(12, "ss_fault", (iroutine) ss_fault);
exc_register(19, "simd_fp", (iroutine) simd_fp_exception);
}
/* Clean IOPL(12,13) and NT(14) flags in EFLAGS register */
static void clean_IOPL_NT_flags(void)
{
__asm__ volatile (
"pushfl\n"
"pop %%eax\n"
"and $0xffff8fff, %%eax\n"
"push %%eax\n"
"popfl\n"
: : : "eax"
);
}
/* Clean AM(18) flag in CR0 register */
static void clean_AM_flag(void)
{
__asm__ volatile (
"mov %%cr0, %%eax\n"
"and $0xfffbffff, %%eax\n"
"mov %%eax, %%cr0\n"
: : : "eax"
);
}
void pm_init(void)
{
descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
ptr_16_32_t idtr;
/*
* Update addresses in GDT and IDT to their virtual counterparts.
*/
idtr.limit = sizeof(idt);
idtr.base = (__address) idt;
gdtr_load(&gdtr);
idtr_load(&idtr);
/*
* Each CPU has its private GDT and TSS.
* All CPUs share one IDT.
*/
if (config.cpu_active == 1) {
idt_init();
/*
* NOTE: bootstrap CPU has statically allocated TSS, because
* the heap hasn't been initialized so far.
*/
tss_p = &tss;
}
else {
tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
if (!tss_p)
panic("could not allocate TSS\n");
}
tss_initialize(tss_p);
gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
gdt_p[TSS_DES].special = 1;
gdt_p[TSS_DES].granularity = 0;
gdt_setbase(&gdt_p[TSS_DES], (__address) tss_p);
gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
/*
* As of this moment, the current CPU has its own GDT pointing
* to its own TSS. We just need to load the TR register.
*/
tr_load(selector(TSS_DES));
clean_IOPL_NT_flags(); /* Disable I/O on nonprivileged levels and clear NT flag. */
clean_AM_flag(); /* Disable alignment check */
}
void set_tls_desc(__address tls)
{
ptr_16_32_t cpugdtr;
descriptor_t *gdt_p;
gdtr_store(&cpugdtr);
gdt_p = (descriptor_t *) cpugdtr.base;
gdt_setbase(&gdt_p[TLS_DES], tls);
/* Reload gdt register to update GS in CPU */
gdtr_load(&cpugdtr);
}

/tags/0.2.0/kernel/arch/ia32/src/asm.S
0,0 → 1,276
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
## very low and hardware-level functions
# Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word
# and 1 means interrupt with error word
#define ERROR_WORD_INTERRUPT_LIST 0x00027D00
.text
.global paging_on
.global enable_l_apic_in_msr
.global interrupt_handlers
.global memcpy
.global memcpy_from_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace
.global memcpy_to_uspace_failover_address
#define MEMCPY_DST 4
#define MEMCPY_SRC 8
#define MEMCPY_SIZE 12
/** Copy memory to/from userspace.
*
* This is almost conventional memcpy().
* The difference is that there is a failover part
* to where control is returned from a page fault
* if the page fault occurs during copy_from_uspace()
* or copy_to_uspace().
*
* @param MEMCPY_DST(%esp) Destination address.
* @param MEMCPY_SRC(%esp) Source address.
* @param MEMCPY_SIZE(%esp) Size.
*
* @return MEMCPY_SRC(%esp) on success and 0 on failure.
*/
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
movl %edi, %edx /* save %edi */
movl %esi, %eax /* save %esi */
movl MEMCPY_SIZE(%esp), %ecx
shrl $2, %ecx /* size / 4 */
movl MEMCPY_DST(%esp), %edi
movl MEMCPY_SRC(%esp), %esi
rep movsl /* copy as much as possible word by word */
movl MEMCPY_SIZE(%esp), %ecx
andl $3, %ecx /* size % 4 */
jz 0f
rep movsb /* copy the rest byte by byte */
0:
movl %edx, %edi
movl %eax, %esi
movl MEMCPY_SRC(%esp), %eax /* MEMCPY_SRC(%esp), success */
ret
/*
* We got here from as_page_fault() after the memory operations
* above had caused a page fault.
*/
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
movl %edx, %edi
movl %eax, %esi
xorl %eax, %eax /* return 0, failure */
ret
## Turn paging on
#
# Enable paging and write-back caching in CR0.
#
paging_on:
movl %cr0,%edx
orl $(1<<31),%edx # paging on
andl $~((1<<30)|(1<<29)),%edx # clear Cache Disable and not Write Though
movl %edx,%cr0
jmp 0f
0:
ret
## Enable local APIC
#
# Enable local APIC in MSR.
#
enable_l_apic_in_msr:
push %eax
movl $0x1b, %ecx
rdmsr
orl $(1<<11),%eax
orl $(0xfee00000),%eax
wrmsr
pop %eax
ret
# Clear nested flag
# overwrites %ecx
.macro CLEAR_NT_FLAG
pushfl
pop %ecx
and $0xffffbfff,%ecx
push %ecx
popfl
.endm
## Declare interrupt handlers
#
# Declare interrupt handlers for n interrupt
# vectors starting at vector i.
#
# The handlers setup data segment registers
# and call exc_dispatch().
#
#define INTERRUPT_ALIGN 64
.macro handler i n
.ifeq \i-0x30 # Syscall handler
push %ds
push %es
push %fs
push %gs
# Push arguments on stack
push %edi
push %esi
push %edx
push %ecx
push %eax
# we must fill the data segment registers
movw $16,%ax
movw %ax,%ds
movw %ax,%es
sti
call syscall_handler # syscall_handler(ax,cx,dx,si,di)
cli
addl $20, %esp # clean-up of parameters
pop %gs
pop %fs
pop %es
pop %ds
CLEAR_NT_FLAG
iret
.else
/*
* This macro distinguishes between two versions of ia32 exceptions.
* One version has error word and the other does not have it.
* The latter version fakes the error word on the stack so that the
* handlers and istate_t can be the same for both types.
*/
.iflt \i-32
.if (1 << \i) & ERROR_WORD_INTERRUPT_LIST
/*
* With error word, do nothing
*/
.else
/*
* Version without error word,
*/
subl $4, %esp
.endif
.else
/*
* Version without error word,
*/
subl $4, %esp
.endif
push %ds
push %es
push %fs
push %gs
#ifdef CONFIG_DEBUG_ALLREGS
push %ebx
push %ebp
push %edi
push %esi
#else
sub $16, %esp
#endif
push %edx
push %ecx
push %eax
# we must fill the data segment registers
movw $16,%ax
movw %ax,%ds
movw %ax,%es
pushl %esp # *istate
pushl $(\i) # intnum
call exc_dispatch # excdispatch(intnum, *istate)
addl $8,%esp # Clear arguments from stack
CLEAR_NT_FLAG # Modifies %ecx
pop %eax
pop %ecx
pop %edx
#ifdef CONFIG_DEBUG_ALLREGS
pop %esi
pop %edi
pop %ebp
pop %ebx
#else
add $16, %esp
#endif
pop %gs
pop %fs
pop %es
pop %ds
addl $4,%esp # Skip error word, no matter whether real or fake.
iret
.endif
.align INTERRUPT_ALIGN
.if (\n-\i)-1
handler "(\i+1)",\n
.endif
.endm
# keep in sync with pm.h !!!
IDT_ITEMS=64
.align INTERRUPT_ALIGN
interrupt_handlers:
h_start:
handler 0 IDT_ITEMS
h_end:
.data
.global interrupt_handler_size
interrupt_handler_size: .long (h_end-h_start)/IDT_ITEMS

/tags/0.2.0/kernel/arch/ia32/src/ddi/ddi.c
0,0 → 1,156
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <ddi/ddi.h>
#include <arch/ddi/ddi.h>
#include <proc/task.h>
#include <arch/types.h>
#include <typedefs.h>
#include <adt/bitmap.h>
#include <mm/slab.h>
#include <arch/pm.h>
#include <errno.h>
#include <arch/cpu.h>
#include <cpu.h>
#include <arch.h>
#include <align.h>
/** Enable I/O space range for task.
*
* Interrupts are disabled and task is locked.
*
* @param task Task.
* @param ioaddr Startign I/O space address.
* @param size Size of the enabled I/O range.
*
* @return 0 on success or an error code from errno.h.
*/
int ddi_iospace_enable_arch(task_t *task, __address ioaddr, size_t size)
{
count_t bits;
bits = ioaddr + size;
if (bits > IO_PORTS)
return ENOENT;
if (task->arch.iomap.bits < bits) {
bitmap_t oldiomap;
__u8 *newmap;
/*
* The I/O permission bitmap is too small and needs to be grown.
*/
newmap = (__u8 *) malloc(BITS2BYTES(bits), FRAME_ATOMIC);
if (!newmap)
return ENOMEM;
bitmap_initialize(&oldiomap, task->arch.iomap.map, task->arch.iomap.bits);
bitmap_initialize(&task->arch.iomap, newmap, bits);
/*
* Mark the new range inaccessible.
*/
bitmap_set_range(&task->arch.iomap, oldiomap.bits, bits - oldiomap.bits);
/*
* In case there really existed smaller iomap,
* copy its contents and deallocate it.
*/
if (oldiomap.bits) {
bitmap_copy(&task->arch.iomap, &oldiomap, oldiomap.bits);
free(oldiomap.map);
}
}
/*
* Enable the range and we are done.
*/
bitmap_clear_range(&task->arch.iomap, (index_t) ioaddr, (count_t) size);
/*
* Increment I/O Permission bitmap generation counter.
*/
task->arch.iomapver++;
return 0;
}
/** Install I/O Permission bitmap.
*
* Current task's I/O permission bitmap, if any, is installed
* in the current CPU's TSS.
*
* Interrupts must be disabled prior this call.
*/
void io_perm_bitmap_install(void)
{
count_t bits;
ptr_16_32_t cpugdtr;
descriptor_t *gdt_p;
count_t ver;
/* First, copy the I/O Permission Bitmap. */
spinlock_lock(&TASK->lock);
ver = TASK->arch.iomapver;
if ((bits = TASK->arch.iomap.bits)) {
bitmap_t iomap;
ASSERT(TASK->arch.iomap.map);
bitmap_initialize(&iomap, CPU->arch.tss->iomap, TSS_IOMAP_SIZE * 8);
bitmap_copy(&iomap, &TASK->arch.iomap, TASK->arch.iomap.bits);
/*
* It is safe to set the trailing eight bits because of the extra
* convenience byte in TSS_IOMAP_SIZE.
*/
bitmap_set_range(&iomap, ALIGN_UP(TASK->arch.iomap.bits, 8), 8);
}
spinlock_unlock(&TASK->lock);
/*
* Second, adjust TSS segment limit.
* Take the extra ending byte with all bits set into account.
*/
gdtr_store(&cpugdtr);
gdt_p = (descriptor_t *) cpugdtr.base;
gdt_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE + BITS2BYTES(bits));
gdtr_load(&cpugdtr);
/*
* Before we load new TSS limit, the current TSS descriptor
* type must be changed to describe inactive TSS.
*/
gdt_p[TSS_DES].access = AR_PRESENT | AR_TSS | DPL_KERNEL;
tr_load(selector(TSS_DES));
/*
* Update the generation count so that faults caused by
* early accesses can be serviced.
*/
CPU->arch.iomapver_copy = ver;
}

/tags/0.2.0/kernel/arch/ia32/src/cpu/cpu.c
0,0 → 1,157
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/cpu.h>
#include <arch/cpuid.h>
#include <arch/pm.h>
#include <arch.h>
#include <arch/types.h>
#include <print.h>
#include <typedefs.h>
#include <fpu_context.h>
#include <arch/smp/apic.h>
/*
* Identification of CPUs.
* Contains only non-MP-Specification specific SMP code.
*/
#define AMD_CPUID_EBX 0x68747541
#define AMD_CPUID_ECX 0x444d4163
#define AMD_CPUID_EDX 0x69746e65
#define INTEL_CPUID_EBX 0x756e6547
#define INTEL_CPUID_ECX 0x6c65746e
#define INTEL_CPUID_EDX 0x49656e69
enum vendor {
VendorUnknown=0,
VendorAMD,
VendorIntel
};
static char *vendor_str[] = {
"Unknown Vendor",
"AuthenticAMD",
"GenuineIntel"
};
void fpu_disable(void)
{
__asm__ volatile (
"mov %%cr0,%%eax;"
"or $8,%%eax;"
"mov %%eax,%%cr0;"
:
:
:"%eax"
);
}
void fpu_enable(void)
{
__asm__ volatile (
"mov %%cr0,%%eax;"
"and $0xffFFffF7,%%eax;"
"mov %%eax,%%cr0;"
:
:
:"%eax"
);
}
void cpu_arch_init(void)
{
cpuid_feature_info fi;
cpuid_extended_feature_info efi;
cpu_info_t info;
__u32 help = 0;
CPU->arch.tss = tss_p;
CPU->arch.tss->iomap_base = &CPU->arch.tss->iomap[0] - ((__u8 *) CPU->arch.tss);
CPU->fpu_owner = NULL;
cpuid(1, &info);
fi.word = info.cpuid_edx;
efi.word = info.cpuid_ecx;
if (fi.bits.fxsr)
fpu_fxsr();
else
fpu_fsr();
if (fi.bits.sse) {
asm volatile (
"mov %%cr4,%0\n"
"or %1,%0\n"
"mov %0,%%cr4\n"
: "+r" (help)
: "i" (CR4_OSFXSR_MASK|(1<<10))
);
}
}
void cpu_identify(void)
{
cpu_info_t info;
CPU->arch.vendor = VendorUnknown;
if (has_cpuid()) {
cpuid(0, &info);
/*
* Check for AMD processor.
*/
if (info.cpuid_ebx==AMD_CPUID_EBX && info.cpuid_ecx==AMD_CPUID_ECX && info.cpuid_edx==AMD_CPUID_EDX) {
CPU->arch.vendor = VendorAMD;
}
/*
* Check for Intel processor.
*/
if (info.cpuid_ebx==INTEL_CPUID_EBX && info.cpuid_ecx==INTEL_CPUID_ECX && info.cpuid_edx==INTEL_CPUID_EDX) {
CPU->arch.vendor = VendorIntel;
}
cpuid(1, &info);
CPU->arch.family = (info.cpuid_eax>>8)&0xf;
CPU->arch.model = (info.cpuid_eax>>4)&0xf;
CPU->arch.stepping = (info.cpuid_eax>>0)&0xf;
}
}
void cpu_print_report(cpu_t* m)
{
printf("cpu%d: (%s family=%d model=%d stepping=%d) %dMHz\n",
m->id, vendor_str[m->arch.vendor], m->arch.family, m->arch.model, m->arch.stepping,
m->frequency_mhz);
}

/tags/0.2.0/kernel/arch/ia32/src/userspace.c
0,0 → 1,78
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <userspace.h>
#include <arch/pm.h>
#include <arch/types.h>
#include <arch.h>
#include <proc/uarg.h>
#include <mm/as.h>
/** Enter userspace
*
* Change CPU protection level to 3, enter userspace.
*
*/
void userspace(uspace_arg_t *kernel_uarg)
{
ipl_t ipl;
ipl = interrupts_disable();
__asm__ volatile (
/*
* Clear nested task flag.
*/
"pushfl\n"
"pop %%eax\n"
"and $0xffffbfff, %%eax\n"
"push %%eax\n"
"popfl\n"
/* Set up GS register (TLS) */
"movl %6, %%gs\n"
"pushl %0\n"
"pushl %1\n"
"pushl %2\n"
"pushl %3\n"
"pushl %4\n"
"movl %5, %%eax\n"
"iret\n"
:
: "i" (selector(UDATA_DES) | PL_USER), "r" (kernel_uarg->uspace_stack+THREAD_STACK_SIZE),
"r" (ipl), "i" (selector(UTEXT_DES) | PL_USER), "r" (kernel_uarg->uspace_entry),
"r" (kernel_uarg->uspace_uarg),
"r" (selector(TLS_DES))
: "eax");
/* Unreachable */
for(;;)
;
}

/tags/0.2.0/kernel/arch/ia32/src/debugger.c
0,0 → 1,0
link ../../amd64/src/debugger.c
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/ia32/src/fpu_context.c
0,0 → 1,116
/*
* Copyright (C) 2005 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <fpu_context.h>
#include <arch.h>
#include <cpu.h>
typedef void (*fpu_context_function)(fpu_context_t *fctx);
static fpu_context_function fpu_save,fpu_restore;
static void fpu_context_f_save(fpu_context_t *fctx)
{
__asm__ volatile (
"fnsave %0"
: "=m"(*fctx)
);
}
static void fpu_context_f_restore(fpu_context_t *fctx)
{
__asm__ volatile (
"frstor %0"
: "=m"(*fctx)
);
}
static void fpu_context_fx_save(fpu_context_t *fctx)
{
__asm__ volatile (
"fxsave %0"
: "=m"(*fctx)
);
}
static void fpu_context_fx_restore(fpu_context_t *fctx)
{
__asm__ volatile (
"fxrstor %0"
: "=m"(*fctx)
);
}
/*
Setup using fxsr instruction
*/
void fpu_fxsr(void)
{
fpu_save=fpu_context_fx_save;
fpu_restore=fpu_context_fx_restore;
}
/*
Setup using not fxsr instruction
*/
void fpu_fsr(void)
{
fpu_save=fpu_context_f_save;
fpu_restore=fpu_context_f_restore;
}
void fpu_context_save(fpu_context_t *fctx)
{
fpu_save(fctx);
}
void fpu_context_restore(fpu_context_t *fctx)
{
fpu_restore(fctx);
}
void fpu_init()
{
__u32 help0=0,help1=0;
__asm__ volatile (
"fninit;\n"
"stmxcsr %0\n"
"mov %0,%1;\n"
"or %2,%1;\n"
"mov %1,%0;\n"
"ldmxcsr %0;\n"
:"+m"(help0),"+r"(help1)
:"i"(0x1f80)
);
}

/tags/0.2.0/kernel/arch/ia32/src/atomic.S
0,0 → 1,60
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
#ifdef CONFIG_SMP
.global spinlock_arch
#
# This is a bus-and-hyperthreading-friendly implementation of spinlock
#
spinlock_arch:
pushl %eax
pushl %ebx
movl 12(%esp),%ebx
0:
#ifdef CONFIG_HT
pause # Pentium 4's with HT love this instruction
#endif
movl (%ebx),%eax
testl %eax,%eax
jnz 0b # lightweight looping while it is locked
incl %eax
xchgl %eax,(%ebx) # now use the atomic operation
testl %eax,%eax
jnz 0b
popl %ebx
popl %eax
ret
#endif

/tags/0.2.0/kernel/arch/ia32/src/context.s
0,0 → 1,72
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
.global context_save_arch
.global context_restore_arch
## Save current CPU context
#
# Save CPU context to the context_t variable
# pointed by the 1st argument. Returns 1 in EAX.
#
context_save_arch:
movl 0(%esp),%eax # the caller's return %eip
movl 4(%esp),%edx # address of the kernel_context variable to save context to
movl %esp,0(%edx) # %esp -> ctx->sp
movl %eax,4(%edx) # %eip -> ctx->pc
movl %ebx,8(%edx) # %ebx -> ctx->ebx
movl %esi,12(%edx) # %esi -> ctx->esi
movl %edi,16(%edx) # %edi -> ctx->edi
movl %ebp,20(%edx) # %ebp -> ctx->ebp
xorl %eax,%eax # context_save returns 1
incl %eax
ret
## Restore saved CPU context
#
# Restore CPU context from context_t variable
# pointed by the 1st argument. Returns 0 in EAX.
#
context_restore_arch:
movl 4(%esp),%eax # address of the kernel_context variable to restore context from
movl 0(%eax),%esp # ctx->sp -> %esp
movl 4(%eax),%edx # ctx->pc -> %edx
movl 8(%eax),%ebx # ctx->ebx -> %ebx
movl 12(%eax),%esi # ctx->esi -> %esi
movl 16(%eax),%edi # ctx->edi -> %edi
movl 20(%eax),%ebp # ctx->ebp -> %ebp
movl %edx,0(%esp) # ctx->pc -> saver's return %eip
xorl %eax,%eax # context_restore returns 0
ret

/tags/0.2.0/kernel/arch/ia32/src/delay.s
0,0 → 1,50
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#
# Micro second delay loop functions.
#
.text
.global asm_delay_loop
.global asm_fake_loop
asm_delay_loop:
movl 4(%esp),%ecx # move argument to %ecx
0: lahf
dec %ecx
jnz 0b
ret
asm_fake_loop:
movl 4(%esp),%ecx # move argument to %ecx
0: lahf
dec %ecx
jz 0b
ret

/tags/0.2.0/kernel/arch/ia32/src/debug/panic.s
0,0 → 1,34
#
# Copyright (C) 2001-2004 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
.global panic_printf
panic_printf:
movl $halt,(%esp) # fake stack to make printf return to halt
jmp printf

/tags/0.2.0/kernel/arch/ia32/src/bios/bios.c
0,0 → 1,38
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/bios/bios.h>
#include <arch/types.h>
__address ebda = 0;
void bios_init(void)
{
/* Copy the EBDA address out from BIOS Data Area */
ebda = *((__u16 *) BIOS_EBDA_PTR) * 0x10;
}

/tags/0.2.0/kernel/arch/ia32/include/interrupt.h
0,0 → 1,119
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_INTERRUPT_H__
#define __ia32_INTERRUPT_H__
#include <arch/types.h>
#include <arch/pm.h>
#define IVT_ITEMS IDT_ITEMS
#define EXC_COUNT 32
#define IRQ_COUNT 16
#define IVT_EXCBASE 0
#define IVT_IRQBASE (IVT_EXCBASE+EXC_COUNT)
#define IVT_FREEBASE (IVT_IRQBASE+IRQ_COUNT)
#define IRQ_CLK 0
#define IRQ_KBD 1
#define IRQ_PIC1 2
#define IRQ_PIC_SPUR 7
/* this one must have four least significant bits set to ones */
#define VECTOR_APIC_SPUR (IVT_ITEMS-1)
#if (((VECTOR_APIC_SPUR + 1)%16) || VECTOR_APIC_SPUR >= IVT_ITEMS)
#error Wrong definition of VECTOR_APIC_SPUR
#endif
#define VECTOR_DEBUG 1
#define VECTOR_PIC_SPUR (IVT_IRQBASE+IRQ_PIC_SPUR)
#define VECTOR_CLK (IVT_IRQBASE+IRQ_CLK)
#define VECTOR_KBD (IVT_IRQBASE+IRQ_KBD)
#define VECTOR_SYSCALL (IVT_FREEBASE+0)
#define VECTOR_TLB_SHOOTDOWN_IPI (IVT_FREEBASE+1)
#define VECTOR_DEBUG_IPI (IVT_FREEBASE+2)
struct istate {
__u32 eax;
__u32 ecx;
__u32 edx;
__u32 esi;
__u32 edi;
__u32 ebp;
__u32 ebx;
__u32 gs;
__u32 fs;
__u32 es;
__u32 ds;
__u32 error_word;
__u32 eip;
__u32 cs;
__u32 eflags;
__u32 stack[];
};
/** Return true if exception happened while in userspace */
static inline int istate_from_uspace(istate_t *istate)
{
return !(istate->eip & 0x80000000);
}
static inline void istate_set_retaddr(istate_t *istate, __address retaddr)
{
istate->eip = retaddr;
}
static inline __native istate_get_pc(istate_t *istate)
{
return istate->eip;
}
extern void (* disable_irqs_function)(__u16 irqmask);
extern void (* enable_irqs_function)(__u16 irqmask);
extern void (* eoi_function)(void);
extern void PRINT_INFO_ERRCODE(istate_t *istate);
extern void null_interrupt(int n, istate_t *istate);
extern void gp_fault(int n, istate_t *istate);
extern void nm_fault(int n, istate_t *istate);
extern void ss_fault(int n, istate_t *istate);
extern void simd_fp_exception(int n, istate_t *istate);
extern void syscall(int n, istate_t *istate);
extern void tlb_shootdown_ipi(int n, istate_t *istate);
extern void trap_virtual_enable_irqs(__u16 irqmask);
extern void trap_virtual_disable_irqs(__u16 irqmask);
extern void trap_virtual_eoi(void);
#endif

/tags/0.2.0/kernel/arch/ia32/include/smp/mps.h
0,0 → 1,125
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MPS_H__
#define __MPS_H__
#include <arch/types.h>
#include <typedefs.h>
#include <synch/waitq.h>
#include <config.h>
#include <arch/smp/smp.h>
#define CT_EXT_ENTRY_TYPE 0
#define CT_EXT_ENTRY_LEN 1
struct mps_fs {
__u32 signature;
__u32 configuration_table;
__u8 length;
__u8 revision;
__u8 checksum;
__u8 config_type;
__u8 mpfib2;
__u8 mpfib3;
__u8 mpfib4;
__u8 mpfib5;
} __attribute__ ((packed));
struct mps_ct {
__u32 signature;
__u16 base_table_length;
__u8 revision;
__u8 checksum;
__u8 oem_id[8];
__u8 product_id[12];
__u32 oem_table;
__u16 oem_table_size;
__u16 entry_count;
__u32 l_apic;
__u16 ext_table_length;
__u8 ext_table_checksum;
__u8 xxx;
__u8 base_table[0];
} __attribute__ ((packed));
struct __processor_entry {
__u8 type;
__u8 l_apic_id;
__u8 l_apic_version;
__u8 cpu_flags;
__u8 cpu_signature[4];
__u32 feature_flags;
__u32 xxx[2];
} __attribute__ ((packed));
struct __bus_entry {
__u8 type;
__u8 bus_id;
__u8 bus_type[6];
} __attribute__ ((packed));
struct __io_apic_entry {
__u8 type;
__u8 io_apic_id;
__u8 io_apic_version;
__u8 io_apic_flags;
__u32 io_apic;
} __attribute__ ((packed));
struct __io_intr_entry {
__u8 type;
__u8 intr_type;
__u8 poel;
__u8 xxx;
__u8 src_bus_id;
__u8 src_bus_irq;
__u8 dst_io_apic_id;
__u8 dst_io_apic_pin;
} __attribute__ ((packed));
struct __l_intr_entry {
__u8 type;
__u8 intr_type;
__u8 poel;
__u8 xxx;
__u8 src_bus_id;
__u8 src_bus_irq;
__u8 dst_l_apic_id;
__u8 dst_l_apic_pin;
} __attribute__ ((packed));
extern waitq_t ap_completion_wq;
extern struct smp_config_operations mps_config_operations;
extern void mps_init(void);
extern void kmp(void *arg);
#endif

/tags/0.2.0/kernel/arch/ia32/include/smp/apic.h
0,0 → 1,361
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __APIC_H__
#define __APIC_H__
#include <arch/types.h>
#include <cpu.h>
#define FIXED (0<<0)
#define LOPRI (1<<0)
#define APIC_ID_COUNT 16
/* local APIC macros */
#define IPI_INIT 0
#define IPI_STARTUP 0
/** Delivery modes. */
#define DELMOD_FIXED 0x0
#define DELMOD_LOWPRI 0x1
#define DELMOD_SMI 0x2
/* 0x3 reserved */
#define DELMOD_NMI 0x4
#define DELMOD_INIT 0x5
#define DELMOD_STARTUP 0x6
#define DELMOD_EXTINT 0x7
/** Destination modes. */
#define DESTMOD_PHYS 0x0
#define DESTMOD_LOGIC 0x1
/** Trigger Modes. */
#define TRIGMOD_EDGE 0x0
#define TRIGMOD_LEVEL 0x1
/** Levels. */
#define LEVEL_DEASSERT 0x0
#define LEVEL_ASSERT 0x1
/** Destination Shorthands. */
#define SHORTHAND_NONE 0x0
#define SHORTHAND_SELF 0x1
#define SHORTHAND_ALL_INCL 0x2
#define SHORTHAND_ALL_EXCL 0x3
/** Interrupt Input Pin Polarities. */
#define POLARITY_HIGH 0x0
#define POLARITY_LOW 0x1
/** Divide Values. (Bit 2 is always 0) */
#define DIVIDE_2 0x0
#define DIVIDE_4 0x1
#define DIVIDE_8 0x2
#define DIVIDE_16 0x3
#define DIVIDE_32 0x8
#define DIVIDE_64 0x9
#define DIVIDE_128 0xa
#define DIVIDE_1 0xb
/** Timer Modes. */
#define TIMER_ONESHOT 0x0
#define TIMER_PERIODIC 0x1
/** Delivery status. */
#define DELIVS_IDLE 0x0
#define DELIVS_PENDING 0x1
/** Destination masks. */
#define DEST_ALL 0xff
/** Dest format models. */
#define MODEL_FLAT 0xf
#define MODEL_CLUSTER 0x0
/** Interrupt Command Register. */
#define ICRlo (0x300/sizeof(__u32))
#define ICRhi (0x310/sizeof(__u32))
struct icr {
union {
__u32 lo;
struct {
__u8 vector; /**< Interrupt Vector. */
unsigned delmod : 3; /**< Delivery Mode. */
unsigned destmod : 1; /**< Destination Mode. */
unsigned delivs : 1; /**< Delivery status (RO). */
unsigned : 1; /**< Reserved. */
unsigned level : 1; /**< Level. */
unsigned trigger_mode : 1; /**< Trigger Mode. */
unsigned : 2; /**< Reserved. */
unsigned shorthand : 2; /**< Destination Shorthand. */
unsigned : 12; /**< Reserved. */
} __attribute__ ((packed));
};
union {
__u32 hi;
struct {
unsigned : 24; /**< Reserved. */
__u8 dest; /**< Destination field. */
} __attribute__ ((packed));
};
} __attribute__ ((packed));
typedef struct icr icr_t;
/* End Of Interrupt. */
#define EOI (0x0b0/sizeof(__u32))
/** Error Status Register. */
#define ESR (0x280/sizeof(__u32))
union esr {
__u32 value;
__u8 err_bitmap;
struct {
unsigned send_checksum_error : 1;
unsigned receive_checksum_error : 1;
unsigned send_accept_error : 1;
unsigned receive_accept_error : 1;
unsigned : 1;
unsigned send_illegal_vector : 1;
unsigned received_illegal_vector : 1;
unsigned illegal_register_address : 1;
unsigned : 24;
} __attribute__ ((packed));
};
typedef union esr esr_t;
/* Task Priority Register */
#define TPR (0x080/sizeof(__u32))
union tpr {
__u32 value;
struct {
unsigned pri_sc : 4; /**< Task Priority Sub-Class. */
unsigned pri : 4; /**< Task Priority. */
} __attribute__ ((packed));
};
typedef union tpr tpr_t;
/** Spurious-Interrupt Vector Register. */
#define SVR (0x0f0/sizeof(__u32))
union svr {
__u32 value;
struct {
__u8 vector; /**< Spurious Vector. */
unsigned lapic_enabled : 1; /**< APIC Software Enable/Disable. */
unsigned focus_checking : 1; /**< Focus Processor Checking. */
unsigned : 22; /**< Reserved. */
} __attribute__ ((packed));
};
typedef union svr svr_t;
/** Time Divide Configuration Register. */
#define TDCR (0x3e0/sizeof(__u32))
union tdcr {
__u32 value;
struct {
unsigned div_value : 4; /**< Divide Value, bit 2 is always 0. */
unsigned : 28; /**< Reserved. */
} __attribute__ ((packed));
};
typedef union tdcr tdcr_t;
/* Initial Count Register for Timer */
#define ICRT (0x380/sizeof(__u32))
/* Current Count Register for Timer */
#define CCRT (0x390/sizeof(__u32))
/** LVT Timer register. */
#define LVT_Tm (0x320/sizeof(__u32))
union lvt_tm {
__u32 value;
struct {
__u8 vector; /**< Local Timer Interrupt vector. */
unsigned : 4; /**< Reserved. */
unsigned delivs : 1; /**< Delivery status (RO). */
unsigned : 3; /**< Reserved. */
unsigned masked : 1; /**< Interrupt Mask. */
unsigned mode : 1; /**< Timer Mode. */
unsigned : 14; /**< Reserved. */
} __attribute__ ((packed));
};
typedef union lvt_tm lvt_tm_t;
/** LVT LINT registers. */
#define LVT_LINT0 (0x350/sizeof(__u32))
#define LVT_LINT1 (0x360/sizeof(__u32))
union lvt_lint {
__u32 value;
struct {
__u8 vector; /**< LINT Interrupt vector. */
unsigned delmod : 3; /**< Delivery Mode. */
unsigned : 1; /**< Reserved. */
unsigned delivs : 1; /**< Delivery status (RO). */
unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */
unsigned irr : 1; /**< Remote IRR (RO). */
unsigned trigger_mode : 1; /**< Trigger Mode. */
unsigned masked : 1; /**< Interrupt Mask. */
unsigned : 15; /**< Reserved. */
} __attribute__ ((packed));
};
typedef union lvt_lint lvt_lint_t;
/** LVT Error register. */
#define LVT_Err (0x370/sizeof(__u32))
union lvt_error {
__u32 value;
struct {
__u8 vector; /**< Local Timer Interrupt vector. */
unsigned : 4; /**< Reserved. */
unsigned delivs : 1; /**< Delivery status (RO). */
unsigned : 3; /**< Reserved. */
unsigned masked : 1; /**< Interrupt Mask. */
unsigned : 15; /**< Reserved. */
} __attribute__ ((packed));
};
typedef union lvt_error lvt_error_t;
/** Local APIC ID Register. */
#define L_APIC_ID (0x020/sizeof(__u32))
union l_apic_id {
__u32 value;
struct {
unsigned : 24; /**< Reserved. */
__u8 apic_id; /**< Local APIC ID. */
} __attribute__ ((packed));
};
typedef union l_apic_id l_apic_id_t;
/** Local APIC Version Register */
#define LAVR (0x030/sizeof(__u32))
#define LAVR_Mask 0xff
#define is_local_apic(x) (((x)&LAVR_Mask&0xf0)==0x1)
#define is_82489DX_apic(x) ((((x)&LAVR_Mask&0xf0)==0x0))
#define is_local_xapic(x) (((x)&LAVR_Mask)==0x14)
/** Logical Destination Register. */
#define LDR (0x0d0/sizeof(__u32))
union ldr {
__u32 value;
struct {
unsigned : 24; /**< Reserved. */
__u8 id; /**< Logical APIC ID. */
} __attribute__ ((packed));
};
typedef union ldr ldr_t;
/** Destination Format Register. */
#define DFR (0x0e0/sizeof(__u32))
union dfr {
__u32 value;
struct {
unsigned : 28; /**< Reserved, all ones. */
unsigned model : 4; /**< Model. */
} __attribute__ ((packed));
};
typedef union dfr dfr_t;
/* IO APIC */
#define IOREGSEL (0x00/sizeof(__u32))
#define IOWIN (0x10/sizeof(__u32))
#define IOAPICID 0x00
#define IOAPICVER 0x01
#define IOAPICARB 0x02
#define IOREDTBL 0x10
/** I/O Register Select Register. */
union io_regsel {
__u32 value;
struct {
__u8 reg_addr; /**< APIC Register Address. */
unsigned : 24; /**< Reserved. */
} __attribute__ ((packed));
};
typedef union io_regsel io_regsel_t;
/** I/O Redirection Register. */
struct io_redirection_reg {
union {
__u32 lo;
struct {
__u8 intvec; /**< Interrupt Vector. */
unsigned delmod : 3; /**< Delivery Mode. */
unsigned destmod : 1; /**< Destination mode. */
unsigned delivs : 1; /**< Delivery status (RO). */
unsigned intpol : 1; /**< Interrupt Input Pin Polarity. */
unsigned irr : 1; /**< Remote IRR (RO). */
unsigned trigger_mode : 1; /**< Trigger Mode. */
unsigned masked : 1; /**< Interrupt Mask. */
unsigned : 15; /**< Reserved. */
} __attribute__ ((packed));
};
union {
__u32 hi;
struct {
unsigned : 24; /**< Reserved. */
__u8 dest : 8; /**< Destination Field. */
} __attribute__ ((packed));
};
} __attribute__ ((packed));
typedef struct io_redirection_reg io_redirection_reg_t;
/** IO APIC Identification Register. */
union io_apic_id {
__u32 value;
struct {
unsigned : 24; /**< Reserved. */
unsigned apic_id : 4; /**< IO APIC ID. */
unsigned : 4; /**< Reserved. */
} __attribute__ ((packed));
};
typedef union io_apic_id io_apic_id_t;
extern volatile __u32 *l_apic;
extern volatile __u32 *io_apic;
extern __u32 apic_id_mask;
extern void apic_init(void);
extern void l_apic_init(void);
extern void l_apic_eoi(void);
extern int l_apic_broadcast_custom_ipi(__u8 vector);
extern int l_apic_send_init_ipi(__u8 apicid);
extern void l_apic_debug(void);
extern __u8 l_apic_id(void);
extern __u32 io_apic_read(__u8 address);
extern void io_apic_write(__u8 address , __u32 x);
extern void io_apic_change_ioredtbl(int pin, int dest, __u8 v, int flags);
extern void io_apic_disable_irqs(__u16 irqmask);
extern void io_apic_enable_irqs(__u16 irqmask);
#endif

/tags/0.2.0/kernel/arch/ia32/include/smp/smp.h
0,0 → 1,46
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_SMP_H__
#define __ia32_SMP_H__
#include <arch/types.h>
#include <typedefs.h>
/** SMP config opertaions interface. */
struct smp_config_operations {
count_t (* cpu_count)(void); /**< Return number of detected processors. */
bool (* cpu_enabled)(index_t i); /**< Check whether the processor of index i is enabled. */
bool (*cpu_bootstrap)(index_t i); /**< Check whether the processor of index i is BSP. */
__u8 (*cpu_apic_id)(index_t i); /**< Return APIC ID of the processor of index i. */
int (*irq_to_pin)(int irq); /**< Return mapping between irq and APIC pin. */
};
extern int smp_irq_to_pin(int irq);
#endif

/tags/0.2.0/kernel/arch/ia32/include/smp/ap.h
0,0 → 1,34
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __AP_H__
#define __AP_H__
extern void ap_boot(void);
#endif

/tags/0.2.0/kernel/arch/ia32/include/mm/as.h
0,0 → 1,45
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_AS_H__
#define __ia32_AS_H__
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0
#define KERNEL_ADDRESS_SPACE_START_ARCH ((unsigned long) 0x80000000)
#define KERNEL_ADDRESS_SPACE_END_ARCH ((unsigned long) 0xffffffff)
#define USER_ADDRESS_SPACE_START_ARCH ((unsigned long) 0x00000000)
#define USER_ADDRESS_SPACE_END_ARCH ((unsigned long) 0x7fffffff)
#define USTACK_ADDRESS_ARCH (USER_ADDRESS_SPACE_END_ARCH-(PAGE_SIZE-1))
#define as_install_arch(as)
extern void as_arch_init(void);
#endif

/tags/0.2.0/kernel/arch/ia32/include/mm/asid.h
0,0 → 1,45
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* ia32 has no hardware support for address space identifiers.
* This file is provided to do nop-implementation of mm/asid.h
* interface.
*/
#ifndef __ia32_ASID_H__
#define __ia32_ASID_H__
typedef int asid_t;
#define ASID_MAX_ARCH 3
#define asid_get() (ASID_START+1)
#define asid_put(asid)
#endif

/tags/0.2.0/kernel/arch/ia32/include/mm/page.h
0,0 → 1,163
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_PAGE_H__
#define __ia32_PAGE_H__
#include <arch/mm/frame.h>
#define PAGE_WIDTH FRAME_WIDTH
#define PAGE_SIZE FRAME_SIZE
#ifdef KERNEL
#ifndef __ASM__
# define KA2PA(x) (((__address) (x)) - 0x80000000)
# define PA2KA(x) (((__address) (x)) + 0x80000000)
#else
# define KA2PA(x) ((x) - 0x80000000)
# define PA2KA(x) ((x) + 0x80000000)
#endif
/*
* Implementation of generic 4-level page table interface.
* IA-32 has 2-level page tables, so PTL1 and PTL2 are left out.
*/
#define PTL0_ENTRIES_ARCH 1024
#define PTL1_ENTRIES_ARCH 0
#define PTL2_ENTRIES_ARCH 0
#define PTL3_ENTRIES_ARCH 1024
#define PTL0_INDEX_ARCH(vaddr) (((vaddr)>>22)&0x3ff)
#define PTL1_INDEX_ARCH(vaddr) 0
#define PTL2_INDEX_ARCH(vaddr) 0
#define PTL3_INDEX_ARCH(vaddr) (((vaddr)>>12)&0x3ff)
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)((((pte_t *)(ptl0))[(i)].frame_address)<<12))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((__address)((((pte_t *)(ptl3))[(i)].frame_address)<<12))
#define SET_PTL0_ADDRESS_ARCH(ptl0) (write_cr3((__address) (ptl0)))
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *)(ptl0))[(i)].frame_address = (a)>>12)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *)(ptl3))[(i)].frame_address = (a)>>12)
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *)(ptl3), (index_t)(i))
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *)(ptl0), (index_t)(i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *)(ptl3), (index_t)(i), (x))
#define PTE_VALID_ARCH(p) (*((__u32 *) (p)) != 0)
#define PTE_PRESENT_ARCH(p) ((p)->present != 0)
#define PTE_GET_FRAME_ARCH(p) ((p)->frame_address<<FRAME_WIDTH)
#define PTE_WRITABLE_ARCH(p) ((p)->writeable != 0)
#define PTE_EXECUTABLE_ARCH(p) 1
#ifndef __ASM__
#include <mm/page.h>
#include <arch/types.h>
#include <arch/mm/frame.h>
#include <typedefs.h>
/* Page fault error codes. */
/** When bit on this position is 0, the page fault was caused by a not-present page. */
#define PFERR_CODE_P (1<<0)
/** When bit on this position is 1, the page fault was caused by a write. */
#define PFERR_CODE_RW (1<<1)
/** When bit on this position is 1, the page fault was caused in user mode. */
#define PFERR_CODE_US (1<<2)
/** When bit on this position is 1, a reserved bit was set in page directory. */
#define PFERR_CODE_RSVD (1<<3)
/** Page Table Entry. */
struct page_specifier {
unsigned present : 1;
unsigned writeable : 1;
unsigned uaccessible : 1;
unsigned page_write_through : 1;
unsigned page_cache_disable : 1;
unsigned accessed : 1;
unsigned dirty : 1;
unsigned pat : 1;
unsigned global : 1;
unsigned soft_valid : 1; /**< Valid content even if the present bit is not set. */
unsigned avl : 2;
unsigned frame_address : 20;
} __attribute__ ((packed));
static inline int get_pt_flags(pte_t *pt, index_t i)
{
pte_t *p = &pt[i];
return (
(!p->page_cache_disable)<<PAGE_CACHEABLE_SHIFT |
(!p->present)<<PAGE_PRESENT_SHIFT |
p->uaccessible<<PAGE_USER_SHIFT |
1<<PAGE_READ_SHIFT |
p->writeable<<PAGE_WRITE_SHIFT |
1<<PAGE_EXEC_SHIFT |
p->global<<PAGE_GLOBAL_SHIFT
);
}
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
{
pte_t *p = &pt[i];
p->page_cache_disable = !(flags & PAGE_CACHEABLE);
p->present = !(flags & PAGE_NOT_PRESENT);
p->uaccessible = (flags & PAGE_USER) != 0;
p->writeable = (flags & PAGE_WRITE) != 0;
p->global = (flags & PAGE_GLOBAL) != 0;
/*
* Ensure that there is at least one bit set even if the present bit is cleared.
*/
p->soft_valid = true;
}
extern void page_arch_init(void);
extern void page_fault(int n, istate_t *istate);
#endif /* __ASM__ */
#endif /* KERNEL */
#endif

/tags/0.2.0/kernel/arch/ia32/include/mm/frame.h
0,0 → 1,48
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_FRAME_H__
#define __ia32_FRAME_H__
#define FRAME_WIDTH 12 /* 4K */
#define FRAME_SIZE (1<<FRAME_WIDTH)
#ifdef KERNEL
#ifndef __ASM__
#include <arch/types.h>
extern __address last_frame;
extern void frame_arch_init(void);
#endif /* __ASM__ */
#endif /* KERNEL */
#endif

/tags/0.2.0/kernel/arch/ia32/include/mm/tlb.h
0,0 → 1,35
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_TLB_H__
#define __ia32_TLB_H__
#define tlb_arch_init()
#define tlb_print()
#endif

/tags/0.2.0/kernel/arch/ia32/include/mm/memory_init.h
0,0 → 1,38
/*
* Copyright (C) 2005 Josef Cejka
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_MEMORY_INIT_H__
#define __ia32_MEMORY_INIT_H__
#include <typedefs.h>
size_t get_memory_size(void);
void memory_print_map(void);
#endif

/tags/0.2.0/kernel/arch/ia32/include/drivers/i8254.h
0,0 → 1,38
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __I8254_H__
#define __I8254_H__
#include <arch/types.h>
extern void i8254_init(void);
extern void i8254_calibrate_delay_loop(void);
extern void i8254_normal_operation(void);
#endif

/tags/0.2.0/kernel/arch/ia32/include/drivers/vesa.h
0,0 → 1,35
/*
* Copyright (C) 2006 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __VESA_H__
#define __VESA_H__
extern int vesa_present(void);
extern void vesa_init(void);
#endif

/tags/0.2.0/kernel/arch/ia32/include/drivers/i8259.h
0,0 → 1,48
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __I8259_H__
#define __I8259_H__
#include <arch/types.h>
#include <arch/interrupt.h>
#define PIC_PIC0PORT1 0x20
#define PIC_PIC0PORT2 0x21
#define PIC_PIC1PORT1 0xa0
#define PIC_PIC1PORT2 0xa1
#define PIC_NEEDICW4 (1<<0)
#define PIC_ICW1 (1<<4)
extern void i8259_init(void);
extern void pic_enable_irqs(__u16 irqmask);
extern void pic_disable_irqs(__u16 irqmask);
extern void pic_eoi(void);
#endif

/tags/0.2.0/kernel/arch/ia32/include/drivers/ega.h
0,0 → 1,39
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __EGA_H__
#define __EGA_H__
#define VIDEORAM 0xb8000
#define ROW 80
#define ROWS 25
#define SCREEN (ROW * ROWS)
extern void ega_init(void);
#endif

/tags/0.2.0/kernel/arch/ia32/include/drivers/i8042.h
0,0 → 1,62
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* This file implements ia32 specific access to i8042 registers.
*/
#ifndef __ia32_I8042_H__
#define __ia32_I8042_H__
#include <arch/asm.h>
#include <arch/types.h>
#define i8042_DATA 0x60
#define i8042_STATUS 0x64
static inline void i8042_data_write(__u8 data)
{
outb(i8042_DATA, data);
}
static inline __u8 i8042_data_read(void)
{
return inb(i8042_DATA);
}
static inline __u8 i8042_status_read(void)
{
return inb(i8042_STATUS);
}
static inline void i8042_command_write(__u8 command)
{
outb(i8042_STATUS, command);
}
#endif

/tags/0.2.0/kernel/arch/ia32/include/barrier.h
0,0 → 1,81
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_BARRIER_H__
#define __ia32_BARRIER_H__
/*
* NOTE:
* No barriers for critical section (i.e. spinlock) on IA-32 are needed:
* - spinlock_lock() and spinlock_trylock() use serializing XCHG instruction
* - writes cannot pass reads on IA-32 => spinlock_unlock() needs no barriers
*/
/*
* Provisions are made to prevent compiler from reordering instructions itself.
*/
#define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory")
#define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory")
static inline void cpuid_serialization(void)
{
__asm__ volatile (
"xorl %%eax, %%eax\n"
"cpuid\n"
::: "eax", "ebx", "ecx", "edx", "memory"
);
}
#ifdef CONFIG_FENCES_P4
# define memory_barrier() __asm__ volatile ("mfence\n" ::: "memory")
# define read_barrier() __asm__ volatile ("lfence\n" ::: "memory")
# ifdef CONFIG_WEAK_MEMORY
# define write_barrier() __asm__ volatile ("sfence\n" ::: "memory")
# else
# define write_barrier() __asm__ volatile( "" ::: "memory");
# endif
#elif CONFIG_FENCES_P3
# define memory_barrier() cpuid_serialization()
# define read_barrier() cpuid_serialization()
# ifdef CONFIG_WEAK_MEMORY
# define write_barrier() __asm__ volatile ("sfence\n" ::: "memory")
# else
# define write_barrier() __asm__ volatile( "" ::: "memory");
# endif
#else
# define memory_barrier() cpuid_serialization()
# define read_barrier() cpuid_serialization()
# ifdef CONFIG_WEAK_MEMORY
# define write_barrier() cpuid_serialization()
# else
# define write_barrier() __asm__ volatile( "" ::: "memory");
# endif
#endif
#endif

/tags/0.2.0/kernel/arch/ia32/include/pm.h
0,0 → 1,173
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PM_H__
#define __PM_H__
#define IDT_ITEMS 64
#define GDT_ITEMS 7
#define VESA_INIT_SEGMENT 0x8000
#define NULL_DES 0
#define KTEXT_DES 1
#define KDATA_DES 2
#define UTEXT_DES 3
#define UDATA_DES 4
#define TSS_DES 5
#define TLS_DES 6 /* Pointer to Thread-Local-Storage data */
#ifdef CONFIG_FB
#define VESA_INIT_SEGMENT 0x8000
#define VESA_INIT_DES 7
#undef GDT_ITEMS
#define GDT_ITEMS 8
#endif /* CONFIG_FB */
#define selector(des) ((des)<<3)
#define PL_KERNEL 0
#define PL_USER 3
#define AR_PRESENT (1<<7)
#define AR_DATA (2<<3)
#define AR_CODE (3<<3)
#define AR_WRITABLE (1<<1)
#define AR_INTERRUPT (0xe)
#define AR_TSS (0x9)
#define DPL_KERNEL (PL_KERNEL<<5)
#define DPL_USER (PL_USER<<5)
#define TSS_BASIC_SIZE 104
#define TSS_IOMAP_SIZE (16*1024+1) /* 16K for bitmap + 1 terminating byte for convenience */
#define IO_PORTS (64*1024)
#ifndef __ASM__
#include <arch/types.h>
#include <typedefs.h>
#include <arch/context.h>
struct ptr_16_32 {
__u16 limit;
__u32 base;
} __attribute__ ((packed));
typedef struct ptr_16_32 ptr_16_32_t;
struct descriptor {
unsigned limit_0_15: 16;
unsigned base_0_15: 16;
unsigned base_16_23: 8;
unsigned access: 8;
unsigned limit_16_19: 4;
unsigned available: 1;
unsigned unused: 1;
unsigned special: 1;
unsigned granularity : 1;
unsigned base_24_31: 8;
} __attribute__ ((packed));
typedef struct descriptor descriptor_t;
struct idescriptor {
unsigned offset_0_15: 16;
unsigned selector: 16;
unsigned unused: 8;
unsigned access: 8;
unsigned offset_16_31: 16;
} __attribute__ ((packed));
typedef struct idescriptor idescriptor_t;
struct tss {
__u16 link;
unsigned : 16;
__u32 esp0;
__u16 ss0;
unsigned : 16;
__u32 esp1;
__u16 ss1;
unsigned : 16;
__u32 esp2;
__u16 ss2;
unsigned : 16;
__u32 cr3;
__u32 eip;
__u32 eflags;
__u32 eax;
__u32 ecx;
__u32 edx;
__u32 ebx;
__u32 esp;
__u32 ebp;
__u32 esi;
__u32 edi;
__u16 es;
unsigned : 16;
__u16 cs;
unsigned : 16;
__u16 ss;
unsigned : 16;
__u16 ds;
unsigned : 16;
__u16 fs;
unsigned : 16;
__u16 gs;
unsigned : 16;
__u16 ldtr;
unsigned : 16;
unsigned : 16;
__u16 iomap_base;
__u8 iomap[TSS_IOMAP_SIZE];
} __attribute__ ((packed));
typedef struct tss tss_t;
extern ptr_16_32_t gdtr;
extern ptr_16_32_t bootstrap_gdtr;
extern ptr_16_32_t protected_ap_gdtr;
extern struct tss *tss_p;
extern descriptor_t gdt[];
extern void pm_init(void);
extern void gdt_setbase(descriptor_t *d, __address base);
extern void gdt_setlimit(descriptor_t *d, __u32 limit);
extern void idt_init(void);
extern void idt_setoffset(idescriptor_t *d, __address offset);
extern void tss_initialize(tss_t *t);
extern void set_tls_desc(__address tls);
#endif /* __ASM__ */
#endif

/tags/0.2.0/kernel/arch/ia32/include/ddi/ddi.h
0,0 → 1,39
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file ddi.h
* @brief ia32 specific DDI declarations and macros.
*/
#ifndef __ia32_DDI_H__
#define __ia32_DDI_H__
extern void io_perm_bitmap_install(void);
#endif

/tags/0.2.0/kernel/arch/ia32/include/proc/task.h
0,0 → 1,41
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_TASK_H__
#define __ia32_TASK_H__
#include <typedefs.h>
#include <arch/types.h>
#include <adt/bitmap.h>
typedef struct {
count_t iomapver; /**< I/O Permission bitmap Generation counter. */
bitmap_t iomap; /**< I/O Permission bitmap. */
} task_arch_t;
#endif

/tags/0.2.0/kernel/arch/ia32/include/proc/thread.h
0,0 → 1,38
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_THREAD_H__
#define __ia32_THREAD_H__
#include <arch/types.h>
typedef struct {
__native tls;
} thread_arch_t;
#endif

/tags/0.2.0/kernel/arch/ia32/include/cpu.h
0,0 → 1,52
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_CPU_H__
#define __ia32_CPU_H__
#include <typedefs.h>
#include <arch/pm.h>
#include <arch/asm.h>
#define EFLAGS_IF (1 << 9)
#define EFLAGS_RF (1 << 16)
struct cpu_arch {
int vendor;
int family;
int model;
int stepping;
struct tss *tss;
count_t iomapver_copy; /** Copy of TASK's I/O Permission bitmap generation count. */
};
#define CR4_OSFXSR_MASK (1<<9)
#endif

/tags/0.2.0/kernel/arch/ia32/include/asm.h
0,0 → 1,291
/*
* Copyright (C) 2001-2004 Jakub Jermar
* Copyright (C) 2005 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_ASM_H__
#define __ia32_ASM_H__
#include <arch/pm.h>
#include <arch/types.h>
#include <config.h>
extern __u32 interrupt_handler_size;
extern void paging_on(void);
extern void interrupt_handlers(void);
extern void enable_l_apic_in_msr(void);
extern void asm_delay_loop(__u32 t);
extern void asm_fake_loop(__u32 t);
/** Halt CPU
*
* Halt the current CPU until interrupt event.
*/
static inline void cpu_halt(void) { __asm__("hlt\n"); };
static inline void cpu_sleep(void) { __asm__("hlt\n"); };
#define GEN_READ_REG(reg) static inline __native read_ ##reg (void) \
{ \
__native res; \
__asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \
return res; \
}
#define GEN_WRITE_REG(reg) static inline void write_ ##reg (__native regn) \
{ \
__asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \
}
GEN_READ_REG(cr0);
GEN_READ_REG(cr2);
GEN_READ_REG(cr3);
GEN_WRITE_REG(cr3);
GEN_READ_REG(dr0);
GEN_READ_REG(dr1);
GEN_READ_REG(dr2);
GEN_READ_REG(dr3);
GEN_READ_REG(dr6);
GEN_READ_REG(dr7);
GEN_WRITE_REG(dr0);
GEN_WRITE_REG(dr1);
GEN_WRITE_REG(dr2);
GEN_WRITE_REG(dr3);
GEN_WRITE_REG(dr6);
GEN_WRITE_REG(dr7);
/** Byte to port
*
* Output byte to port
*
* @param port Port to write to
* @param val Value to write
*/
static inline void outb(__u16 port, __u8 val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); }
/** Word to port
*
* Output word to port
*
* @param port Port to write to
* @param val Value to write
*/
static inline void outw(__u16 port, __u16 val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); }
/** Double word to port
*
* Output double word to port
*
* @param port Port to write to
* @param val Value to write
*/
static inline void outl(__u16 port, __u32 val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); }
/** Byte from port
*
* Get byte from port
*
* @param port Port to read from
* @return Value read
*/
static inline __u8 inb(__u16 port) { __u8 val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; }
/** Word from port
*
* Get word from port
*
* @param port Port to read from
* @return Value read
*/
static inline __u16 inw(__u16 port) { __u16 val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; }
/** Double word from port
*
* Get double word from port
*
* @param port Port to read from
* @return Value read
*/
static inline __u32 inl(__u16 port) { __u32 val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; }
/** Enable interrupts.
*
* Enable interrupts and return previous
* value of EFLAGS.
*
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_enable(void)
{
ipl_t v;
__asm__ volatile (
"pushf\n\t"
"popl %0\n\t"
"sti\n"
: "=r" (v)
);
return v;
}
/** Disable interrupts.
*
* Disable interrupts and return previous
* value of EFLAGS.
*
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_disable(void)
{
ipl_t v;
__asm__ volatile (
"pushf\n\t"
"popl %0\n\t"
"cli\n"
: "=r" (v)
);
return v;
}
/** Restore interrupt priority level.
*
* Restore EFLAGS.
*
* @param ipl Saved interrupt priority level.
*/
static inline void interrupts_restore(ipl_t ipl)
{
__asm__ volatile (
"pushl %0\n\t"
"popf\n"
: : "r" (ipl)
);
}
/** Return interrupt priority level.
*
* @return EFLAFS.
*/
static inline ipl_t interrupts_read(void)
{
ipl_t v;
__asm__ volatile (
"pushf\n\t"
"popl %0\n"
: "=r" (v)
);
return v;
}
/** Return base address of current stack
*
* Return the base address of the current stack.
* The stack is assumed to be STACK_SIZE bytes long.
* The stack must start on page boundary.
*/
static inline __address get_stack_base(void)
{
__address v;
__asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1)));
return v;
}
static inline __u64 rdtsc(void)
{
__u64 v;
__asm__ volatile("rdtsc\n" : "=A" (v));
return v;
}
/** Return current IP address */
static inline __address * get_ip()
{
__address *ip;
__asm__ volatile (
"mov %%eip, %0"
: "=r" (ip)
);
return ip;
}
/** Invalidate TLB Entry.
*
* @param addr Address on a page whose TLB entry is to be invalidated.
*/
static inline void invlpg(__address addr)
{
__asm__ volatile ("invlpg %0\n" :: "m" (*(__native *)addr));
}
/** Load GDTR register from memory.
*
* @param gdtr_reg Address of memory from where to load GDTR.
*/
static inline void gdtr_load(ptr_16_32_t *gdtr_reg)
{
__asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg));
}
/** Store GDTR register to memory.
*
* @param gdtr_reg Address of memory to where to load GDTR.
*/
static inline void gdtr_store(ptr_16_32_t *gdtr_reg)
{
__asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg));
}
/** Load IDTR register from memory.
*
* @param idtr_reg Address of memory from where to load IDTR.
*/
static inline void idtr_load(ptr_16_32_t *idtr_reg)
{
__asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg));
}
/** Load TR from descriptor table.
*
* @param sel Selector specifying descriptor of TSS segment.
*/
static inline void tr_load(__u16 sel)
{
__asm__ volatile ("ltr %0" : : "r" (sel));
}
#endif

/tags/0.2.0/kernel/arch/ia32/include/atomic.h
0,0 → 1,121
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_ATOMIC_H__
#define __ia32_ATOMIC_H__
#include <arch/types.h>
#include <arch/barrier.h>
#include <preemption.h>
#include <typedefs.h>
static inline void atomic_inc(atomic_t *val) {
#ifdef CONFIG_SMP
__asm__ volatile ("lock incl %0\n" : "=m" (val->count));
#else
__asm__ volatile ("incl %0\n" : "=m" (val->count));
#endif /* CONFIG_SMP */
}
static inline void atomic_dec(atomic_t *val) {
#ifdef CONFIG_SMP
__asm__ volatile ("lock decl %0\n" : "=m" (val->count));
#else
__asm__ volatile ("decl %0\n" : "=m" (val->count));
#endif /* CONFIG_SMP */
}
static inline long atomic_postinc(atomic_t *val)
{
long r;
__asm__ volatile (
"movl $1, %0\n"
"lock xaddl %0, %1\n"
: "=r" (r), "=m" (val->count)
);
return r;
}
static inline long atomic_postdec(atomic_t *val)
{
long r;
__asm__ volatile (
"movl $-1, %0\n"
"lock xaddl %0, %1\n"
: "=r" (r), "=m" (val->count)
);
return r;
}
#define atomic_preinc(val) (atomic_postinc(val)+1)
#define atomic_predec(val) (atomic_postdec(val)-1)
static inline __u32 test_and_set(atomic_t *val) {
__u32 v;
__asm__ volatile (
"movl $1, %0\n"
"xchgl %0, %1\n"
: "=r" (v),"=m" (val->count)
);
return v;
}
/** ia32 specific fast spinlock */
static inline void atomic_lock_arch(atomic_t *val)
{
__u32 tmp;
preemption_disable();
__asm__ volatile (
"0:;"
#ifdef CONFIG_HT
"pause;" /* Pentium 4's HT love this instruction */
#endif
"mov %0, %1;"
"testl %1, %1;"
"jnz 0b;" /* Lightweight looping on locked spinlock */
"incl %1;" /* now use the atomic operation */
"xchgl %0, %1;"
"testl %1, %1;"
"jnz 0b;"
: "=m"(val->count),"=r"(tmp)
);
/*
* Prevent critical section code from bleeding out this way up.
*/
CS_ENTER_BARRIER();
}
#endif

/tags/0.2.0/kernel/arch/ia32/include/debugger.h
0,0 → 1,0
link ../../amd64/include/debugger.h
Property changes:
Added: svn:special
+*
\ No newline at end of property

/tags/0.2.0/kernel/arch/ia32/include/fpu_context.h
0,0 → 1,46
/*
* Copyright (C) 2005 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_FPU_CONTEXT_H__
#define __ia32_FPU_CONTEXT_H__
#include <arch/types.h>
#define ARCH_HAS_FPU
#define FPU_CONTEXT_ALIGN 16
void fpu_fxsr(void);
void fpu_fsr(void);
struct fpu_context {
__u8 fpu[512]; /* FXSAVE & FXRSTOR storage area */
};
#endif

/tags/0.2.0/kernel/arch/ia32/include/cpuid.h
0,0 → 1,110
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_CPUID_H__
#define __ia32_CPUID_H__
#include <arch/types.h>
struct cpu_info {
__u32 cpuid_eax;
__u32 cpuid_ebx;
__u32 cpuid_ecx;
__u32 cpuid_edx;
} __attribute__ ((packed));
struct __cpuid_extended_feature_info {
unsigned sse3 : 1;
unsigned : 31;
} __attribute__ ((packed));
typedef union cpuid_extended_feature_info
{
struct __cpuid_extended_feature_info bits;
__u32 word;
}cpuid_extended_feature_info;
struct __cpuid_feature_info {
unsigned : 23;
unsigned mmx : 1;
unsigned fxsr : 1;
unsigned sse : 1;
unsigned sse2 : 1;
unsigned : 5;
} __attribute__ ((packed));
typedef union cpuid_feature_info
{
struct __cpuid_feature_info bits;
__u32 word ;
}cpuid_feature_info;
static inline __u32 has_cpuid(void)
{
__u32 val, ret;
__asm__ volatile (
"pushf\n" /* read flags */
"popl %0\n"
"movl %0, %1\n"
"btcl $21, %1\n" /* swap the ID bit */
"pushl %1\n" /* propagate the change into flags */
"popf\n"
"pushf\n"
"popl %1\n"
"andl $(1 << 21), %0\n" /* interrested only in ID bit */
"andl $(1 << 21), %1\n"
"xorl %1, %0\n"
: "=r" (ret), "=r" (val)
);
return ret;
}
static inline void cpuid(__u32 cmd, struct cpu_info *info)
{
__asm__ volatile (
"movl %4, %%eax\n"
"cpuid\n"
"movl %%eax, %0\n"
"movl %%ebx, %1\n"
"movl %%ecx, %2\n"
"movl %%edx, %3\n"
: "=m" (info->cpuid_eax), "=m" (info->cpuid_ebx), "=m" (info->cpuid_ecx), "=m" (info->cpuid_edx)
: "m" (cmd)
: "eax", "ebx", "ecx", "edx"
);
}
#endif

/tags/0.2.0/kernel/arch/ia32/include/types.h
0,0 → 1,54
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __TYPES_H__
#define __TYPES_H__
#define NULL 0
typedef signed char __s8;
typedef signed short __s16;
typedef signed long __s32;
typedef signed long long __s64;
typedef unsigned char __u8;
typedef unsigned short __u16;
typedef unsigned long __u32;
typedef unsigned long long __u64;
typedef __u32 __address;
typedef __u32 pfn_t;
typedef __u32 ipl_t;
typedef __u32 __native;
typedef __s32 __snative;
typedef struct page_specifier pte_t;
#endif

/tags/0.2.0/kernel/arch/ia32/include/boot/boot.h
0,0 → 1,41
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_BOOT_H__
#define __ia32_BOOT_H__
#define BOOT_OFFSET 0x108000
#define AP_BOOT_OFFSET 0x8000
#define BOOT_STACK_SIZE 0x400
#define MULTIBOOT_HEADER_MAGIC 0x1BADB002
#define MULTIBOOT_HEADER_FLAGS 0x00010003
#define MULTIBOOT_LOADER_MAGIC 0x2BADB002
#endif

/tags/0.2.0/kernel/arch/ia32/include/boot/memmap.h
0,0 → 1,68
/*
* Copyright (C) 2005 Josef Cejka
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_MEMMAP_H__
#define __ia32_MEMMAP_H__
/* E820h memory range types - other values*/
/* Free memory */
#define MEMMAP_MEMORY_AVAILABLE 1
/* Not available for OS */
#define MEMMAP_MEMORY_RESERVED 2
/* OS may use it after reading ACPI table */
#define MEMMAP_MEMORY_ACPI 3
/* Unusable, required to be saved and restored across an NVS sleep */
#define MEMMAP_MEMORY_NVS 4
/* Corrupted memory */
#define MEMMAP_MEMORY_UNUSABLE 5
/* size of one entry */
#define MEMMAP_E820_RECORD_SIZE 20
/* maximum entries */
#define MEMMAP_E820_MAX_RECORDS 32
#ifndef __ASM__
#include <arch/types.h>
struct e820memmap_ {
__u64 base_address;
__u64 size;
__u32 type;
} __attribute__ ((packed));
extern struct e820memmap_ e820table[MEMMAP_E820_MAX_RECORDS];
extern __u8 e820counter;
extern __u32 e801memorysize; /**< Size of available memory in KB. */
#endif
#endif

/tags/0.2.0/kernel/arch/ia32/include/elf.h
0,0 → 1,36
/*
* Copyright (C) 2006 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_ELF_H__
#define __ia32_ELF_H__
#define ELF_MACHINE EM_386
#define ELF_DATA_ENCODING ELFDATA2LSB
#define ELF_CLASS ELFCLASS32
#endif

/tags/0.2.0/kernel/arch/ia32/include/debug.h
0,0 → 1,36
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_DEBUG_H__
#define __ia32_DEBUG_H__
#include <arch/asm.h>
#define HERE get_ip()
#endif

/tags/0.2.0/kernel/arch/ia32/include/memstr.h
0,0 → 1,142
/*
* Copyright (C) 2005 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_MEMSTR_H__
#define __ia32_MEMSTR_H__
/** Copy memory
*
* Copy a given number of bytes (3rd argument)
* from the memory location defined by 2nd argument
* to the memory location defined by 1st argument.
* The memory areas cannot overlap.
*
* @param dst Destination
* @param src Source
* @param cnt Number of bytes
* @return Destination
*/
static inline void * memcpy(void * dst, const void * src, size_t cnt)
{
__native d0, d1, d2;
__asm__ __volatile__(
/* copy all full dwords */
"rep movsl\n\t"
/* load count again */
"movl %4, %%ecx\n\t"
/* ecx = ecx mod 4 */
"andl $3, %%ecx\n\t"
/* are there last <=3 bytes? */
"jz 1f\n\t"
/* copy last <=3 bytes */
"rep movsb\n\t"
/* exit from asm block */
"1:\n"
: "=&c" (d0), "=&D" (d1), "=&S" (d2)
: "0" ((__native) (cnt / 4)), "g" ((__native) cnt), "1" ((__native) dst), "2" ((__native) src)
: "memory");
return dst;
}
/** Compare memory regions for equality
*
* Compare a given number of bytes (3rd argument)
* at memory locations defined by 1st and 2nd argument
* for equality. If bytes are equal function returns 0.
*
* @param src Region 1
* @param dst Region 2
* @param cnt Number of bytes
* @return Zero if bytes are equal, non-zero otherwise
*/
static inline int memcmp(const void * src, const void * dst, size_t cnt)
{
__u32 d0, d1, d2;
int ret;
__asm__ (
"repe cmpsb\n\t"
"je 1f\n\t"
"movl %3, %0\n\t"
"addl $1, %0\n\t"
"1:\n"
: "=a" (ret), "=%S" (d0), "=&D" (d1), "=&c" (d2)
: "0" (0), "1" ((__native) src), "2" ((__native) dst), "3" ((__native) cnt)
);
return ret;
}
/** Fill memory with words
* Fill a given number of words (2nd argument)
* at memory defined by 1st argument with the
* word value defined by 3rd argument.
*
* @param dst Destination
* @param cnt Number of words
* @param x Value to fill
*/
static inline void memsetw(__address dst, size_t cnt, __u16 x)
{
__u32 d0, d1;
__asm__ __volatile__ (
"rep stosw\n\t"
: "=&D" (d0), "=&c" (d1), "=a" (x)
: "0" (dst), "1" (cnt), "2" (x)
: "memory"
);
}
/** Fill memory with bytes
* Fill a given number of bytes (2nd argument)
* at memory defined by 1st argument with the
* word value defined by 3rd argument.
*
* @param dst Destination
* @param cnt Number of bytes
* @param x Value to fill
*/
static inline void memsetb(__address dst, size_t cnt, __u8 x)
{
__u32 d0, d1;
__asm__ __volatile__ (
"rep stosb\n\t"
: "=&D" (d0), "=&c" (d1), "=a" (x)
: "0" (dst), "1" (cnt), "2" (x)
: "memory"
);
}
#endif

/tags/0.2.0/kernel/arch/ia32/include/context.h
0,0 → 1,58
/*
* Copyright (C) 2001-2004 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_CONTEXT_H__
#define __ia32_CONTEXT_H__
#include <arch/types.h>
#define STACK_ITEM_SIZE 4
/*
* Both context_save() and context_restore() eat two doublewords from the stack.
* First for pop of the saved register, second during ret instruction.
*
* One item is put onto stack to support get_stack_base().
*/
#define SP_DELTA (8+STACK_ITEM_SIZE)
/*
* Only save registers that must be preserved across
* function calls.
*/
struct context {
__address sp;
__address pc;
__u32 ebx;
__u32 esi;
__u32 edi;
__u32 ebp;
ipl_t ipl;
} __attribute__ ((packed));
#endif

/tags/0.2.0/kernel/arch/ia32/include/byteorder.h
0,0 → 1,36
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_BYTEORDER_H__
#define __ia32_BYTEORDER_H__
/* IA-32 is little-endian */
#define __native_le2host(n) (n)
#define __u64_le2host(n) (n)
#endif

/tags/0.2.0/kernel/arch/ia32/include/arch.h
0,0 → 1,32
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_ARCH_H__
#define __ia32_ARCH_H__
#endif

/tags/0.2.0/kernel/arch/ia32/include/faddr.h
0,0 → 1,36
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_FADDR_H__
#define __ia32_FADDR_H__
#include <arch/types.h>
#define FADDR(fptr) ((__address) (fptr))
#endif

/tags/0.2.0/kernel/arch/ia32/include/arg.h
0,0 → 1,34
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia32_ARG_H__
#define __ia32_ARG_H__
#include <stackarg.h>
#endif

/tags/0.2.0/kernel/arch/ia32/include/bios/bios.h
0,0 → 1,40
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __BIOS_H__
#define __BIOS_H__
#include <arch/types.h>
#define BIOS_EBDA_PTR 0x40e
extern __address ebda;
extern void bios_init(void);
#endif /* __BIOS_H__ */

/tags/0.2.0/kernel/arch/ia32/Makefile.inc
0,0 → 1,142
#
# Copyright (C) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
## Toolchain configuration
#
BFD_NAME = elf32-i386
BFD_ARCH = i386
BFD = binary
TARGET = i686-pc-linux-gnu
TOOLCHAIN_DIR = /usr/local/i686/bin
## Make some default assumptions
#
ifndef IA32_CPU
IA32_CPU = pentium4
endif
DEFS += -D_CPU=${IA32_CPU} -D__32_BITS__
## Accepted CPUs
#
ifeq ($(IA32_CPU),athlon-xp)
CFLAGS += -march=athlon-xp -mmmx -msse -m3dnow
DEFS += -DCONFIG_FENCES_P3
CONFIG_SMP = n
CONFIG_HT = n
endif
ifeq ($(IA32_CPU),athlon-mp)
CFLAGS += -march=athlon-mp -mmmx -msse -m3dnow
DEFS += -DCONFIG_FENCES_P3
CONFIG_HT = n
endif
ifeq ($(IA32_CPU),pentium3)
CFLAGS += -march=pentium3 -mmmx -msse
DEFS += -DCONFIG_FENCES_P3
CONFIG_HT = n
endif
ifeq ($(IA32_CPU),prescott)
CFLAGS += -march=pentium4 -mfpmath=sse -mmmx -msse -msse2 -msse3
DEFS += -DCONFIG_FENCES_P4
endif
ifeq ($(IA32_CPU),pentium4)
CFLAGS += -march=pentium4 -mfpmath=sse -mmmx -msse -msse2
DEFS += -DCONFIG_FENCES_P4
endif
## Own configuration directives
#
CONFIG_ACPI = y
## Compile with hierarchical page tables support.
#
CONFIG_PAGE_PT = y
DEFS += -DCONFIG_PAGE_PT
## Compile with i8042 controller support
#
CONFIG_I8042 = y
## Accepted configuration directives
#
ifeq ($(CONFIG_SMP),y)
DEFS += -DCONFIG_SMP
endif
ifeq ($(CONFIG_HT),y)
DEFS += -DCONFIG_HT
endif
ifeq ($(CONFIG_SIMICS_FIX),y)
DEFS += -DCONFIG_SIMICS_FIX
endif
## Compile with support for software integer division.
#
CONFIG_SOFTINT = y
ARCH_SOURCES = \
arch/$(ARCH)/src/context.s \
arch/$(ARCH)/src/debug/panic.s \
arch/$(ARCH)/src/delay.s \
arch/$(ARCH)/src/asm.S \
arch/$(ARCH)/src/proc/scheduler.c \
arch/$(ARCH)/src/proc/task.c \
arch/$(ARCH)/src/proc/thread.c \
arch/$(ARCH)/src/bios/bios.c \
arch/$(ARCH)/src/smp/ap.S \
arch/$(ARCH)/src/smp/apic.c \
arch/$(ARCH)/src/smp/mps.c \
arch/$(ARCH)/src/smp/smp.c \
arch/$(ARCH)/src/atomic.S \
arch/$(ARCH)/src/smp/ipi.c \
arch/$(ARCH)/src/ia32.c \
arch/$(ARCH)/src/interrupt.c \
arch/$(ARCH)/src/pm.c \
arch/$(ARCH)/src/userspace.c \
arch/$(ARCH)/src/cpu/cpu.c \
arch/$(ARCH)/src/mm/as.c \
arch/$(ARCH)/src/mm/frame.c \
arch/$(ARCH)/src/mm/memory_init.c \
arch/$(ARCH)/src/mm/page.c \
arch/$(ARCH)/src/mm/tlb.c \
arch/$(ARCH)/src/ddi/ddi.c \
arch/$(ARCH)/src/drivers/i8254.c \
arch/$(ARCH)/src/drivers/i8259.c \
arch/$(ARCH)/src/drivers/ega.c \
arch/$(ARCH)/src/drivers/vesa.c \
arch/$(ARCH)/src/boot/boot.S \
arch/$(ARCH)/src/fpu_context.c \
arch/$(ARCH)/src/debugger.c

/tags/0.2.0/kernel/arch/ia32/_link.ld.in
0,0 → 1,65
/** IA-32 linker script
*
* umapped section:
* kernel text
* kernel data
* mapped section:
* kernel text
* kernel data
*/
#define __ASM__
#include <arch/boot/boot.h>
#include <arch/mm/page.h>
SECTIONS {
.unmapped BOOT_OFFSET: AT (0) {
unmapped_ktext_start = .;
*(K_TEXT_START);
unmapped_ktext_end = .;
unmapped_kdata_start = .;
*(K_DATA_START);
unmapped_kdata_end = .;
}
.mapped (PA2KA(BOOT_OFFSET)+SIZEOF(.unmapped)): AT (SIZEOF(.unmapped)) {
ktext_start = .;
*(.text);
ktext_end = .;
kdata_start = .;
*(.data); /* initialized data */
*(.rodata*); /* string literals */
*(COMMON); /* global variables */
hardcoded_load_address = .;
LONG(PA2KA(BOOT_OFFSET));
hardcoded_ktext_size = .;
LONG((ktext_end - ktext_start) + (unmapped_ktext_end - unmapped_ktext_start));
hardcoded_kdata_size = .;
LONG((kdata_end - kdata_start) + (unmapped_kdata_end - unmapped_kdata_start));
hardcoded_unmapped_ktext_size = .;
LONG(unmapped_ktext_end - unmapped_ktext_start);
hardcoded_unmapped_kdata_size = .;
LONG(unmapped_kdata_end - unmapped_kdata_start);
symbol_table = .;
*(symtab.*); /* Symbol table, must be LAST symbol! */
*(.bss); /* uninitialized static variables */
kdata_end = .;
}
/DISCARD/ : {
*(.note.GNU-stack);
*(.comment);
}
#ifdef CONFIG_SMP
_hardcoded_unmapped_size = (unmapped_ktext_end - unmapped_ktext_start) + (unmapped_kdata_end - unmapped_kdata_start);
ap_boot = unmapped_ap_boot - BOOT_OFFSET + AP_BOOT_OFFSET;
ap_gdtr = unmapped_ap_gdtr - BOOT_OFFSET + AP_BOOT_OFFSET;
protected_ap_gdtr = PA2KA(ap_gdtr);
#endif /* CONFIG_SMP */
}

/tags/0.2.0/kernel/arch/ppc32/include/drivers/cuda.h
0,0 → 1,40
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CUDA_H__
#define __CUDA_H__
#include <arch/types.h>
#include <typedefs.h>
#define CUDA_IRQ 10
extern void cuda_init(__address base, size_t size);
extern int cuda_get_scancode(void);
#endif

/tags/0.2.0/kernel/arch/ppc32/include/drivers/pic.h
0,0 → 1,48
/*
* Copyright (C) 2006 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PIC_H_
#define __PIC_H_
/* PIC handler, read from pearpc source codes */
#define PIC_HW_ADDR 0x80800000
#define PIC_PENDING_LOW 8
#define PIC_PENDING_HIGH 4
#define PIC_MASK_LOW 9
#define PIC_MASK_HIGH 5
#define PIC_ACK_LOW 10
#define PIC_ACK_HIGH 6
void pic_init(void);
void pic_enable_interrupt(int intnum);
void pic_disable_interrupt(int intnum);
void pic_ack_interrupt(int intnum);
int pic_get_pending(void);
#endif

/tags/0.2.0/kernel/arch/ppc32/include/arch.h
0,0 → 1,34
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_ARCH_H__
#define __ppc32_ARCH_H__
#include <arch/drivers/cuda.h>
#endif

/tags/0.2.0/kernel/arch/ppc32/include/boot/boot.h
0,0 → 1,89
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_BOOT_H__
#define __ppc32_BOOT_H__
#define BOOT_OFFSET 0x4000
/* Temporary stack size for boot process */
#define TEMP_STACK_SIZE 0x100
#define TASKMAP_MAX_RECORDS 32
#define MEMMAP_MAX_RECORDS 32
#ifndef __ASM__
#include <arch/types.h>
typedef struct {
__address addr;
__u32 size;
} utask_t;
typedef struct {
__u32 count;
utask_t tasks[TASKMAP_MAX_RECORDS];
} taskmap_t;
typedef struct {
__address start;
__u32 size;
} memzone_t;
typedef struct {
__u32 total;
__u32 count;
memzone_t zones[MEMMAP_MAX_RECORDS];
} memmap_t;
typedef struct {
__address addr;
unsigned int width;
unsigned int height;
unsigned int bpp;
unsigned int scanline;
} screen_t;
typedef struct {
__address addr;
unsigned int size;
} keyboard_t;
typedef struct {
taskmap_t taskmap;
memmap_t memmap;
screen_t screen;
keyboard_t keyboard;
} bootinfo_t;
extern bootinfo_t bootinfo;
#endif
#endif

/tags/0.2.0/kernel/arch/ppc32/include/interrupt.h
0,0 → 1,51
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_INTERRUPT_H__
#define __ppc32_INTERRUPT_H__
#include <arch/exception.h>
#define IRQ_COUNT 64
#define IVT_ITEMS (16 + IRQ_COUNT)
#define INT_OFFSET 16
#define int_register(it, name, handler) exc_register(((it) + INT_OFFSET), name, handler)
#define VECTOR_DATA_STORAGE 2
#define VECTOR_INSTRUCTION_STORAGE 3
#define VECTOR_EXTERNAL 4
#define VECTOR_DECREMENTER 8
extern void start_decrementer(void);
extern void interrupt_init(void);
extern void extint_handler(int n, istate_t *istate);
#endif

/tags/0.2.0/kernel/arch/ppc32/include/mm/page.h
0,0 → 1,153
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_PAGE_H__
#define __ppc32_PAGE_H__
#include <arch/mm/frame.h>
#define PAGE_WIDTH FRAME_WIDTH
#define PAGE_SIZE FRAME_SIZE
#ifdef KERNEL
#ifndef __ASM__
# define KA2PA(x) (((__address) (x)) - 0x80000000)
# define PA2KA(x) (((__address) (x)) + 0x80000000)
#else
# define KA2PA(x) ((x) - 0x80000000)
# define PA2KA(x) ((x) + 0x80000000)
#endif
/*
* Implementation of generic 4-level page table interface,
* the hardware Page Hash Table is used as cache.
*
* Page table layout:
* - 32-bit virtual addressess
* - Offset is 12 bits => pages are 4K long
* - PTL0 has 1024 entries (10 bits)
* - PTL1 is not used
* - PTL2 is not used
* - PLT3 has 1024 entries (10 bits)
*/
#define PTL0_ENTRIES_ARCH 1024
#define PTL1_ENTRIES_ARCH 0
#define PTL2_ENTRIES_ARCH 0
#define PTL3_ENTRIES_ARCH 1024
#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff)
#define PTL1_INDEX_ARCH(vaddr) 0
#define PTL2_INDEX_ARCH(vaddr) 0
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff)
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *) (ptl0))[(i)].pfn << 12)
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *) (ptl3))[(i)].pfn << 12)
#define SET_PTL0_ADDRESS_ARCH(ptl0)
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *) (ptl0), (index_t) (i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *) (ptl3), (index_t) (i))
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
#define PTE_VALID_ARCH(pte) (*((__u32 *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte) ((pte)->p != 0)
#define PTE_GET_FRAME_ARCH(pte) ((pte)->pfn << 12)
#define PTE_WRITABLE_ARCH(pte) 1
#define PTE_EXECUTABLE_ARCH(pte) 1
#ifndef __ASM__
#include <mm/page.h>
#include <arch/mm/frame.h>
#include <arch/types.h>
static inline int get_pt_flags(pte_t *pt, index_t i)
{
pte_t *p = &pt[i];
return (
(1 << PAGE_CACHEABLE_SHIFT) |
((!p->p) << PAGE_PRESENT_SHIFT) |
(1 << PAGE_USER_SHIFT) |
(1 << PAGE_READ_SHIFT) |
(1 << PAGE_WRITE_SHIFT) |
(1 << PAGE_EXEC_SHIFT) |
(p->g << PAGE_GLOBAL_SHIFT)
);
}
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
{
pte_t *p = &pt[i];
p->p = !(flags & PAGE_NOT_PRESENT);
p->g = (flags & PAGE_GLOBAL) != 0;
p->valid = 1;
}
extern void page_arch_init(void);
#define PHT_BITS 16
#define PHT_ORDER 4
typedef struct {
unsigned v : 1; /**< Valid */
unsigned vsid : 24; /**< Virtual Segment ID */
unsigned h : 1; /**< Primary/secondary hash */
unsigned api : 6; /**< Abbreviated Page Index */
unsigned rpn : 20; /**< Real Page Number */
unsigned reserved0 : 3;
unsigned r : 1; /**< Reference */
unsigned c : 1; /**< Change */
unsigned wimg : 4; /**< Access control */
unsigned reserved1 : 1;
unsigned pp : 2; /**< Page protection */
} phte_t;
extern void pht_refill(int n, istate_t *istate);
extern void pht_init(void);
#endif /* __ASM__ */
#endif /* KERNEL */
#endif

/tags/0.2.0/kernel/arch/ppc32/include/mm/as.h
0,0 → 1,45
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_AS_H__
#define __ppc32_AS_H__
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0
#define KERNEL_ADDRESS_SPACE_START_ARCH ((unsigned long) 0x80000000)
#define KERNEL_ADDRESS_SPACE_END_ARCH ((unsigned long) 0xffffffff)
#define USER_ADDRESS_SPACE_START_ARCH ((unsigned long) 0x00000000)
#define USER_ADDRESS_SPACE_END_ARCH ((unsigned long) 0x7fffffff)
#define USTACK_ADDRESS_ARCH (0x7fffffff-(PAGE_SIZE-1))
#define as_install_arch(as)
extern void as_arch_init(void);
#endif

/tags/0.2.0/kernel/arch/ppc32/include/mm/asid.h
0,0 → 1,39
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_ASID_H__
#define __ppc32_ASID_H__
typedef int asid_t;
#define ASID_MAX_ARCH 3
#define asid_get() (ASID_START+1)
#define asid_put(asid)
#endif

/tags/0.2.0/kernel/arch/ppc32/include/mm/frame.h
0,0 → 1,47
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_FRAME_H__
#define __ppc32_FRAME_H__
#define FRAME_WIDTH 12 /* 4K */
#define FRAME_SIZE (1 << FRAME_WIDTH)
#ifdef KERNEL
#ifndef __ASM__
#include <arch/types.h>
extern __address last_frame;
extern void frame_arch_init(void);
#endif /* __ASM__ */
#endif /* KERNEL */
#endif

/tags/0.2.0/kernel/arch/ppc32/include/mm/tlb.h
0,0 → 1,33
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_TLB_H__
#define __ppc32_TLB_H__
#endif

/tags/0.2.0/kernel/arch/ppc32/include/mm/memory_init.h
0,0 → 1,38
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_MEMORY_INIT_H__
#define __ppc32_MEMORY_INIT_H__
#include <typedefs.h>
size_t get_memory_size(void);
void memory_print_map(void);
#endif

/tags/0.2.0/kernel/arch/ppc32/include/exception.h
0,0 → 1,95
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_EXCEPTION_H__
#define __ppc32_EXCEPTION_H__
#ifndef __ppc32_TYPES_H__
# include <arch/types.h>
#endif
#include <typedefs.h>
struct istate {
__u32 r0;
__u32 r2;
__u32 r3;
__u32 r4;
__u32 r5;
__u32 r6;
__u32 r7;
__u32 r8;
__u32 r9;
__u32 r10;
__u32 r11;
__u32 r13;
__u32 r14;
__u32 r15;
__u32 r16;
__u32 r17;
__u32 r18;
__u32 r19;
__u32 r20;
__u32 r21;
__u32 r22;
__u32 r23;
__u32 r24;
__u32 r25;
__u32 r26;
__u32 r27;
__u32 r28;
__u32 r29;
__u32 r30;
__u32 r31;
__u32 cr;
__u32 pc;
__u32 srr1;
__u32 lr;
__u32 ctr;
__u32 xer;
__u32 r12;
__u32 sp;
};
static inline void istate_set_retaddr(istate_t *istate, __address retaddr)
{
istate->pc = retaddr;
}
/** Return true if exception happened while in userspace */
#include <panic.h>
static inline int istate_from_uspace(istate_t *istate)
{
panic("istate_from_uspace not yet implemented");
return 0;
}
static inline __native istate_get_pc(istate_t *istate)
{
return istate->pc;
}
#endif

/tags/0.2.0/kernel/arch/ppc32/include/proc/task.h
0,0 → 1,38
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_TASK_H__
#define __ppc32_TASK_H__
typedef struct {
} task_arch_t;
#define task_create_arch(t)
#define task_destroy_arch(t)
#endif

/tags/0.2.0/kernel/arch/ppc32/include/proc/thread.h
0,0 → 1,37
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_THREAD_H__
#define __ppc32_THREAD_H__
typedef struct {
} thread_arch_t;
#define thread_create_arch(t)
#endif

/tags/0.2.0/kernel/arch/ppc32/include/asm/regname.h
0,0 → 1,222
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_REGNAME_H__
#define __ppc32_REGNAME_H__
/* Condition Register Bit Fields */
#define cr0 0
#define cr1 1
#define cr2 2
#define cr3 3
#define cr4 4
#define cr5 5
#define cr6 6
#define cr7 7
/* General Purpose Registers (GPRs) */
#define r0 0
#define r1 1
#define r2 2
#define r3 3
#define r4 4
#define r5 5
#define r6 6
#define r7 7
#define r8 8
#define r9 9
#define r10 10
#define r11 11
#define r12 12
#define r13 13
#define r14 14
#define r15 15
#define r16 16
#define r17 17
#define r18 18
#define r19 19
#define r20 20
#define r21 21
#define r22 22
#define r23 23
#define r24 24
#define r25 25
#define r26 26
#define r27 27
#define r28 28
#define r29 29
#define r30 30
#define r31 31
/* GPR Aliases */
#define sp 1
/* Floating Point Registers (FPRs) */
#define fr0 0
#define fr1 1
#define fr2 2
#define fr3 3
#define fr4 4
#define fr5 5
#define fr6 6
#define fr7 7
#define fr8 8
#define fr9 9
#define fr10 10
#define fr11 11
#define fr12 12
#define fr13 13
#define fr14 14
#define fr15 15
#define fr16 16
#define fr17 17
#define fr18 18
#define fr19 19
#define fr20 20
#define fr21 21
#define fr22 22
#define fr23 23
#define fr24 24
#define fr25 25
#define fr26 26
#define fr27 27
#define fr28 28
#define fr29 29
#define fr30 30
#define fr31 31
#define vr0 0
#define vr1 1
#define vr2 2
#define vr3 3
#define vr4 4
#define vr5 5
#define vr6 6
#define vr7 7
#define vr8 8
#define vr9 9
#define vr10 10
#define vr11 11
#define vr12 12
#define vr13 13
#define vr14 14
#define vr15 15
#define vr16 16
#define vr17 17
#define vr18 18
#define vr19 19
#define vr20 20
#define vr21 21
#define vr22 22
#define vr23 23
#define vr24 24
#define vr25 25
#define vr26 26
#define vr27 27
#define vr28 28
#define vr29 29
#define vr30 30
#define vr31 31
#define evr0 0
#define evr1 1
#define evr2 2
#define evr3 3
#define evr4 4
#define evr5 5
#define evr6 6
#define evr7 7
#define evr8 8
#define evr9 9
#define evr10 10
#define evr11 11
#define evr12 12
#define evr13 13
#define evr14 14
#define evr15 15
#define evr16 16
#define evr17 17
#define evr18 18
#define evr19 19
#define evr20 20
#define evr21 21
#define evr22 22
#define evr23 23
#define evr24 24
#define evr25 25
#define evr26 26
#define evr27 27
#define evr28 28
#define evr29 29
#define evr30 30
#define evr31 31
/* Special Purpose Registers (SPRs) */
#define xer 1
#define lr 8
#define ctr 9
#define dec 22
#define sdr1 25
#define srr0 26
#define srr1 27
#define sprg0 272
#define sprg1 273
#define sprg2 274
#define sprg3 275
#define prv 287
#define ibat0u 528
#define ibat0l 529
#define ibat1u 530
#define ibat1l 531
#define ibat2u 532
#define ibat2l 533
#define ibat3u 534
#define ibat3l 535
#define dbat0u 536
#define dbat0l 537
#define dbat1u 538
#define dbat1l 539
#define dbat2u 540
#define dbat2l 541
#define dbat3u 542
#define dbat3l 543
#define hid0 1008
/* MSR bits */
#define msr_ir (1 << 4)
#define msr_dr (1 << 5)
#define msr_pr (1 << 14)
#define msr_ee (1 << 15)
/* HID0 bits */
#define hid0_ice (1 << 15)
#define hid0_dce (1 << 14)
#define hid0_icfi (1 << 11)
#define hid0_dci (1 << 10)
#endif

/tags/0.2.0/kernel/arch/ppc32/include/types.h
0,0 → 1,60
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_TYPES_H__
#define __ppc32_TYPES_H__
#define NULL 0
typedef signed char __s8;
typedef signed short __s16;
typedef signed int __s32;
typedef signed long long __s64;
typedef unsigned char __u8;
typedef unsigned short __u16;
typedef unsigned int __u32;
typedef unsigned long long __u64;
typedef __u32 __address;
typedef __u32 pfn_t;
typedef __u32 ipl_t;
typedef __u32 __native;
/** Page Table Entry. */
typedef struct {
unsigned p : 1; /**< Present bit. */
unsigned a : 1; /**< Accessed bit. */
unsigned g : 1; /**< Global bit. */
unsigned valid : 1; /**< Valid content even if not present. */
unsigned pfn : 20; /**< Physical frame number. */
} pte_t;
#endif

/tags/0.2.0/kernel/arch/ppc32/include/asm.h
0,0 → 1,146
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_ASM_H__
#define __ppc32_ASM_H__
#include <arch/types.h>
#include <config.h>
/** Enable interrupts.
*
* Enable interrupts and return previous
* value of EE.
*
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_enable(void)
{
ipl_t v;
ipl_t tmp;
asm volatile (
"mfmsr %0\n"
"mfmsr %1\n"
"ori %1, %1, 1 << 15\n"
"mtmsr %1\n"
: "=r" (v), "=r" (tmp)
);
return v;
}
/** Disable interrupts.
*
* Disable interrupts and return previous
* value of EE.
*
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_disable(void)
{
ipl_t v;
ipl_t tmp;
asm volatile (
"mfmsr %0\n"
"mfmsr %1\n"
"rlwinm %1, %1, 0, 17, 15\n"
"mtmsr %1\n"
: "=r" (v), "=r" (tmp)
);
return v;
}
/** Restore interrupt priority level.
*
* Restore EE.
*
* @param ipl Saved interrupt priority level.
*/
static inline void interrupts_restore(ipl_t ipl)
{
ipl_t tmp;
asm volatile (
"mfmsr %1\n"
"rlwimi %0, %1, 0, 17, 15\n"
"cmpw 0, %0, %1\n"
"beq 0f\n"
"mtmsr %0\n"
"0:\n"
: "=r" (ipl), "=r" (tmp)
: "0" (ipl)
: "cr0"
);
}
/** Return interrupt priority level.
*
* Return EE.
*
* @return Current interrupt priority level.
*/
static inline ipl_t interrupts_read(void)
{
ipl_t v;
asm volatile (
"mfmsr %0\n"
: "=r" (v)
);
return v;
}
/** Return base address of current stack.
*
* Return the base address of the current stack.
* The stack is assumed to be STACK_SIZE bytes long.
* The stack must start on page boundary.
*/
static inline __address get_stack_base(void)
{
__address v;
asm volatile (
"and %0, %%sp, %1\n"
: "=r" (v)
: "r" (~(STACK_SIZE - 1))
);
return v;
}
static inline void cpu_sleep(void)
{
}
void cpu_halt(void);
void asm_delay_loop(__u32 t);
extern void userspace_asm(__address uspace_uarg, __address stack, __address entry);
#endif

/tags/0.2.0/kernel/arch/ppc32/include/byteorder.h
0,0 → 1,64
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_BYTEORDER_H__
#define __ppc32_BYTEORDER_H__
#include <arch/types.h>
#include <byteorder.h>
#define BIG_ENDIAN
static inline __u64 __u64_le2host(__u64 n)
{
return __u64_byteorder_swap(n);
}
/** Convert little-endian __native to host __native
*
* Convert little-endian __native parameter to host endianess.
*
* @param n Little-endian __native argument.
*
* @return Result in host endianess.
*
*/
static inline __native __native_le2host(__native n)
{
__address v;
asm volatile (
"lwbrx %0, %1, %2\n"
: "=r" (v)
: "i" (0), "r" (&n)
);
return v;
}
#endif

/tags/0.2.0/kernel/arch/ppc32/include/cpuid.h
0,0 → 1,47
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_CPUID_H__
#define __ppc32_CPUID_H__
#include <arch/types.h>
struct cpu_info {
__u16 version;
__u16 revision;
} __attribute__ ((packed));
static inline void cpu_version(struct cpu_info *info)
{
asm volatile (
"mfpvr %0\n"
: "=r" (*info)
);
}
#endif

/tags/0.2.0/kernel/arch/ppc32/include/atomic.h
0,0 → 1,88
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_ATOMIC_H__
#define __ppc32_ATOMIC_H__
static inline void atomic_inc(atomic_t *val)
{
long tmp;
asm volatile (
"1:\n"
"lwarx %0, 0, %2\n"
"addic %0, %0, 1\n"
"stwcx. %0, 0, %2\n"
"bne- 1b"
: "=&r" (tmp), "=m" (val->count)
: "r" (&val->count), "m" (val->count)
: "cc"
);
}
static inline void atomic_dec(atomic_t *val)
{
long tmp;
asm volatile (
"1:\n"
"lwarx %0, 0, %2\n"
"addic %0, %0, -1\n"
"stwcx. %0, 0, %2\n"
"bne- 1b"
: "=&r" (tmp), "=m" (val->count)
: "r" (&val->count), "m" (val->count)
: "cc"
);
}
static inline long atomic_postinc(atomic_t *val)
{
atomic_inc(val);
return val->count - 1;
}
static inline long atomic_postdec(atomic_t *val)
{
atomic_dec(val);
return val->count + 1;
}
static inline long atomic_preinc(atomic_t *val)
{
atomic_inc(val);
return val->count;
}
static inline long atomic_predec(atomic_t *val)
{
atomic_dec(val);
return val->count;
}
#endif

/tags/0.2.0/kernel/arch/ppc32/include/barrier.h
0,0 → 1,39
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_BARRIER_H__
#define __ppc32_BARRIER_H__
#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory")
#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory")
#define memory_barrier() asm volatile ("sync" ::: "memory")
#define read_barrier() asm volatile ("sync" ::: "memory")
#define write_barrier() asm volatile ("eieio" ::: "memory")
#endif

/tags/0.2.0/kernel/arch/ppc32/include/context.h
0,0 → 1,68
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_CONTEXT_H__
#define __ppc32_CONTEXT_H__
#ifndef __ppc32_TYPES_H__
# include <arch/types.h>
#endif
#define SP_DELTA 16
struct context {
__address sp;
__address pc;
__u32 r2;
__u32 r13;
__u32 r14;
__u32 r15;
__u32 r16;
__u32 r17;
__u32 r18;
__u32 r19;
__u32 r20;
__u32 r21;
__u32 r22;
__u32 r23;
__u32 r24;
__u32 r25;
__u32 r26;
__u32 r27;
__u32 r28;
__u32 r29;
__u32 r30;
__u32 r31;
__u32 cr;
ipl_t ipl;
} __attribute__ ((packed));
#endif

/tags/0.2.0/kernel/arch/ppc32/include/elf.h
0,0 → 1,36
/*
* Copyright (C) 2006 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_ELF_H__
#define __ppc32_ELF_H__
#define ELF_MACHINE EM_PPC
#define ELF_DATA_ENCODING ELFDATA2MSB
#define ELF_CLASS ELFCLASS32
#endif

/tags/0.2.0/kernel/arch/ppc32/include/context_offset.h
0,0 → 1,45
/* This file is automatically generated by gencontext.c. */
/* struct context */
#define OFFSET_SP 0x0
#define OFFSET_PC 0x4
#define OFFSET_R2 0x8
#define OFFSET_R13 0xc
#define OFFSET_R14 0x10
#define OFFSET_R15 0x14
#define OFFSET_R16 0x18
#define OFFSET_R17 0x1c
#define OFFSET_R18 0x20
#define OFFSET_R19 0x24
#define OFFSET_R20 0x28
#define OFFSET_R21 0x2c
#define OFFSET_R22 0x30
#define OFFSET_R23 0x34
#define OFFSET_R24 0x38
#define OFFSET_R25 0x3c
#define OFFSET_R26 0x40
#define OFFSET_R27 0x44
#define OFFSET_R28 0x48
#define OFFSET_R29 0x4c
#define OFFSET_R30 0x50
#define OFFSET_R31 0x54
#define OFFSET_CR 0x58
#define OFFSET_FR14 0x0
#define OFFSET_FR15 0x8
#define OFFSET_FR16 0x10
#define OFFSET_FR17 0x18
#define OFFSET_FR18 0x20
#define OFFSET_FR19 0x28
#define OFFSET_FR20 0x30
#define OFFSET_FR21 0x38
#define OFFSET_FR22 0x40
#define OFFSET_FR23 0x48
#define OFFSET_FR24 0x50
#define OFFSET_FR25 0x58
#define OFFSET_FR26 0x60
#define OFFSET_FR27 0x68
#define OFFSET_FR28 0x70
#define OFFSET_FR29 0x78
#define OFFSET_FR30 0x80
#define OFFSET_FR31 0x88
#define OFFSET_FPSCR 0x90

/tags/0.2.0/kernel/arch/ppc32/include/fpu_context.h
0,0 → 1,58
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_FPU_CONTEXT_H__
#define __ppc32_FPU_CONTEXT_H__
#ifndef __ppc32_TYPES_H__
# include <arch/types.h>
#endif
struct fpu_context {
__u64 fr14;
__u64 fr15;
__u64 fr16;
__u64 fr17;
__u64 fr18;
__u64 fr19;
__u64 fr20;
__u64 fr21;
__u64 fr22;
__u64 fr23;
__u64 fr24;
__u64 fr25;
__u64 fr26;
__u64 fr27;
__u64 fr28;
__u64 fr29;
__u64 fr30;
__u64 fr31;
__u32 fpscr;
} __attribute__ ((packed));
#endif

/tags/0.2.0/kernel/arch/ppc32/include/cpu.h
0,0 → 1,39
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_CPU_H__
#define __ppc32_CPU_H__
#include <typedefs.h>
struct cpu_arch {
int version;
int revision;
};
#endif

/tags/0.2.0/kernel/arch/ppc32/include/memstr.h
0,0 → 1,39
/*
* Copyright (C) 2005 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_MEMSTR_H__
#define __ppc32_MEMSTR_H__
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt))
extern void memsetw(__address dst, size_t cnt, __u16 x);
extern void memsetb(__address dst, size_t cnt, __u8 x);
extern int memcmp(__address src, __address dst, int cnt);
#endif

/tags/0.2.0/kernel/arch/ppc32/include/debug.h
0,0 → 1,32
/*
* Copyright (C) 2005
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_DEBUG_H__
#define __ppc32_DEBUG_H__
#endif

/tags/0.2.0/kernel/arch/ppc32/include/arg.h
0,0 → 1,34
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_ARG_H__
#define __ppc32_ARG_H__
#include <stdarg.h>
#endif

/tags/0.2.0/kernel/arch/ppc32/include/faddr.h
0,0 → 1,36
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc32_FADDR_H__
#define __ppc32_FADDR_H__
#include <arch/types.h>
#define FADDR(fptr) ((__address) (fptr))
#endif

/tags/0.2.0/kernel/arch/ppc32/src/drivers/cuda.c
0,0 → 1,302
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/drivers/cuda.h>
#include <arch/asm.h>
#include <console/console.h>
#include <console/chardev.h>
#include <arch/drivers/pic.h>
#include <sysinfo/sysinfo.h>
#include <interrupt.h>
#include <stdarg.h>
#define SPECIAL '?'
#define PACKET_ADB 0x00
#define PACKET_CUDA 0x01
#define CUDA_POWERDOWN 0x0a
#define RS 0x200
#define B (0 * RS)
#define A (1 * RS)
#define SR (10 * RS)
#define ACR (11 * RS)
#define SR_OUT 0x10
#define TACK 0x10
#define TIP 0x20
static volatile __u8 *cuda = NULL;
static char lchars[0x80] = {
'a',
's',
'd',
'f',
'h',
'g',
'z',
'x',
'c',
'v',
SPECIAL,
'b',
'q',
'w',
'e',
'r',
'y',
't',
'1',
'2',
'3',
'4',
'6',
'5',
'=',
'9',
'7',
'-',
'8',
'0',
']',
'o',
'u',
'[',
'i',
'p',
'\n', /* Enter */
'l',
'j',
'\'',
'k',
';',
'\\',
',',
'/',
'n',
'm',
'.',
'\t', /* Tab */
' ',
'`',
'\b', /* Backspace */
SPECIAL,
SPECIAL, /* Escape */
SPECIAL, /* Ctrl */
SPECIAL, /* Alt */
SPECIAL, /* Shift */
SPECIAL, /* Caps-Lock */
SPECIAL, /* RAlt */
SPECIAL, /* Left */
SPECIAL, /* Right */
SPECIAL, /* Down */
SPECIAL, /* Up */
SPECIAL,
SPECIAL,
'.', /* Keypad . */
SPECIAL,
'*', /* Keypad * */
SPECIAL,
'+', /* Keypad + */
SPECIAL,
SPECIAL, /* NumLock */
SPECIAL,
SPECIAL,
SPECIAL,
'/', /* Keypad / */
'\n', /* Keypad Enter */
SPECIAL,
'-', /* Keypad - */
SPECIAL,
SPECIAL,
SPECIAL,
'0', /* Keypad 0 */
'1', /* Keypad 1 */
'2', /* Keypad 2 */
'3', /* Keypad 3 */
'4', /* Keypad 4 */
'5', /* Keypad 5 */
'6', /* Keypad 6 */
'7', /* Keypad 7 */
SPECIAL,
'8', /* Keypad 8 */
'9', /* Keypad 9 */
SPECIAL,
SPECIAL,
SPECIAL,
SPECIAL, /* F5 */
SPECIAL, /* F6 */
SPECIAL, /* F7 */
SPECIAL, /* F3 */
SPECIAL, /* F8 */
SPECIAL, /* F9 */
SPECIAL,
SPECIAL, /* F11 */
SPECIAL,
SPECIAL, /* F13 */
SPECIAL,
SPECIAL, /* ScrollLock */
SPECIAL,
SPECIAL, /* F10 */
SPECIAL,
SPECIAL, /* F12 */
SPECIAL,
SPECIAL, /* Pause */
SPECIAL, /* Insert */
SPECIAL, /* Home */
SPECIAL, /* PageUp */
SPECIAL, /* Delete */
SPECIAL, /* F4 */
SPECIAL, /* End */
SPECIAL, /* F2 */
SPECIAL, /* PageDown */
SPECIAL /* F1 */
};
void send_packet(const __u8 kind, index_t count, ...);
static void receive_packet(__u8 *kind, index_t count, __u8 data[])
{
cuda[B] = cuda[B] & ~TIP;
*kind = cuda[SR];
index_t i;
for (i = 0; i < count; i++)
data[i] = cuda[SR];
cuda[B] = cuda[B] | TIP;
}
/* Called from getc(). */
static void cuda_resume(chardev_t *d)
{
}
/* Called from getc(). */
static void cuda_suspend(chardev_t *d)
{
}
static char key_read(chardev_t *d)
{
char ch;
ch = 0;
return ch;
}
static chardev_t kbrd;
static chardev_operations_t ops = {
.suspend = cuda_suspend,
.resume = cuda_resume,
.read = key_read
};
int cuda_get_scancode(void)
{
__u8 kind;
__u8 data[4];
receive_packet(&kind, 4, data);
if ((kind == PACKET_ADB) && (data[0] == 0x40) && (data[1] == 0x2c))
return data[2];
return -1;
}
static void cuda_irq(int n, istate_t *istate)
{
int scan_code = cuda_get_scancode();
if (scan_code != -1) {
__u8 scancode = (__u8) scan_code;
if ((scancode & 0x80) != 0x80)
chardev_push_character(&kbrd, lchars[scancode & 0x7f]);
}
}
void cuda_init(__address base, size_t size)
{
cuda = (__u8 *) hw_map(base, size);
int_register(CUDA_IRQ, "cuda", cuda_irq);
pic_enable_interrupt(CUDA_IRQ);
chardev_initialize("cuda_kbd", &kbrd, &ops);
stdin = &kbrd;
sysinfo_set_item_val("cuda", NULL, true);
sysinfo_set_item_val("cuda.irq", NULL, CUDA_IRQ);
}
void send_packet(const __u8 kind, index_t count, ...)
{
index_t i;
va_list va;
cuda[B] = cuda[B] | TIP;
cuda[ACR] = cuda[ACR] | SR_OUT;
cuda[SR] = kind;
cuda[B] = cuda[B] & ~TIP;
va_start(va, count);
for (i = 0; i < count; i++) {
cuda[ACR] = cuda[ACR] | SR_OUT;
cuda[SR] = va_arg(va, int);
cuda[B] = cuda[B] | TACK;
}
va_end(va);
cuda[B] = cuda[B] | TIP;
}
void cpu_halt(void) {
#ifdef CONFIG_POWEROFF
send_packet(PACKET_CUDA, 1, CUDA_POWERDOWN);
#endif
asm volatile (
"b 0\n"
);
}

/tags/0.2.0/kernel/arch/ppc32/src/drivers/pic.c
0,0 → 1,85
/*
* Copyright (C) 2006 Ondrej Palkovsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/asm.h>
#include <arch/drivers/pic.h>
#include <byteorder.h>
#include <bitops.h>
static volatile __u32 *pic;
void pic_init(void)
{
pic = (__u32 *)hw_map(PIC_HW_ADDR, PAGE_SIZE);
}
void pic_enable_interrupt(int intnum)
{
if (intnum < 32) {
pic[PIC_MASK_LOW] = pic[PIC_MASK_LOW] | (1 << intnum);
} else {
pic[PIC_MASK_HIGH] = pic[PIC_MASK_HIGH] | (1 << (intnum - 32));
}
}
void pic_disable_interrupt(int intnum)
{
if (intnum < 32) {
pic[PIC_MASK_LOW] = pic[PIC_MASK_LOW] & (~(1 << intnum));
} else {
pic[PIC_MASK_HIGH] = pic[PIC_MASK_HIGH] & (~(1 << (intnum - 32)));
}
}
void pic_ack_interrupt(int intnum)
{
if (intnum < 32)
pic[PIC_ACK_LOW] = 1 << intnum;
else
pic[PIC_ACK_HIGH] = 1 << (intnum - 32);
}
/** Return number of pending interrupt */
int pic_get_pending(void)
{
int pending;
pending = pic[PIC_PENDING_LOW];
if (pending) {
return fnzb32(pending);
}
pending = pic[PIC_PENDING_HIGH];
if (pending) {
return fnzb32(pending) + 32;
}
return -1;
}

/tags/0.2.0/kernel/arch/ppc32/src/ppc32.c
0,0 → 1,112
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <arch/boot/boot.h>
#include <arch/drivers/cuda.h>
#include <arch/mm/memory_init.h>
#include <arch/interrupt.h>
#include <genarch/fb/fb.h>
#include <userspace.h>
#include <proc/uarg.h>
#include <console/console.h>
#include <arch/drivers/pic.h>
bootinfo_t bootinfo;
void arch_pre_main(void)
{
/* Setup usermode */
init.cnt = bootinfo.taskmap.count;
__u32 i;
for (i = 0; i < bootinfo.taskmap.count; i++) {
init.tasks[i].addr = PA2KA(bootinfo.taskmap.tasks[i].addr);
init.tasks[i].size = bootinfo.taskmap.tasks[i].size;
}
}
void arch_pre_mm_init(void)
{
/* Initialize dispatch table */
interrupt_init();
/* Start decrementer */
start_decrementer();
}
void arch_post_mm_init(void)
{
if (config.cpu_active == 1) {
fb_init(bootinfo.screen.addr, bootinfo.screen.width, bootinfo.screen.height, bootinfo.screen.bpp, bootinfo.screen.scanline);
/* Initialize PIC */
pic_init();
cuda_init(bootinfo.keyboard.addr, bootinfo.keyboard.size);
/* Merge all zones to 1 big zone */
zone_merge_all();
}
}
void arch_pre_smp_init(void)
{
memory_print_map();
}
void arch_post_smp_init(void)
{
}
void calibrate_delay_loop(void)
{
}
void userspace(uspace_arg_t *kernel_uarg)
{
userspace_asm((__address) kernel_uarg->uspace_uarg, (__address) kernel_uarg->uspace_stack + THREAD_STACK_SIZE - SP_DELTA, (__address) kernel_uarg->uspace_entry);
/* Unreachable */
for (;;)
;
}
/** Acquire console back for kernel
*
*/
void arch_grab_console(void)
{
}
/** Return console to userspace
*
*/
void arch_release_console(void)
{
}

/tags/0.2.0/kernel/arch/ppc32/src/exception.S
0,0 → 1,300
#
# Copyright (C) 2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/regname.h>
#include <arch/mm/page.h>
.section K_UNMAPPED_TEXT_START, "ax"
.macro CONTEXT_STORE
# save R12 in SPRG1, backup CR in R12
# save SP in SPRG2
mtsprg1 r12
mfcr r12
mtsprg2 sp
# check whether SP is in kernel
andis. sp, sp, 0x8000
bne 1f
# stack is in user-space
mfsprg0 sp
b 2f
1:
# stack is in kernel
mfsprg2 sp
subis sp, sp, 0x8000
2:
subi sp, sp, 160
stw r0, 8(sp)
stw r2, 12(sp)
stw r3, 16(sp)
stw r4, 20(sp)
stw r5, 24(sp)
stw r6, 28(sp)
stw r7, 32(sp)
stw r8, 36(sp)
stw r9, 40(sp)
stw r10, 44(sp)
stw r11, 48(sp)
stw r13, 52(sp)
stw r14, 56(sp)
stw r15, 60(sp)
stw r16, 64(sp)
stw r17, 68(sp)
stw r18, 72(sp)
stw r19, 76(sp)
stw r20, 80(sp)
stw r21, 84(sp)
stw r22, 88(sp)
stw r23, 92(sp)
stw r24, 96(sp)
stw r25, 100(sp)
stw r26, 104(sp)
stw r27, 108(sp)
stw r28, 112(sp)
stw r29, 116(sp)
stw r30, 120(sp)
stw r31, 124(sp)
stw r12, 128(sp)
mfsrr0 r12
stw r12, 132(sp)
mfsrr1 r12
stw r12, 136(sp)
mflr r12
stw r12, 140(sp)
mfctr r12
stw r12, 144(sp)
mfxer r12
stw r12, 148(sp)
mfsprg1 r12
stw r12, 152(sp)
mfsprg2 r12
stw r12, 156(sp)
.endm
.org 0x060
jump_to_kernel:
lis r12, iret@ha
addi r12, r12, iret@l
mtlr r12
mfmsr r12
ori r12, r12, (msr_ir | msr_dr)@l
mtsrr1 r12
addis sp, sp, 0x8000
mr r4, sp
addi r4, r4, 8
rfi
jump_to_kernel_syscall:
lis r12, syscall_handler@ha
addi r12, r12, syscall_handler@l
mtsrr0 r12
lis r12, iret_syscall@ha
addi r12, r12, iret_syscall@l
mtlr r12
mfmsr r12
ori r12, r12, (msr_ir | msr_dr)@l
mtsrr1 r12
addis sp, sp, 0x8000
rfi
.org 0x100
.global exc_system_reset
exc_system_reset:
CONTEXT_STORE
lis r12, exc_dispatch@ha
addi r12, r12, exc_dispatch@l
mtsrr0 r12
li r3, 0
b jump_to_kernel
.org 0x200
.global exc_machine_check
exc_machine_check:
CONTEXT_STORE
lis r12, exc_dispatch@ha
addi r12, r12, exc_dispatch@l
mtsrr0 r12
li r3, 1
b jump_to_kernel
.org 0x300
.global exc_data_storage
exc_data_storage:
CONTEXT_STORE
lis r12, exc_dispatch@ha
addi r12, r12, exc_dispatch@l
mtsrr0 r12
li r3, 2
b jump_to_kernel
.org 0x400
.global exc_instruction_storage
exc_instruction_storage:
CONTEXT_STORE
lis r12, exc_dispatch@ha
addi r12, r12, exc_dispatch@l
mtsrr0 r12
li r3, 3
b jump_to_kernel
.org 0x500
.global exc_external
exc_external:
CONTEXT_STORE
lis r12, exc_dispatch@ha
addi r12, r12, exc_dispatch@l
mtsrr0 r12
li r3, 4
b jump_to_kernel
.org 0x600
.global exc_alignment
exc_alignment:
CONTEXT_STORE
lis r12, exc_dispatch@ha
addi r12, r12, exc_dispatch@l
mtsrr0 r12
li r3, 5
b jump_to_kernel
.org 0x700
.global exc_program
exc_program:
CONTEXT_STORE
lis r12, exc_dispatch@ha
addi r12, r12, exc_dispatch@l
mtsrr0 r12
li r3, 6
b jump_to_kernel
.org 0x800
.global exc_fp_unavailable
exc_fp_unavailable:
CONTEXT_STORE
lis r12, exc_dispatch@ha
addi r12, r12, exc_dispatch@l
mtsrr0 r12
li r3, 7
b jump_to_kernel
.org 0x900
.global exc_decrementer
exc_decrementer:
CONTEXT_STORE
lis r12, exc_dispatch@ha
addi r12, r12, exc_dispatch@l
mtsrr0 r12
li r3, 8
b jump_to_kernel
.org 0xa00
.global exc_reserved0
exc_reserved0:
CONTEXT_STORE
lis r12, exc_dispatch@ha
addi r12, r12, exc_dispatch@l
mtsrr0 r12
li r3, 9
b jump_to_kernel
.org 0xb00
.global exc_reserved1
exc_reserved1:
CONTEXT_STORE
lis r12, exc_dispatch@ha
addi r12, r12, exc_dispatch@l
mtsrr0 r12
li r3, 10
b jump_to_kernel
.org 0xc00
.global exc_syscall
exc_syscall:
CONTEXT_STORE
b jump_to_kernel_syscall
.org 0xd00
.global exc_trace
exc_trace:
CONTEXT_STORE
lis r12, exc_dispatch@ha
addi r12, r12, exc_dispatch@l
mtsrr0 r12
li r3, 12
b jump_to_kernel

/tags/0.2.0/kernel/arch/ppc32/src/mm/page.c
0,0 → 1,299
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/page.h>
#include <genarch/mm/page_pt.h>
#include <arch/mm/frame.h>
#include <arch/asm.h>
#include <arch/interrupt.h>
#include <mm/frame.h>
#include <mm/page.h>
#include <mm/as.h>
#include <arch.h>
#include <arch/types.h>
#include <arch/exception.h>
#include <align.h>
#include <config.h>
#include <print.h>
#include <symtab.h>
static phte_t *phte;
/** Try to find PTE for faulting address
*
* Try to find PTE for faulting address.
* The as->lock must be held on entry to this function
* if lock is true.
*
* @param as Address space.
* @param lock Lock/unlock the address space.
* @param badvaddr Faulting virtual address.
* @param access Access mode that caused the fault.
* @param istate Pointer to interrupted state.
* @param pfrc Pointer to variable where as_page_fault() return code will be stored.
* @return PTE on success, NULL otherwise.
*
*/
static pte_t *find_mapping_and_check(as_t *as, bool lock, __address badvaddr, int access,
istate_t *istate, int *pfcr)
{
/*
* Check if the mapping exists in page tables.
*/
pte_t *pte = page_mapping_find(as, badvaddr);
if ((pte) && (pte->p)) {
/*
* Mapping found in page tables.
* Immediately succeed.
*/
return pte;
} else {
int rc;
/*
* Mapping not found in page tables.
* Resort to higher-level page fault handler.
*/
page_table_unlock(as, lock);
switch (rc = as_page_fault(badvaddr, access, istate)) {
case AS_PF_OK:
/*
* The higher-level page fault handler succeeded,
* The mapping ought to be in place.
*/
page_table_lock(as, lock);
pte = page_mapping_find(as, badvaddr);
ASSERT((pte) && (pte->p));
return pte;
case AS_PF_DEFER:
page_table_lock(as, lock);
*pfcr = rc;
return NULL;
case AS_PF_FAULT:
page_table_lock(as, lock);
printf("Page fault.\n");
*pfcr = rc;
return NULL;
default:
panic("unexpected rc (%d)\n", rc);
}
}
}
static void pht_refill_fail(__address badvaddr, istate_t *istate)
{
char *symbol = "";
char *sym2 = "";
char *s = get_symtab_entry(istate->pc);
if (s)
symbol = s;
s = get_symtab_entry(istate->lr);
if (s)
sym2 = s;
panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, istate->pc, symbol, sym2);
}
static void pht_insert(const __address vaddr, const pfn_t pfn)
{
__u32 page = (vaddr >> 12) & 0xffff;
__u32 api = (vaddr >> 22) & 0x3f;
__u32 vsid;
asm volatile (
"mfsrin %0, %1\n"
: "=r" (vsid)
: "r" (vaddr)
);
/* Primary hash (xor) */
__u32 h = 0;
__u32 hash = vsid ^ page;
__u32 base = (hash & 0x3ff) << 3;
__u32 i;
bool found = false;
/* Find unused or colliding
PTE in PTEG */
for (i = 0; i < 8; i++) {
if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) && (phte[base + i].api == api))) {
found = true;
break;
}
}
if (!found) {
/* Secondary hash (not) */
__u32 base2 = (~hash & 0x3ff) << 3;
/* Find unused or colliding
PTE in PTEG */
for (i = 0; i < 8; i++) {
if ((!phte[base2 + i].v) || ((phte[base2 + i].vsid == vsid) && (phte[base2 + i].api == api))) {
found = true;
base = base2;
h = 1;
break;
}
}
if (!found) {
// TODO: A/C precedence groups
i = page % 8;
}
}
phte[base + i].v = 1;
phte[base + i].vsid = vsid;
phte[base + i].h = h;
phte[base + i].api = api;
phte[base + i].rpn = pfn;
phte[base + i].r = 0;
phte[base + i].c = 0;
phte[base + i].pp = 2; // FIXME
}
/** Process Instruction/Data Storage Interrupt
*
* @param data True if Data Storage Interrupt.
* @param istate Interrupted register context.
*
*/
void pht_refill(int n, istate_t *istate)
{
__address badvaddr;
pte_t *pte;
int pfcr;
as_t *as;
bool lock;
if (AS == NULL) {
as = AS_KERNEL;
lock = false;
} else {
as = AS;
lock = true;
}
if (n == VECTOR_DATA_STORAGE) {
asm volatile (
"mfdar %0\n"
: "=r" (badvaddr)
);
} else
badvaddr = istate->pc;
page_table_lock(as, lock);
pte = find_mapping_and_check(as, lock, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pfcr);
if (!pte) {
switch (pfcr) {
case AS_PF_FAULT:
goto fail;
break;
case AS_PF_DEFER:
/*
* The page fault came during copy_from_uspace()
* or copy_to_uspace().
*/
page_table_unlock(as, lock);
return;
default:
panic("Unexpected pfrc (%d)\n", pfcr);
}
}
pte->a = 1; /* Record access to PTE */
pht_insert(badvaddr, pte->pfn);
page_table_unlock(as, lock);
return;
fail:
page_table_unlock(as, lock);
pht_refill_fail(badvaddr, istate);
}
void pht_init(void)
{
memsetb((__address) phte, 1 << PHT_BITS, 0);
}
void page_arch_init(void)
{
if (config.cpu_active == 1) {
page_mapping_operations = &pt_mapping_operations;
__address cur;
int flags;
/* Frames below 128 MB are mapped using BAT,
map rest of the physical memory */
for (cur = 128 << 20; cur < last_frame; cur += FRAME_SIZE) {
flags = PAGE_CACHEABLE;
if ((PA2KA(cur) >= config.base) && (PA2KA(cur) < config.base + config.kernel_size))
flags |= PAGE_GLOBAL;
page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
}
/* Allocate page hash table */
phte_t *physical_phte = (phte_t *) PFN2ADDR(frame_alloc(PHT_ORDER, FRAME_KA | FRAME_PANIC));
phte = (phte_t *) PA2KA((__address) physical_phte);
ASSERT((__address) physical_phte % (1 << PHT_BITS) == 0);
pht_init();
asm volatile (
"mtsdr1 %0\n"
:
: "r" ((__address) physical_phte)
);
}
}
__address hw_map(__address physaddr, size_t size)
{
if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
panic("Unable to map physical memory %p (%d bytes)", physaddr, size)
__address virtaddr = PA2KA(last_frame);
pfn_t i;
for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++)
page_mapping_insert(AS_KERNEL, virtaddr + PFN2ADDR(i), physaddr + PFN2ADDR(i), PAGE_NOT_CACHEABLE);
last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE);
return virtaddr;
}

/tags/0.2.0/kernel/arch/ppc32/src/mm/tlb.c
0,0 → 1,77
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <mm/tlb.h>
/** Initialize Page Hash Table.
*
* Setup the Page Hash Table with no entries.
*
*/
void tlb_arch_init(void)
{
tlb_invalidate_all();
}
void tlb_invalidate_all(void)
{
asm volatile (
"tlbia\n"
"tlbsync\n"
);
}
/** Invalidate all entries in TLB that belong to specified address space.
*
* @param asid This parameter is ignored as the architecture doesn't support it.
*/
void tlb_invalidate_asid(asid_t asid)
{
tlb_invalidate_all();
}
/** Invalidate TLB entries for specified page range belonging to specified address space.
*
* @param asid This parameter is ignored as the architecture doesn't support it.
* @param page Address of the first page whose entry is to be invalidated.
* @param cnt Number of entries to invalidate.
*/
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
tlb_invalidate_all();
}
/** Print contents of Page Hash Table. */
void tlb_print(void)
{
}

/tags/0.2.0/kernel/arch/ppc32/src/mm/frame.c
0,0 → 1,62
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/boot/boot.h>
#include <arch/mm/frame.h>
#include <arch/mm/memory_init.h>
#include <mm/frame.h>
#include <align.h>
#include <macros.h>
__address last_frame = 0;
void frame_arch_init(void)
{
pfn_t minconf = 2;
count_t i;
pfn_t start, conf;
size_t size;
for (i = 0; i < bootinfo.memmap.count; i++) {
start = ADDR2PFN(ALIGN_UP(bootinfo.memmap.zones[i].start, FRAME_SIZE));
size = SIZE2FRAMES(ALIGN_DOWN(bootinfo.memmap.zones[i].size, FRAME_SIZE));
if ((minconf < start) || (minconf >= start + size))
conf = start;
else
conf = minconf;
zone_create(start, size, conf, 0);
if (last_frame < ALIGN_UP(bootinfo.memmap.zones[i].start + bootinfo.memmap.zones[i].size, FRAME_SIZE))
last_frame = ALIGN_UP(bootinfo.memmap.zones[i].start + bootinfo.memmap.zones[i].size, FRAME_SIZE);
}
/* First is exception vector, second is 'implementation specific', third and fourth is reserved */
frame_mark_unavailable(0, 4);
}

/tags/0.2.0/kernel/arch/ppc32/src/mm/memory_init.c
0,0 → 1,47
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/boot/boot.h>
#include <arch/mm/memory_init.h>
#include <typedefs.h>
#include <print.h>
size_t get_memory_size(void)
{
return bootinfo.memmap.total;
}
void memory_print_map(void)
{
count_t i;
for (i = 0; i < bootinfo.memmap.count; i++)
printf("base: %#x size: %#x\n", bootinfo.memmap.zones[i].start, bootinfo.memmap.zones[i].size);
}

/tags/0.2.0/kernel/arch/ppc32/src/mm/as.c
0,0 → 1,36
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/as.h>
#include <genarch/mm/as_pt.h>
/** Architecture dependent address space init. */
void as_arch_init(void)
{
as_operations = &as_pt_operations;
}

/tags/0.2.0/kernel/arch/ppc32/src/interrupt.c
0,0 → 1,87
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <interrupt.h>
#include <arch/interrupt.h>
#include <arch/types.h>
#include <arch.h>
#include <time/clock.h>
#include <ipc/sysipc.h>
#include <arch/drivers/pic.h>
void start_decrementer(void)
{
asm volatile (
"mtdec %0\n"
:
: "r" (1000)
);
}
/** Handler of external interrupts */
static void exception_external(int n, istate_t *istate)
{
int inum;
while ((inum = pic_get_pending()) != -1) {
exc_dispatch(inum + INT_OFFSET, istate);
pic_ack_interrupt(inum);
}
}
static void exception_decrementer(int n, istate_t *istate)
{
clock();
start_decrementer();
}
/* Initialize basic tables for exception dispatching */
void interrupt_init(void)
{
exc_register(VECTOR_DATA_STORAGE, "data_storage", pht_refill);
exc_register(VECTOR_INSTRUCTION_STORAGE, "instruction_storage", pht_refill);
exc_register(VECTOR_EXTERNAL, "external", exception_external);
exc_register(VECTOR_DECREMENTER, "timer", exception_decrementer);
}
static void ipc_int(int n, istate_t *istate)
{
ipc_irq_send_notif(n - INT_OFFSET);
}
/* Reregister irq to be IPC-ready */
void irq_ipc_bind_arch(__native irq)
{
int_register(irq, "ipc_int", ipc_int);
}

/tags/0.2.0/kernel/arch/ppc32/src/asm.S
0,0 → 1,311
#
# Copyright (C) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/regname.h>
.text
.global userspace_asm
.global iret
.global iret_syscall
.global memsetb
.global memcpy
.global memcpy_from_uspace
.global memcpy_to_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace_failover_address
userspace_asm:
# r3 = uspace_uarg
# r4 = stack
# r5 = entry
# disable interrupts
mfmsr r31
rlwinm r31, r31, 0, 17, 15
mtmsr r31
# set entry point
mtsrr0 r5
# set problem state, enable interrupts
ori r31, r31, msr_pr
ori r31, r31, msr_ee
mtsrr1 r31
# set stack
mr sp, r4
# jump to userspace
rfi
iret:
# disable interrupts
mfmsr r31
rlwinm r31, r31, 0, 17, 15
mtmsr r31
lwz r0, 8(sp)
lwz r2, 12(sp)
lwz r3, 16(sp)
lwz r4, 20(sp)
lwz r5, 24(sp)
lwz r6, 28(sp)
lwz r7, 32(sp)
lwz r8, 36(sp)
lwz r9, 40(sp)
lwz r10, 44(sp)
lwz r11, 48(sp)
lwz r13, 52(sp)
lwz r14, 56(sp)
lwz r15, 60(sp)
lwz r16, 64(sp)
lwz r17, 68(sp)
lwz r18, 72(sp)
lwz r19, 76(sp)
lwz r20, 80(sp)
lwz r21, 84(sp)
lwz r22, 88(sp)
lwz r23, 92(sp)
lwz r24, 96(sp)
lwz r25, 100(sp)
lwz r26, 104(sp)
lwz r27, 108(sp)
lwz r28, 112(sp)
lwz r29, 116(sp)
lwz r30, 120(sp)
lwz r31, 124(sp)
lwz r12, 128(sp)
mtcr r12
lwz r12, 132(sp)
mtsrr0 r12
lwz r12, 136(sp)
mtsrr1 r12
lwz r12, 140(sp)
mtlr r12
lwz r12, 144(sp)
mtctr r12
lwz r12, 148(sp)
mtxer r12
lwz r12, 152(sp)
lwz sp, 156(sp)
rfi
iret_syscall:
# reset decrementer
li r31, 1000
mtdec r31
# disable interrupts
mfmsr r31
rlwinm r31, r31, 0, 17, 15
mtmsr r31
lwz r0, 8(sp)
lwz r2, 12(sp)
lwz r4, 20(sp)
lwz r5, 24(sp)
lwz r6, 28(sp)
lwz r7, 32(sp)
lwz r8, 36(sp)
lwz r9, 40(sp)
lwz r10, 44(sp)
lwz r11, 48(sp)
lwz r13, 52(sp)
lwz r14, 56(sp)
lwz r15, 60(sp)
lwz r16, 64(sp)
lwz r17, 68(sp)
lwz r18, 72(sp)
lwz r19, 76(sp)
lwz r20, 80(sp)
lwz r21, 84(sp)
lwz r22, 88(sp)
lwz r23, 92(sp)
lwz r24, 96(sp)
lwz r25, 100(sp)
lwz r26, 104(sp)
lwz r27, 108(sp)
lwz r28, 112(sp)
lwz r29, 116(sp)
lwz r30, 120(sp)
lwz r31, 124(sp)
lwz r12, 128(sp)
mtcr r12
lwz r12, 132(sp)
mtsrr0 r12
lwz r12, 136(sp)
mtsrr1 r12
lwz r12, 140(sp)
mtlr r12
lwz r12, 144(sp)
mtctr r12
lwz r12, 148(sp)
mtxer r12
lwz r12, 152(sp)
lwz sp, 156(sp)
rfi
memsetb:
rlwimi r5, r5, 8, 16, 23
rlwimi r5, r5, 16, 0, 15
addi r14, r3, -4
cmplwi 0, r4, 4
blt 7f
stwu r5, 4(r14)
beqlr
andi. r15, r14, 3
add r4, r15, r4
subf r14, r15, r14
srwi r15, r4, 2
mtctr r15
bdz 6f
1:
stwu r5, 4(r14)
bdnz 1b
6:
andi. r4, r4, 3
7:
cmpwi 0, r4, 0
beqlr
mtctr r4
addi r6, r6, 3
8:
stbu r5, 1(r14)
bdnz 8b
blr
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
srwi. r7, r5, 3
addi r6, r3, -4
addi r4, r4, -4
beq 2f
andi. r0, r6, 3
mtctr r7
bne 5f
1:
lwz r7, 4(r4)
lwzu r8, 8(r4)
stw r7, 4(r6)
stwu r8, 8(r6)
bdnz 1b
andi. r5, r5, 7
2:
cmplwi 0, r5, 4
blt 3f
lwzu r0, 4(r4)
addi r5, r5, -4
stwu r0, 4(r6)
3:
cmpwi 0, r5, 0
beqlr
mtctr r5
addi r4, r4, 3
addi r6, r6, 3
4:
lbzu r0, 1(r4)
stbu r0, 1(r6)
bdnz 4b
blr
5:
subfic r0, r0, 4
mtctr r0
6:
lbz r7, 4(r4)
addi r4, r4, 1
stb r7, 4(r6)
addi r6, r6, 1
bdnz 6b
subf r5, r0, r5
rlwinm. r7, r5, 32-3, 3, 31
beq 2b
mtctr r7
b 1b
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
b memcpy_from_uspace_failover_address

/tags/0.2.0/kernel/arch/ppc32/src/proc/scheduler.c
0,0 → 1,54
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/page.h>
#include <arch/boot/boot.h>
#include <proc/scheduler.h>
#include <proc/thread.h>
#include <arch.h>
/** Perform ppc32 specific tasks needed before the new task is run. */
void before_task_runs_arch(void)
{
}
/** Perform ppc32 specific tasks needed before the new thread is scheduled. */
void before_thread_runs_arch(void)
{
pht_init();
tlb_invalidate_all();
asm volatile (
"mtsprg0 %0\n"
:
: "r" (KA2PA(&THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA]))
);
}
void after_thread_ran_arch(void)
{
}

/tags/0.2.0/kernel/arch/ppc32/src/dummy.s
0,0 → 1,38
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
.global asm_delay_loop
.global sys_tls_set
sys_tls_set:
b sys_tls_set
asm_delay_loop:
blr

/tags/0.2.0/kernel/arch/ppc32/src/ddi/ddi.c
0,0 → 1,47
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <ddi/ddi.h>
#include <proc/task.h>
#include <arch/types.h>
#include <typedefs.h>
/** Enable I/O space range for task.
*
* Interrupts are disabled and task is locked.
*
* @param task Task.
* @param ioaddr Startign I/O space address.
* @param size Size of the enabled I/O range.
*
* @return 0 on success or an error code from errno.h.
*/
int ddi_iospace_enable_arch(task_t *task, __address ioaddr, size_t size)
{
return 0;
}

/tags/0.2.0/kernel/arch/ppc32/src/boot/boot.S
0,0 → 1,81
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/regname.h>
#include <arch/boot/boot.h>
.section K_TEXT_START, "ax"
.global kernel_image_start
kernel_image_start:
# load temporal kernel stack
lis sp, kernel_stack@ha
addi sp, sp, kernel_stack@l
# set kernel stack for interrupt handling
mr r31, sp
subis r31, r31, 0x8000
mtsprg0 r31
# r3 contains physical address of bootinfo_t
# r4 contains size of bootinfo_t
addis r3, r3, 0x8000
lis r31, bootinfo@ha
addi r31, r31, bootinfo@l # r31 = bootinfo
cmpwi r4, 0
beq bootinfo_end
bootinfo_loop:
lwz r30, 0(r3)
stw r30, 0(r31)
addi r3, r3, 4
addi r31, r31, 4
subi r4, r4, 4
cmpwi r4, 0
bgt bootinfo_loop
bootinfo_end:
bl arch_pre_main
b main_bsp
.section K_DATA_START, "aw", @progbits
.align 12
kernel_stack_bottom:
.space TEMP_STACK_SIZE
kernel_stack:

/tags/0.2.0/kernel/arch/ppc32/src/fpu_context.S
0,0 → 1,105
#
# Copyright (C) 2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/regname.h>
#include <arch/context_offset.h>
.text
.global fpu_context_save
.global fpu_context_restore
.global fpu_init
.global fpu_enable
.global fpu_disable
.macro FPU_CONTEXT_STORE r
stfd fr14, OFFSET_FR14(\r)
stfd fr15, OFFSET_FR15(\r)
stfd fr16, OFFSET_FR16(\r)
stfd fr17, OFFSET_FR17(\r)
stfd fr18, OFFSET_FR18(\r)
stfd fr19, OFFSET_FR19(\r)
stfd fr20, OFFSET_FR20(\r)
stfd fr21, OFFSET_FR21(\r)
stfd fr22, OFFSET_FR22(\r)
stfd fr23, OFFSET_FR23(\r)
stfd fr24, OFFSET_FR24(\r)
stfd fr25, OFFSET_FR25(\r)
stfd fr26, OFFSET_FR26(\r)
stfd fr27, OFFSET_FR27(\r)
stfd fr28, OFFSET_FR28(\r)
stfd fr29, OFFSET_FR29(\r)
stfd fr30, OFFSET_FR30(\r)
stfd fr31, OFFSET_FR31(\r)
.endm
.macro FPU_CONTEXT_LOAD r
lfd fr14, OFFSET_FR14(\r)
lfd fr15, OFFSET_FR15(\r)
lfd fr16, OFFSET_FR16(\r)
lfd fr17, OFFSET_FR17(\r)
lfd fr18, OFFSET_FR18(\r)
lfd fr19, OFFSET_FR19(\r)
lfd fr20, OFFSET_FR20(\r)
lfd fr21, OFFSET_FR21(\r)
lfd fr22, OFFSET_FR22(\r)
lfd fr23, OFFSET_FR23(\r)
lfd fr24, OFFSET_FR24(\r)
lfd fr25, OFFSET_FR25(\r)
lfd fr26, OFFSET_FR26(\r)
lfd fr27, OFFSET_FR27(\r)
lfd fr28, OFFSET_FR28(\r)
lfd fr29, OFFSET_FR29(\r)
lfd fr30, OFFSET_FR30(\r)
lfd fr31, OFFSET_FR31(\r)
.endm
fpu_context_save:
// FPU_CONTEXT_STORE r3
//
// mffs fr0
// stfd fr0, OFFSET_FPSCR(r3)
blr
fpu_context_restore:
// FPU_CONTEXT_LOAD r3
//
// lfd fr0, OFFSET_FPSCR(r3)
// mtfsf 7, fr0
blr
fpu_init:
blr
fpu_enable:
blr
fpu_disable:
blr

/tags/0.2.0/kernel/arch/ppc32/src/cpu/cpu.c
0,0 → 1,54
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/cpu.h>
#include <arch/cpuid.h>
#include <cpu.h>
#include <arch.h>
#include <typedefs.h>
#include <print.h>
void cpu_arch_init(void)
{
}
void cpu_identify(void)
{
cpu_info_t info;
cpu_version(&info);
CPU->arch.version = info.version;
CPU->arch.revision = info.revision;
}
void cpu_print_report(cpu_t *m)
{
printf("cpu%d: version=%d, revision=%d\n", m->id, m->arch.version, m->arch.revision);
}

/tags/0.2.0/kernel/arch/ppc32/src/context.S
0,0 → 1,109
#
# Copyright (C) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/regname.h>
#include <arch/context_offset.h>
.text
.global context_save_arch
.global context_restore_arch
.macro CONTEXT_STORE r
stw sp, OFFSET_SP(\r)
stw r2, OFFSET_R2(\r)
stw r13, OFFSET_R13(\r)
stw r14, OFFSET_R14(\r)
stw r15, OFFSET_R15(\r)
stw r16, OFFSET_R16(\r)
stw r17, OFFSET_R17(\r)
stw r18, OFFSET_R18(\r)
stw r19, OFFSET_R19(\r)
stw r20, OFFSET_R20(\r)
stw r21, OFFSET_R21(\r)
stw r22, OFFSET_R22(\r)
stw r23, OFFSET_R23(\r)
stw r24, OFFSET_R24(\r)
stw r25, OFFSET_R25(\r)
stw r26, OFFSET_R26(\r)
stw r27, OFFSET_R27(\r)
stw r28, OFFSET_R28(\r)
stw r29, OFFSET_R29(\r)
stw r30, OFFSET_R30(\r)
stw r31, OFFSET_R31(\r)
.endm
.macro CONTEXT_LOAD r
lwz sp, OFFSET_SP(\r)
lwz r2, OFFSET_R2(\r)
lwz r13, OFFSET_R13(\r)
lwz r14, OFFSET_R14(\r)
lwz r15, OFFSET_R15(\r)
lwz r16, OFFSET_R16(\r)
lwz r17, OFFSET_R17(\r)
lwz r18, OFFSET_R18(\r)
lwz r19, OFFSET_R19(\r)
lwz r20, OFFSET_R20(\r)
lwz r21, OFFSET_R21(\r)
lwz r22, OFFSET_R22(\r)
lwz r23, OFFSET_R23(\r)
lwz r24, OFFSET_R24(\r)
lwz r25, OFFSET_R25(\r)
lwz r26, OFFSET_R26(\r)
lwz r27, OFFSET_R27(\r)
lwz r28, OFFSET_R28(\r)
lwz r29, OFFSET_R29(\r)
lwz r30, OFFSET_R30(\r)
lwz r31, OFFSET_R31(\r)
.endm
context_save_arch:
CONTEXT_STORE r3
mflr r4
stw r4, OFFSET_PC(r3)
mfcr r4
stw r4, OFFSET_CR(r3)
# context_save returns 1
li r3, 1
blr
context_restore_arch:
CONTEXT_LOAD r3
lwz r4, OFFSET_CR(r3)
mtcr r4
lwz r4, OFFSET_PC(r3)
mtlr r4
# context_restore returns 0
li r3, 0
blr

/tags/0.2.0/kernel/arch/ppc32/src/debug/panic.s
0,0 → 1,38
#
# Copyright (C) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/macro.h>
.text
.global panic_printf
panic_printf:
lis %r14, halt@ha
addi %r14, %r14, halt@l
mtlr %r14 # fake stack to make printf return to halt
b printf

/tags/0.2.0/kernel/arch/ppc32/Makefile.inc
0,0 → 1,82
#
# Copyright (C) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
## Toolchain configuration
#
BFD_NAME = elf32-powerpc
BFD_ARCH = powerpc:common
BFD = binary
TARGET = ppc-linux-gnu
TOOLCHAIN_DIR = /usr/local/ppc/bin
## Make some default assumptions
#
CFLAGS += -mcpu=powerpc -msoft-float -m32
AFLAGS += -a32
LFLAGS += -no-check-sections -N
DEFS += -D__32_BITS__
## Own configuration directives
#
CONFIG_FB = y
## Compile with hierarchical page tables support.
#
CONFIG_PAGE_PT = y
DEFS += -DCONFIG_PAGE_PT
## Compile with support for software integer division.
#
CONFIG_SOFTINT = y
ARCH_SOURCES = \
arch/$(ARCH)/src/context.S \
arch/$(ARCH)/src/debug/panic.s \
arch/$(ARCH)/src/fpu_context.S \
arch/$(ARCH)/src/boot/boot.S \
arch/$(ARCH)/src/ppc32.c \
arch/$(ARCH)/src/dummy.s \
arch/$(ARCH)/src/exception.S \
arch/$(ARCH)/src/interrupt.c \
arch/$(ARCH)/src/asm.S \
arch/$(ARCH)/src/cpu/cpu.c \
arch/$(ARCH)/src/proc/scheduler.c \
arch/$(ARCH)/src/ddi/ddi.c \
arch/$(ARCH)/src/drivers/cuda.c \
arch/$(ARCH)/src/mm/as.c \
arch/$(ARCH)/src/mm/frame.c \
arch/$(ARCH)/src/mm/memory_init.c \
arch/$(ARCH)/src/mm/page.c \
arch/$(ARCH)/src/mm/tlb.c \
arch/$(ARCH)/src/drivers/pic.c

/tags/0.2.0/kernel/arch/ppc32/_link.ld.in
0,0 → 1,59
/** PPC32 linker script
*
* umapped section:
* kernel text
* kernel data
* mapped section:
* kernel text
* kernel data
*
*/
#define __ASM__
#include <arch/boot/boot.h>
#include <arch/mm/page.h>
ENTRY(kernel_image_start)
OUTPUT_FORMAT("elf32-powerpc")
OUTPUT_ARCH("powerpc:common")
SECTIONS {
.unmapped 0: AT (0) {
unmapped_ktext_start = .;
*(K_UNMAPPED_TEXT_START);
unmapped_ktext_end = .;
unmapped_kdata_start = .;
*(K_UNMAPPED_DATA_START);
unmapped_kdata_start = .;
}
.mapped PA2KA(BOOT_OFFSET): AT (BOOT_OFFSET) {
ktext_start = .;
*(K_TEXT_START);
*(.text);
ktext_end = .;
kdata_start = .;
*(K_DATA_START);
*(.rodata);
*(.rodata.*);
*(.data); /* initialized data */
*(.sdata);
*(.sdata2);
*(.sbss);
hardcoded_ktext_size = .;
LONG(ktext_end - ktext_start);
hardcoded_kdata_size = .;
LONG(kdata_end - kdata_start);
hardcoded_load_address = .;
LONG(PA2KA(BOOT_OFFSET));
*(.bss); /* uninitialized static variables */
*(COMMON); /* global variables */
symbol_table = .;
*(symtab.*); /* Symbol table, must be LAST symbol!*/
kdata_end = .;
}
}

/tags/0.2.0/kernel/arch/ia64/include/interrupt.h
0,0 → 1,138
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_INTERRUPT_H__
#define __ia64_INTERRUPT_H__
#include <typedefs.h>
#include <arch/types.h>
#include <arch/register.h>
#define IRQ_COUNT 257 /* 256 NOT suppotred IRQS*//* TODO */
#define IRQ_KBD 256 /* One simulated interrupt for ski simulator keyboard*/
/** External Interrupt vectors. */
#define INTERRUPT_TIMER 0
#define INTERRUPT_SPURIOUS 15
/** General Exception codes. */
#define GE_ILLEGALOP 0
#define GE_PRIVOP 1
#define GE_PRIVREG 2
#define GE_RESREGFLD 3
#define GE_DISBLDISTRAN 4
#define GE_ILLEGALDEP 8
#define EOI 0 /**< The actual value doesn't matter. */
struct istate {
__r128 f2;
__r128 f3;
__r128 f4;
__r128 f5;
__r128 f6;
__r128 f7;
__r128 f8;
__r128 f9;
__r128 f10;
__r128 f11;
__r128 f12;
__r128 f13;
__r128 f14;
__r128 f15;
__r128 f16;
__r128 f17;
__r128 f18;
__r128 f19;
__r128 f20;
__r128 f21;
__r128 f22;
__r128 f23;
__r128 f24;
__r128 f25;
__r128 f26;
__r128 f27;
__r128 f28;
__r128 f29;
__r128 f30;
__r128 f31;
__address ar_bsp;
__address ar_bspstore;
__address ar_bspstore_new;
__u64 ar_rnat;
__u64 ar_ifs;
__u64 ar_pfs;
__u64 ar_rsc;
__address cr_ifa;
cr_isr_t cr_isr;
__address cr_iipa;
psr_t cr_ipsr;
__address cr_iip;
__u64 pr;
__address sp;
/*
* The following variables are defined only for break_instruction handler.
*/
__u64 in0;
__u64 in1;
__u64 in2;
__u64 in3;
__u64 in4;
};
static inline void istate_set_retaddr(istate_t *istate, __address retaddr)
{
istate->cr_iip = retaddr;
istate->cr_ipsr.ri = 0; /* return to instruction slot #0 */
}
static inline __native istate_get_pc(istate_t *istate)
{
return istate->cr_iip;
}
#include <panic.h>
static inline int istate_from_uspace(istate_t *istate)
{
return (istate->cr_iip)<0xe000000000000000ULL;
}
extern void *ivt;
extern void general_exception(__u64 vector, istate_t *istate);
extern int break_instruction(__u64 vector, istate_t *istate);
extern void universal_handler(__u64 vector, istate_t *istate);
extern void nop_handler(__u64 vector, istate_t *istate);
extern void external_interrupt(__u64 vector, istate_t *istate);
extern void virtual_interrupt(__u64 irq, void *param);
extern void disabled_fp_register(__u64 vector, istate_t *istate);
#endif

/tags/0.2.0/kernel/arch/ia64/include/proc/task.h
0,0 → 1,38
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_TASK_H__
#define __ia64_TASK_H__
typedef struct {
} task_arch_t;
#define task_create_arch(t)
#define task_destroy_arch(t)
#endif

/tags/0.2.0/kernel/arch/ia64/include/proc/thread.h
0,0 → 1,37
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_THREAD_H__
#define __ia64_THREAD_H__
typedef struct {
} thread_arch_t;
#define thread_create_arch(t)
#endif

/tags/0.2.0/kernel/arch/ia64/include/mm/as.h
0,0 → 1,43
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_AS_H__
#define __ia64_AS_H__
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0
#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0xe000000000000000ULL
#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffffULL
#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000ULL
#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0xdfffffffffffffffULL
#define USTACK_ADDRESS_ARCH 0x0000000ff0000000ULL
extern void as_arch_init(void);
#endif

/tags/0.2.0/kernel/arch/ia64/include/mm/vhpt.h
0,0 → 1,54
/*
* Copyright (C) 2006 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_VHPT_H__
#define __ia64_VHPT_H__
#include <arch/mm/tlb.h>
#include <arch/mm/page.h>
__address vhpt_set_up(void);
static inline vhpt_entry_t tlb_entry_t2vhpt_entry_t(tlb_entry_t tentry)
{
vhpt_entry_t ventry;
ventry.word[0]=tentry.word[0];
ventry.word[1]=tentry.word[1];
return ventry;
}
void vhpt_mapping_insert(__address va, asid_t asid, tlb_entry_t entry);
void vhpt_invalidate_all(void);
void vhpt_invalidate_asid(asid_t asid);
#endif

/tags/0.2.0/kernel/arch/ia64/include/mm/page.h
0,0 → 1,274
/*
* Copyright (C) 2005 - 2006 Jakub Jermar
* Copyright (C) 2006 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_PAGE_H__
#define __ia64_PAGE_H__
#include <arch/mm/frame.h>
#define PAGE_SIZE FRAME_SIZE
#define PAGE_WIDTH FRAME_WIDTH
#ifdef KERNEL
/** Bit width of the TLB-locked portion of kernel address space. */
#define KERNEL_PAGE_WIDTH 28 /* 256M */
#define PPN_SHIFT 12
#define VRN_SHIFT 61
#define VRN_MASK (7LL << VRN_SHIFT)
#define VA2VRN(va) ((va)>>VRN_SHIFT)
#ifdef __ASM__
#define VRN_KERNEL 7
#else
#define VRN_KERNEL 7LL
#endif
#define REGION_REGISTERS 8
#define KA2PA(x) ((__address) (x-(VRN_KERNEL<<VRN_SHIFT)))
#define PA2KA(x) ((__address) (x+(VRN_KERNEL<<VRN_SHIFT)))
#define VHPT_WIDTH 20 /* 1M */
#define VHPT_SIZE (1 << VHPT_WIDTH)
#define PTA_BASE_SHIFT 15
/** Memory Attributes. */
#define MA_WRITEBACK 0x0
#define MA_UNCACHEABLE 0x4
/** Privilege Levels. Only the most and the least privileged ones are ever used. */
#define PL_KERNEL 0x0
#define PL_USER 0x3
/* Access Rigths. Only certain combinations are used by the kernel. */
#define AR_READ 0x0
#define AR_EXECUTE 0x1
#define AR_WRITE 0x2
#ifndef __ASM__
#include <arch/mm/frame.h>
#include <arch/barrier.h>
#include <genarch/mm/page_ht.h>
#include <arch/mm/asid.h>
#include <arch/types.h>
#include <typedefs.h>
#include <debug.h>
struct vhpt_tag_info {
unsigned long long tag : 63;
unsigned ti : 1;
} __attribute__ ((packed));
union vhpt_tag {
struct vhpt_tag_info tag_info;
unsigned tag_word;
};
struct vhpt_entry_present {
/* Word 0 */
unsigned p : 1;
unsigned : 1;
unsigned ma : 3;
unsigned a : 1;
unsigned d : 1;
unsigned pl : 2;
unsigned ar : 3;
unsigned long long ppn : 38;
unsigned : 2;
unsigned ed : 1;
unsigned ig1 : 11;
/* Word 1 */
unsigned : 2;
unsigned ps : 6;
unsigned key : 24;
unsigned : 32;
/* Word 2 */
union vhpt_tag tag;
/* Word 3 */
__u64 ig3 : 64;
} __attribute__ ((packed));
struct vhpt_entry_not_present {
/* Word 0 */
unsigned p : 1;
unsigned long long ig0 : 52;
unsigned ig1 : 11;
/* Word 1 */
unsigned : 2;
unsigned ps : 6;
unsigned long long ig2 : 56;
/* Word 2 */
union vhpt_tag tag;
/* Word 3 */
__u64 ig3 : 64;
} __attribute__ ((packed));
typedef union vhpt_entry {
struct vhpt_entry_present present;
struct vhpt_entry_not_present not_present;
__u64 word[4];
} vhpt_entry_t;
struct region_register_map {
unsigned ve : 1;
unsigned : 1;
unsigned ps : 6;
unsigned rid : 24;
unsigned : 32;
} __attribute__ ((packed));
typedef union region_register {
struct region_register_map map;
unsigned long long word;
} region_register;
struct pta_register_map {
unsigned ve : 1;
unsigned : 1;
unsigned size : 6;
unsigned vf : 1;
unsigned : 6;
unsigned long long base : 49;
} __attribute__ ((packed));
typedef union pta_register {
struct pta_register_map map;
__u64 word;
} pta_register;
/** Return Translation Hashed Entry Address.
*
* VRN bits are used to read RID (ASID) from one
* of the eight region registers registers.
*
* @param va Virtual address including VRN bits.
*
* @return Address of the head of VHPT collision chain.
*/
static inline __u64 thash(__u64 va)
{
__u64 ret;
__asm__ volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
return ret;
}
/** Return Translation Hashed Entry Tag.
*
* VRN bits are used to read RID (ASID) from one
* of the eight region registers.
*
* @param va Virtual address including VRN bits.
*
* @return The unique tag for VPN and RID in the collision chain returned by thash().
*/
static inline __u64 ttag(__u64 va)
{
__u64 ret;
__asm__ volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
return ret;
}
/** Read Region Register.
*
* @param i Region register index.
*
* @return Current contents of rr[i].
*/
static inline __u64 rr_read(index_t i)
{
__u64 ret;
ASSERT(i < REGION_REGISTERS);
__asm__ volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
return ret;
}
/** Write Region Register.
*
* @param i Region register index.
* @param v Value to be written to rr[i].
*/
static inline void rr_write(index_t i, __u64 v)
{
ASSERT(i < REGION_REGISTERS);
__asm__ volatile (
"mov rr[%0] = %1\n"
:
: "r" (i << VRN_SHIFT), "r" (v)
);
}
/** Read Page Table Register.
*
* @return Current value stored in PTA.
*/
static inline __u64 pta_read(void)
{
__u64 ret;
__asm__ volatile ("mov %0 = cr.pta\n" : "=r" (ret));
return ret;
}
/** Write Page Table Register.
*
* @param v New value to be stored in PTA.
*/
static inline void pta_write(__u64 v)
{
__asm__ volatile ("mov cr.pta = %0\n" : : "r" (v));
}
extern void page_arch_init(void);
extern vhpt_entry_t *vhpt_hash(__address page, asid_t asid);
extern bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v);
extern void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags);
#endif /* __ASM__ */
#endif /* KERNEL */
#endif

/tags/0.2.0/kernel/arch/ia64/include/mm/tlb.h
0,0 → 1,94
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_TLB_H__
#define __ia64_TLB_H__
#define tlb_arch_init()
#define tlb_print()
#include <arch/mm/page.h>
#include <arch/mm/asid.h>
#include <arch/interrupt.h>
#include <arch/types.h>
#include <typedefs.h>
/** Data and instruction Translation Register indices. */
#define DTR_KERNEL 0
#define ITR_KERNEL 0
#define DTR_KSTACK1 1
#define DTR_KSTACK2 2
/** Portion of TLB insertion format data structure. */
union tlb_entry {
__u64 word[2];
struct {
/* Word 0 */
unsigned p : 1; /**< Present. */
unsigned : 1;
unsigned ma : 3; /**< Memory attribute. */
unsigned a : 1; /**< Accessed. */
unsigned d : 1; /**< Dirty. */
unsigned pl : 2; /**< Privilege level. */
unsigned ar : 3; /**< Access rights. */
unsigned long long ppn : 38; /**< Physical Page Number, a.k.a. PFN. */
unsigned : 2;
unsigned ed : 1;
unsigned ig1 : 11;
/* Word 1 */
unsigned : 2;
unsigned ps : 6; /**< Page size will be 2^ps. */
unsigned key : 24; /**< Protection key, unused. */
unsigned : 32;
} __attribute__ ((packed));
} __attribute__ ((packed));
typedef union tlb_entry tlb_entry_t;
extern void tc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtc);
extern void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry);
extern void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry);
extern void tr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr);
extern void dtr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr);
extern void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr);
extern void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr);
extern void dtc_pte_copy(pte_t *t);
extern void itc_pte_copy(pte_t *t);
extern void alternate_instruction_tlb_fault(__u64 vector, istate_t *istate);
extern void alternate_data_tlb_fault(__u64 vector, istate_t *istate);
extern void data_nested_tlb_fault(__u64 vector, istate_t *istate);
extern void data_dirty_bit_fault(__u64 vector, istate_t *istate);
extern void instruction_access_bit_fault(__u64 vector, istate_t *istate);
extern void data_access_bit_fault(__u64 vector, istate_t *istate);
extern void page_not_present(__u64 vector, istate_t *istate);
#endif

/tags/0.2.0/kernel/arch/ia64/include/mm/frame.h
0,0 → 1,45
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_FRAME_H__
#define __ia64_FRAME_H__
#define FRAME_WIDTH 14 /* 16K */
#define FRAME_SIZE (1<<FRAME_WIDTH)
#ifdef KERNEL
#ifndef __ASM__
extern void frame_arch_init(void);
#define ARCH_STACK_FRAMES TWO_FRAMES
#endif /* __ASM__ */
#endif /* KERNEL */
#endif

/tags/0.2.0/kernel/arch/ia64/include/mm/memory_init.h
0,0 → 1,36
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_MEMORY_INIT_H__
#define __ia64_MEMORY_INIT_H__
#include <config.h>
#define get_memory_size() (512*1024*1024) /* 512M */
#endif

/tags/0.2.0/kernel/arch/ia64/include/mm/asid.h
0,0 → 1,57
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_ASID_H__
#define __ia64_ASID_H__
#ifndef __ASM__
#include <arch/types.h>
typedef __u16 asid_t;
typedef __u32 rid_t;
#endif /* __ASM__ */
/**
* Number of ia64 RIDs (Region Identifiers) per kernel ASID.
* Note that some architectures may support more bits,
* but those extra bits are not used by the kernel.
*/
#define RIDS_PER_ASID 7
#define RID_MAX 262143 /* 2^18 - 1 */
#define RID_KERNEL 0
#define RID_INVALID 1
#define ASID2RID(asid, vrn) (((asid)>RIDS_PER_ASID)?(((asid)*RIDS_PER_ASID)+(vrn)):(asid))
#define RID2ASID(rid) ((rid)/RIDS_PER_ASID)
#define ASID_MAX_ARCH (RID_MAX/RIDS_PER_ASID)
#endif

/tags/0.2.0/kernel/arch/ia64/include/ski/ski.h
0,0 → 1,46
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SKI_H__
#define __SKI_H__
#include <arch/types.h>
#include <console/console.h>
#define SKI_INIT_CONSOLE 20
#define SKI_GETCHAR 21
#define SKI_PUTCHAR 31
extern void ski_init_console(void);
extern void ski_set_console_sysinfo(void);
extern void poll_keyboard(void);
extern chardev_t ski_uconsole;
extern int kbd_uspace;
#endif

/tags/0.2.0/kernel/arch/ia64/include/arch.h
0,0 → 1,36
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_ARCH_H__
#define __ia64_ARCH_H__
#define LOADED_PROG_STACK_PAGES_NO 2
#include <arch/ski/ski.h>
#endif

/tags/0.2.0/kernel/arch/ia64/include/asm.h
0,0 → 1,276
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_ASM_H__
#define __ia64_ASM_H__
#include <config.h>
#include <arch/types.h>
#include <arch/register.h>
/** Return base address of current stack
*
* Return the base address of the current stack.
* The stack is assumed to be STACK_SIZE long.
* The stack must start on page boundary.
*/
static inline __address get_stack_base(void)
{
__u64 v;
__asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
return v;
}
/** Return Processor State Register.
*
* @return PSR.
*/
static inline __u64 psr_read(void)
{
__u64 v;
__asm__ volatile ("mov %0 = psr\n" : "=r" (v));
return v;
}
/** Read IVA (Interruption Vector Address).
*
* @return Return location of interruption vector table.
*/
static inline __u64 iva_read(void)
{
__u64 v;
__asm__ volatile ("mov %0 = cr.iva\n" : "=r" (v));
return v;
}
/** Write IVA (Interruption Vector Address) register.
*
* @param New location of interruption vector table.
*/
static inline void iva_write(__u64 v)
{
__asm__ volatile ("mov cr.iva = %0\n" : : "r" (v));
}
/** Read IVR (External Interrupt Vector Register).
*
* @return Highest priority, pending, unmasked external interrupt vector.
*/
static inline __u64 ivr_read(void)
{
__u64 v;
__asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v));
return v;
}
/** Write ITC (Interval Timer Counter) register.
*
* @param New counter value.
*/
static inline void itc_write(__u64 v)
{
__asm__ volatile ("mov ar.itc = %0\n" : : "r" (v));
}
/** Read ITC (Interval Timer Counter) register.
*
* @return Current counter value.
*/
static inline __u64 itc_read(void)
{
__u64 v;
__asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v));
return v;
}
/** Write ITM (Interval Timer Match) register.
*
* @param New match value.
*/
static inline void itm_write(__u64 v)
{
__asm__ volatile ("mov cr.itm = %0\n" : : "r" (v));
}
/** Read ITM (Interval Timer Match) register.
*
* @return Match value.
*/
static inline __u64 itm_read(void)
{
__u64 v;
__asm__ volatile ("mov %0 = cr.itm\n" : "=r" (v));
return v;
}
/** Read ITV (Interval Timer Vector) register.
*
* @return Current vector and mask bit.
*/
static inline __u64 itv_read(void)
{
__u64 v;
__asm__ volatile ("mov %0 = cr.itv\n" : "=r" (v));
return v;
}
/** Write ITV (Interval Timer Vector) register.
*
* @param New vector and mask bit.
*/
static inline void itv_write(__u64 v)
{
__asm__ volatile ("mov cr.itv = %0\n" : : "r" (v));
}
/** Write EOI (End Of Interrupt) register.
*
* @param This value is ignored.
*/
static inline void eoi_write(__u64 v)
{
__asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v));
}
/** Read TPR (Task Priority Register).
*
* @return Current value of TPR.
*/
static inline __u64 tpr_read(void)
{
__u64 v;
__asm__ volatile ("mov %0 = cr.tpr\n" : "=r" (v));
return v;
}
/** Write TPR (Task Priority Register).
*
* @param New value of TPR.
*/
static inline void tpr_write(__u64 v)
{
__asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v));
}
/** Disable interrupts.
*
* Disable interrupts and return previous
* value of PSR.
*
* @return Old interrupt priority level.
*/
static ipl_t interrupts_disable(void)
{
__u64 v;
__asm__ volatile (
"mov %0 = psr\n"
"rsm %1\n"
: "=r" (v)
: "i" (PSR_I_MASK)
);
return (ipl_t) v;
}
/** Enable interrupts.
*
* Enable interrupts and return previous
* value of PSR.
*
* @return Old interrupt priority level.
*/
static ipl_t interrupts_enable(void)
{
__u64 v;
__asm__ volatile (
"mov %0 = psr\n"
"ssm %1\n"
";;\n"
"srlz.d\n"
: "=r" (v)
: "i" (PSR_I_MASK)
);
return (ipl_t) v;
}
/** Restore interrupt priority level.
*
* Restore PSR.
*
* @param ipl Saved interrupt priority level.
*/
static inline void interrupts_restore(ipl_t ipl)
{
if (ipl & PSR_I_MASK)
(void) interrupts_enable();
else
(void) interrupts_disable();
}
/** Return interrupt priority level.
*
* @return PSR.
*/
static inline ipl_t interrupts_read(void)
{
return (ipl_t) psr_read();
}
/** Disable protection key checking. */
static inline void pk_disable(void)
{
__asm__ volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
}
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(__u32 t);
extern void switch_to_userspace(__address entry, __address sp, __address bsp, __address uspace_uarg, __u64 ipsr, __u64 rsc);
#endif

/tags/0.2.0/kernel/arch/ia64/include/context.h
0,0 → 1,127
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_CONTEXT_H__
#define __ia64_CONTEXT_H__
#include <arch/types.h>
#include <arch/register.h>
#include <typedefs.h>
#include <align.h>
#include <arch/stack.h>
/*
* context_save_arch() and context_restore_arch() are both leaf procedures.
* No need to allocate scratch area.
*
* One item is put onto the stack to support get_stack_base().
*/
#define SP_DELTA (0+ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT))
#ifdef context_set
#undef context_set
#endif
/* RSE stack starts at the bottom of memory stack. */
#define context_set(c, _pc, stack, size) \
do { \
(c)->pc = (__address) _pc; \
(c)->bsp = ((__address) stack) + ALIGN_UP((size), REGISTER_STACK_ALIGNMENT); \
(c)->ar_pfs &= PFM_MASK; \
(c)->sp = ((__address) stack) + ALIGN_UP((size), STACK_ALIGNMENT) - SP_DELTA; \
} while (0);
/*
* Only save registers that must be preserved across
* function calls.
*/
struct context {
/*
* Application registers
*/
__u64 ar_pfs;
__u64 ar_unat_caller;
__u64 ar_unat_callee;
__u64 ar_rsc;
__address bsp; /* ar_bsp */
__u64 ar_rnat;
__u64 ar_lc;
/*
* General registers
*/
__u64 r1;
__u64 r4;
__u64 r5;
__u64 r6;
__u64 r7;
__address sp; /* r12 */
__u64 r13;
/*
* Branch registers
*/
__address pc; /* b0 */
__u64 b1;
__u64 b2;
__u64 b3;
__u64 b4;
__u64 b5;
/*
* Predicate registers
*/
__u64 pr;
__r128 f2 __attribute__ ((aligned(16)));
__r128 f3;
__r128 f4;
__r128 f5;
__r128 f16;
__r128 f17;
__r128 f18;
__r128 f19;
__r128 f20;
__r128 f21;
__r128 f22;
__r128 f23;
__r128 f24;
__r128 f25;
__r128 f26;
__r128 f27;
__r128 f28;
__r128 f29;
__r128 f30;
__r128 f31;
ipl_t ipl;
};
#endif

/tags/0.2.0/kernel/arch/ia64/include/faddr.h
0,0 → 1,44
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_FADDR_H__
#define __ia64_FADDR_H__
#include <arch/types.h>
/**
*
* Calculate absolute address of function
* referenced by fptr pointer.
*
* @param fptr Function pointer.
*
*/
#define FADDR(f) (*((__address *)(f)));
#endif

/tags/0.2.0/kernel/arch/ia64/include/atomic.h
0,0 → 1,57
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_ATOMIC_H__
#define __ia64_ATOMIC_H__
/** Atomic addition.
*
* @param val Atomic value.
* @param imm Value to add.
*
* @return Value before addition.
*/
static inline long atomic_add(atomic_t *val, int imm)
{
long v;
__asm__ volatile ("fetchadd8.rel %0 = %1, %2\n" : "=r" (v), "+m" (val->count) : "i" (imm));
return v;
}
static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); }
static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); }
static inline long atomic_preinc(atomic_t *val) { return atomic_add(val, 1) + 1; }
static inline long atomic_predec(atomic_t *val) { return atomic_add(val, -1) - 1; }
static inline long atomic_postinc(atomic_t *val) { return atomic_add(val, 1); }
static inline long atomic_postdec(atomic_t *val) { return atomic_add(val, -1); }
#endif

/tags/0.2.0/kernel/arch/ia64/include/fpu_context.h
0,0 → 1,44
/*
* Copyright (C) 2005 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_FPU_CONTEXT_H__
#define __ia64_FPU_CONTEXT_H__
#define ARCH_HAS_FPU 1
#define FPU_CONTEXT_ALIGN 16
#include <arch/types.h>
#define FRS 96
struct fpu_context {
__r128 fr[FRS];
};
#endif

/tags/0.2.0/kernel/arch/ia64/include/register.h
0,0 → 1,269
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_REGISTER_H__
#define __ia64_REGISTER_H__
#define CR_IVR_MASK 0xf
#define PSR_IC_MASK 0x2000
#define PSR_I_MASK 0x4000
#define PSR_PK_MASK 0x8000
#define PSR_DT_MASK (1<<17)
#define PSR_RT_MASK (1<<27)
#define PSR_DFL_MASK (1<<18)
#define PSR_DFH_MASK (1<<19)
#define PSR_IT_MASK 0x0000001000000000
#define PSR_CPL_SHIFT 32
#define PSR_CPL_MASK_SHIFTED 3
#define PFM_MASK (~0x3fffffffff)
#define RSC_MODE_MASK 3
#define RSC_PL_MASK 12
/** Application registers. */
#define AR_KR0 0
#define AR_KR1 1
#define AR_KR2 2
#define AR_KR3 3
#define AR_KR4 4
#define AR_KR5 5
#define AR_KR6 6
#define AR_KR7 7
/* AR 8-15 reserved */
#define AR_RSC 16
#define AR_BSP 17
#define AR_BSPSTORE 18
#define AR_RNAT 19
/* AR 20 reserved */
#define AR_FCR 21
/* AR 22-23 reserved */
#define AR_EFLAG 24
#define AR_CSD 25
#define AR_SSD 26
#define AR_CFLG 27
#define AR_FSR 28
#define AR_FIR 29
#define AR_FDR 30
/* AR 31 reserved */
#define AR_CCV 32
/* AR 33-35 reserved */
#define AR_UNAT 36
/* AR 37-39 reserved */
#define AR_FPSR 40
/* AR 41-43 reserved */
#define AR_ITC 44
/* AR 45-47 reserved */
/* AR 48-63 ignored */
#define AR_PFS 64
#define AR_LC 65
#define AR_EC 66
/* AR 67-111 reserved */
/* AR 112-127 ignored */
/** Control registers. */
#define CR_DCR 0
#define CR_ITM 1
#define CR_IVA 2
/* CR3-CR7 reserved */
#define CR_PTA 8
/* CR9-CR15 reserved */
#define CR_IPSR 16
#define CR_ISR 17
/* CR18 reserved */
#define CR_IIP 19
#define CR_IFA 20
#define CR_ITIR 21
#define CR_IIPA 22
#define CR_IFS 23
#define CR_IIM 24
#define CR_IHA 25
/* CR26-CR63 reserved */
#define CR_LID 64
#define CR_IVR 65
#define CR_TPR 66
#define CR_EOI 67
#define CR_IRR0 68
#define CR_IRR1 69
#define CR_IRR2 70
#define CR_IRR3 71
#define CR_ITV 72
#define CR_PMV 73
#define CR_CMCV 74
/* CR75-CR79 reserved */
#define CR_LRR0 80
#define CR_LRR1 81
/* CR82-CR127 reserved */
#ifndef __ASM__
#include <arch/types.h>
/** Processor Status Register. */
union psr {
__u64 value;
struct {
unsigned : 1;
unsigned be : 1; /**< Big-Endian data accesses. */
unsigned up : 1; /**< User Performance monitor enable. */
unsigned ac : 1; /**< Alignment Check. */
unsigned mfl : 1; /**< Lower floating-point register written. */
unsigned mfh : 1; /**< Upper floating-point register written. */
unsigned : 7;
unsigned ic : 1; /**< Interruption Collection. */
unsigned i : 1; /**< Interrupt Bit. */
unsigned pk : 1; /**< Protection Key enable. */
unsigned : 1;
unsigned dt : 1; /**< Data address Translation. */
unsigned dfl : 1; /**< Disabled Floating-point Low register set. */
unsigned dfh : 1; /**< Disabled Floating-point High register set. */
unsigned sp : 1; /**< Secure Performance monitors. */
unsigned pp : 1; /**< Privileged Performance monitor enable. */
unsigned di : 1; /**< Disable Instruction set transition. */
unsigned si : 1; /**< Secure Interval timer. */
unsigned db : 1; /**< Debug Breakpoint fault. */
unsigned lp : 1; /**< Lower Privilege transfer trap. */
unsigned tb : 1; /**< Taken Branch trap. */
unsigned rt : 1; /**< Register Stack Translation. */
unsigned : 4;
unsigned cpl : 2; /**< Current Privilege Level. */
unsigned is : 1; /**< Instruction Set. */
unsigned mc : 1; /**< Machine Check abort mask. */
unsigned it : 1; /**< Instruction address Translation. */
unsigned id : 1; /**< Instruction Debug fault disable. */
unsigned da : 1; /**< Disable Data Access and Dirty-bit faults. */
unsigned dd : 1; /**< Data Debug fault disable. */
unsigned ss : 1; /**< Single Step enable. */
unsigned ri : 2; /**< Restart Instruction. */
unsigned ed : 1; /**< Exception Deferral. */
unsigned bn : 1; /**< Register Bank. */
unsigned ia : 1; /**< Disable Instruction Access-bit faults. */
} __attribute__ ((packed));
};
typedef union psr psr_t;
/** Register Stack Configuration Register */
union rsc {
__u64 value;
struct {
unsigned mode : 2;
unsigned pl : 2; /**< Privilege Level. */
unsigned be : 1; /**< Big-endian. */
unsigned : 11;
unsigned loadrs : 14;
} __attribute__ ((packed));
};
typedef union rsc rsc_t;
/** External Interrupt Vector Register */
union cr_ivr {
__u8 vector;
__u64 value;
};
typedef union cr_ivr cr_ivr_t;
/** Task Priority Register */
union cr_tpr {
struct {
unsigned : 4;
unsigned mic: 4; /**< Mask Interrupt Class. */
unsigned : 8;
unsigned mmi: 1; /**< Mask Maskable Interrupts. */
} __attribute__ ((packed));
__u64 value;
};
typedef union cr_tpr cr_tpr_t;
/** Interval Timer Vector */
union cr_itv {
struct {
unsigned vector : 8;
unsigned : 4;
unsigned : 1;
unsigned : 3;
unsigned m : 1; /**< Mask. */
} __attribute__ ((packed));
__u64 value;
};
typedef union cr_itv cr_itv_t;
/** Interruption Status Register */
union cr_isr {
struct {
union {
/** General Exception code field structuring. */
struct {
unsigned ge_na : 4;
unsigned ge_code : 4;
} __attribute__ ((packed));
__u16 code;
};
__u8 vector;
unsigned : 8;
unsigned x : 1; /**< Execute exception. */
unsigned w : 1; /**< Write exception. */
unsigned r : 1; /**< Read exception. */
unsigned na : 1; /**< Non-access exception. */
unsigned sp : 1; /**< Speculative load exception. */
unsigned rs : 1; /**< Register stack. */
unsigned ir : 1; /**< Incomplete Register frame. */
unsigned ni : 1; /**< Nested Interruption. */
unsigned so : 1; /**< IA-32 Supervisor Override. */
unsigned ei : 2; /**< Excepting Instruction. */
unsigned ed : 1; /**< Exception Deferral. */
unsigned : 20;
} __attribute__ ((packed));
__u64 value;
};
typedef union cr_isr cr_isr_t;
/** CPUID Register 3 */
union cpuid3 {
struct {
__u8 number;
__u8 revision;
__u8 model;
__u8 family;
__u8 archrev;
} __attribute__ ((packed));
__u64 value;
};
typedef union cpuid3 cpuid3_t;
#endif /* !__ASM__ */
#endif

/tags/0.2.0/kernel/arch/ia64/include/types.h
0,0 → 1,62
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __TYPES_H__
#define __TYPES_H__
#define NULL 0
typedef signed char __s8;
typedef signed short int __s16;
typedef signed int __s32;
typedef signed long __s64;
typedef unsigned char __u8;
typedef unsigned short __u16;
typedef unsigned int __u32;
typedef unsigned long __u64;
typedef unsigned char __r8; /*Reserve byte*/
typedef unsigned short __r16;
typedef unsigned int __r32;
typedef unsigned long __r64;
typedef struct __r128{__r64 lo;__r64 hi;} __r128;
typedef __u64 __address;
typedef __u64 pfn_t;
typedef __u64 ipl_t;
typedef __u64 __native;
typedef __s64 __snative;
typedef struct pte pte_t;
#endif

/tags/0.2.0/kernel/arch/ia64/include/elf.h
0,0 → 1,36
/*
* Copyright (C) 2006 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_ELF_H__
#define __ia64_ELF_H__
#define ELF_MACHINE EM_IA_64
#define ELF_DATA_ENCODING ELFDATA2LSB
#define ELF_CLASS ELFCLASS64
#endif

/tags/0.2.0/kernel/arch/ia64/include/pal/pal.h
0,0 → 1,101
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_PAL_H__
#define __ia64_PAL_H__
#define PAL_OK 0 /**< Call completed without error. */
#define PAL_UNIMPL -1 /**< Unimplemented procedure. */
#define PAL_INVARG -2 /**< Invalid argument. */
#define PAL_ERR -3 /**< Can not compete call without error. */
/** These are the indices for PAL_PROC. */
#define PAL_CACHE_FLUSH 1
#define PAL_CACHE_INFO 2
#define PAL_CACHE_INIT 3
#define PAL_CACHE_PROT_INFO 38
#define PAL_CACHE_SHARED_INFO 43
#define PAL_CACHE_SUMMARY 4
#define PAL_MEM_ATTRIB 5
#define PAL_PREFETCH_VISIBILITY 41
#define PAL_PTCE_INFO 6
#define PAL_VM_INFO 7
#define PAL_VM_PAGE_SIZE 34
#define PAL_VM_SUMMARY 8
#define PAL_VM_TR_READ 261
#define PAL_BUS_GET_FEATURES 9
#define PAL_BUS_SET_FEATURES 10
#define PAL_DEBUG_INFO 11
#define PAL_FIXED_ADDR 12
#define PAL_FREQ_BASE 13
#define PAL_FREQ_RATIOS 14
#define PAL_LOGICAL_TO_PHYSICAL 42
#define PAL_PERF_MON_INFO 15
#define PAL_PLATFORM_ADDR 16
#define PAL_PROC_GET_FEATURES 17
#define PAL_PROC_SET_FEATURES 18
#define PAL_REGISTER_INFO 39
#define PAL_RSE_INFO 19
#define PAL_VERSION 20
#define PAL_MC_CLEAR_LOG 21
#define PAL_MC_DRAIN 22
#define PAL_MC_DYNAMIC_STATE 24
#define PAL_MC_ERROR_INFO 25
#define PAL_MC_EXPECTED 23
#define PAL_MC_REGISTER_MEM 27
#define PAL_MC_RESUME 26
#define PAL_HALT 28
#define PAL_HALT_INFO 257
#define PAL_HALT_LIGHT 29
#define PAL_CACHE_LINE_INIT 31
#define PAL_CACHE_READ 259
#define PAL_CACHE_WRITE 260
#define PAL_TEST_INFO 37
#define PAL_TEST_PROC 258
#define PAL_COPY_INFO 30
#define PAL_COPY_PAL 256
#define PAL_ENTER_IA_32_ENV 33
#define PAL_PMI_ENTRYPOINT 32
/*
Ski PTCE data
*/
#define PAL_PTCE_INFO_BASE() (0x100000000LL)
#define PAL_PTCE_INFO_COUNT1() (2)
#define PAL_PTCE_INFO_COUNT2() (3)
#define PAL_PTCE_INFO_STRIDE1() (0x10000000)
#define PAL_PTCE_INFO_STRIDE2() (0x2000)
#endif

/tags/0.2.0/kernel/arch/ia64/include/memstr.h
0,0 → 1,39
/*
* Copyright (C) 2005 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_MEMSTR_H__
#define __ia64_MEMSTR_H__
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt))
extern void memsetw(__address dst, size_t cnt, __u16 x);
extern void memsetb(__address dst, size_t cnt, __u8 x);
extern int memcmp(__address src, __address dst, int cnt);
#endif

/tags/0.2.0/kernel/arch/ia64/include/debug.h
0,0 → 1,32
/*
* Copyright (C) 2005
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_DEBUG_H__
#define __ia64_DEBUG_H__
#endif

/tags/0.2.0/kernel/arch/ia64/include/drivers/it.h
0,0 → 1,43
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_IT_H__
#define __ia64_IT_H__
/*
* Unfortunately, Ski does not emulate PAL,
* so we can't read the real frequency ratios
* from firmware.
*
*/
#define IT_DELTA 100000
extern void it_init(void);
extern void it_interrupt(void);
#endif

/tags/0.2.0/kernel/arch/ia64/include/cpu.h
0,0 → 1,60
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_CPU_H__
#define __ia64_CPU_H__
#include <arch/types.h>
#include <typedefs.h>
#include <arch/register.h>
#define FAMILY_ITANIUM 0x7
#define FAMILY_ITANIUM2 0x1f
struct cpu_arch {
__u64 cpuid0;
__u64 cpuid1;
cpuid3_t cpuid3;
};
/** Read CPUID register.
*
* @param n CPUID register number.
*
* @return Value of CPUID[n] register.
*/
static inline __u64 cpuid_read(int n)
{
__u64 v;
__asm__ volatile ("mov %0 = cpuid[%1]\n" : "=r" (v) : "r" (n));
return v;
}
#endif

/tags/0.2.0/kernel/arch/ia64/include/stack.h
0,0 → 1,37
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_STACK_H__
#define __ia64_STACK_H__
#define STACK_ITEM_SIZE 8
#define STACK_ALIGNMENT 16
#define STACK_SCRATCH_AREA_SIZE 16
#define REGISTER_STACK_ALIGNMENT 8
#endif

/tags/0.2.0/kernel/arch/ia64/include/barrier.h
0,0 → 1,45
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_BARRIER_H__
#define __ia64_BARRIER_H__
/*
* TODO: Implement true IA-64 memory barriers for macros below.
*/
#define CS_ENTER_BARRIER() memory_barrier()
#define CS_LEAVE_BARRIER() memory_barrier()
#define memory_barrier() __asm__ volatile ("mf\n" ::: "memory")
#define read_barrier() memory_barrier()
#define write_barrier() memory_barrier()
#define srlz_i() __asm__ volatile (";; srlz.i ;;\n" ::: "memory")
#define srlz_d() __asm__ volatile (";; srlz.d\n" ::: "memory")
#endif

/tags/0.2.0/kernel/arch/ia64/include/byteorder.h
0,0 → 1,36
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_BYTEORDER_H__
#define __ia64_BYTEORDER_H__
/* IA-64 is little-endian */
#define __native_le2host(n) (n)
#define __u64_le2host(n) (n)
#endif

/tags/0.2.0/kernel/arch/ia64/include/arg.h
0,0 → 1,34
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ia64_ARG_H__
#define __ia64_ARG_H__
#include <stdarg.h>
#endif

/tags/0.2.0/kernel/arch/ia64/include/smp/atomic.h
--- ia64/src/mm/tlb.c (nonexistent)
+++ ia64/src/mm/tlb.c (revision 1968)
@@ -0,0 +1,669 @@
+/*
+ * Copyright (C) 2006 Jakub Jermar
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * TLB management.
+ */
+
+#include <mm/tlb.h>
+#include <mm/asid.h>
+#include <mm/page.h>
+#include <mm/as.h>
+#include <arch/mm/tlb.h>
+#include <arch/mm/page.h>
+#include <arch/mm/vhpt.h>
+#include <arch/barrier.h>
+#include <arch/interrupt.h>
+#include <arch/pal/pal.h>
+#include <arch/asm.h>
+#include <typedefs.h>
+#include <panic.h>
+#include <print.h>
+#include <arch.h>
+#include <interrupt.h>
+
+/** Invalidate all TLB entries. */
+void tlb_invalidate_all(void)
+{
+ ipl_t ipl;
+ __address adr;
+ __u32 count1, count2, stride1, stride2;
+
+ int i,j;
+
+ adr = PAL_PTCE_INFO_BASE();
+ count1 = PAL_PTCE_INFO_COUNT1();
+ count2 = PAL_PTCE_INFO_COUNT2();
+ stride1 = PAL_PTCE_INFO_STRIDE1();
+ stride2 = PAL_PTCE_INFO_STRIDE2();
+
+ ipl = interrupts_disable();
+
+ for(i = 0; i < count1; i++) {
+ for(j = 0; j < count2; j++) {
+ __asm__ volatile (
+ "ptc.e %0 ;;"
+ :
+ : "r" (adr)
+ );
+ adr += stride2;
+ }
+ adr += stride1;
+ }
+
+ interrupts_restore(ipl);
+
+ srlz_d();
+ srlz_i();
+#ifdef CONFIG_VHPT
+ vhpt_invalidate_all();
+#endif
+}
+
+/** Invalidate entries belonging to an address space.
+ *
+ * @param asid Address space identifier.
+ */
+void tlb_invalidate_asid(asid_t asid)
+{
+ tlb_invalidate_all();
+}
+
+
+void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
+{
+ region_register rr;
+ bool restore_rr = false;
+ int b = 0;
+ int c = cnt;
+
+ __address va;
+ va = page;
+
+ rr.word = rr_read(VA2VRN(va));
+ if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
+ /*
+ * The selected region register does not contain required RID.
+ * Save the old content of the register and replace the RID.
+ */
+ region_register rr0;
+
+ rr0 = rr;
+ rr0.map.rid = ASID2RID(asid, VA2VRN(va));
+ rr_write(VA2VRN(va), rr0.word);
+ srlz_d();
+ srlz_i();
+ }
+
+ while(c >>= 1)
+ b++;
+ b >>= 1;
+ __u64 ps;
+
+ switch (b) {
+ case 0: /*cnt 1-3*/
+ ps = PAGE_WIDTH;
+ break;
+ case 1: /*cnt 4-15*/
+ /*cnt=((cnt-1)/4)+1;*/
+ ps = PAGE_WIDTH+2;
+ va &= ~((1<<ps)-1);
+ break;
+ case 2: /*cnt 16-63*/
+ /*cnt=((cnt-1)/16)+1;*/
+ ps = PAGE_WIDTH+4;
+ va &= ~((1<<ps)-1);
+ break;
+ case 3: /*cnt 64-255*/
+ /*cnt=((cnt-1)/64)+1;*/
+ ps = PAGE_WIDTH+6;
+ va &= ~((1<<ps)-1);
+ break;
+ case 4: /*cnt 256-1023*/
+ /*cnt=((cnt-1)/256)+1;*/
+ ps = PAGE_WIDTH+8;
+ va &= ~((1<<ps)-1);
+ break;
+ case 5: /*cnt 1024-4095*/
+ /*cnt=((cnt-1)/1024)+1;*/
+ ps = PAGE_WIDTH+10;
+ va &= ~((1<<ps)-1);
+ break;
+ case 6: /*cnt 4096-16383*/
+ /*cnt=((cnt-1)/4096)+1;*/
+ ps = PAGE_WIDTH+12;
+ va &= ~((1<<ps)-1);
+ break;
+ case 7: /*cnt 16384-65535*/
+ case 8: /*cnt 65536-(256K-1)*/
+ /*cnt=((cnt-1)/16384)+1;*/
+ ps = PAGE_WIDTH+14;
+ va &= ~((1<<ps)-1);
+ break;
+ default:
+ /*cnt=((cnt-1)/(16384*16))+1;*/
+ ps=PAGE_WIDTH+18;
+ va&=~((1<<ps)-1);
+ break;
+ }
+ /*cnt+=(page!=va);*/
+ for(; va<(page+cnt*(PAGE_SIZE)); va += (1<<ps)) {
+ __asm__ volatile (
+ "ptc.l %0,%1;;"
+ :
+ : "r" (va), "r" (ps<<2)
+ );
+ }
+ srlz_d();
+ srlz_i();
+
+ if (restore_rr) {
+ rr_write(VA2VRN(va), rr.word);
+ srlz_d();
+ srlz_i();
+ }
+}
+
+
+/** Insert data into data translation cache.
+ *
+ * @param va Virtual page address.
+ * @param asid Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion format.
+ */
+void dtc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry)
+{
+ tc_mapping_insert(va, asid, entry, true);
+}
+
+/** Insert data into instruction translation cache.
+ *
+ * @param va Virtual page address.
+ * @param asid Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion format.
+ */
+void itc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry)
+{
+ tc_mapping_insert(va, asid, entry, false);
+}
+
+/** Insert data into instruction or data translation cache.
+ *
+ * @param va Virtual page address.
+ * @param asid Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param dtc If true, insert into data translation cache, use instruction translation cache otherwise.
+ */
+void tc_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtc)
+{
+ region_register rr;
+ bool restore_rr = false;
+
+ rr.word = rr_read(VA2VRN(va));
+ if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
+ /*
+ * The selected region register does not contain required RID.
+ * Save the old content of the register and replace the RID.
+ */
+ region_register rr0;
+
+ rr0 = rr;
+ rr0.map.rid = ASID2RID(asid, VA2VRN(va));
+ rr_write(VA2VRN(va), rr0.word);
+ srlz_d();
+ srlz_i();
+ }
+
+ __asm__ volatile (
+ "mov r8=psr;;\n"
+ "rsm %0;;\n" /* PSR_IC_MASK */
+ "srlz.d;;\n"
+ "srlz.i;;\n"
+ "mov cr.ifa=%1\n" /* va */
+ "mov cr.itir=%2;;\n" /* entry.word[1] */
+ "cmp.eq p6,p7 = %4,r0;;\n" /* decide between itc and dtc */
+ "(p6) itc.i %3;;\n"
+ "(p7) itc.d %3;;\n"
+ "mov psr.l=r8;;\n"
+ "srlz.d;;\n"
+ :
+ : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (dtc)
+ : "p6", "p7", "r8"
+ );
+
+ if (restore_rr) {
+ rr_write(VA2VRN(va), rr.word);
+ srlz_d();
+ srlz_i();
+ }
+}
+
+/** Insert data into instruction translation register.
+ *
+ * @param va Virtual page address.
+ * @param asid Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param tr Translation register.
+ */
+void itr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr)
+{
+ tr_mapping_insert(va, asid, entry, false, tr);
+}
+
+/** Insert data into data translation register.
+ *
+ * @param va Virtual page address.
+ * @param asid Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param tr Translation register.
+ */
+void dtr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, index_t tr)
+{
+ tr_mapping_insert(va, asid, entry, true, tr);
+}
+
+/** Insert data into instruction or data translation register.
+ *
+ * @param va Virtual page address.
+ * @param asid Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param dtc If true, insert into data translation register, use instruction translation register otherwise.
+ * @param tr Translation register.
+ */
+void tr_mapping_insert(__address va, asid_t asid, tlb_entry_t entry, bool dtr, index_t tr)
+{
+ region_register rr;
+ bool restore_rr = false;
+
+ rr.word = rr_read(VA2VRN(va));
+ if ((restore_rr = (rr.map.rid != ASID2RID(asid, VA2VRN(va))))) {
+ /*
+ * The selected region register does not contain required RID.
+ * Save the old content of the register and replace the RID.
+ */
+ region_register rr0;
+
+ rr0 = rr;
+ rr0.map.rid = ASID2RID(asid, VA2VRN(va));
+ rr_write(VA2VRN(va), rr0.word);
+ srlz_d();
+ srlz_i();
+ }
+
+ __asm__ volatile (
+ "mov r8=psr;;\n"
+ "rsm %0;;\n" /* PSR_IC_MASK */
+ "srlz.d;;\n"
+ "srlz.i;;\n"
+ "mov cr.ifa=%1\n" /* va */
+ "mov cr.itir=%2;;\n" /* entry.word[1] */
+ "cmp.eq p6,p7=%5,r0;;\n" /* decide between itr and dtr */
+ "(p6) itr.i itr[%4]=%3;;\n"
+ "(p7) itr.d dtr[%4]=%3;;\n"
+ "mov psr.l=r8;;\n"
+ "srlz.d;;\n"
+ :
+ : "i" (PSR_IC_MASK), "r" (va), "r" (entry.word[1]), "r" (entry.word[0]), "r" (tr), "r" (dtr)
+ : "p6", "p7", "r8"
+ );
+
+ if (restore_rr) {
+ rr_write(VA2VRN(va), rr.word);
+ srlz_d();
+ srlz_i();
+ }
+}
+
+/** Insert data into DTLB.
+ *
+ * @param va Virtual page address.
+ * @param asid Address space identifier.
+ * @param entry The rest of TLB entry as required by TLB insertion format.
+ * @param dtr If true, insert into data translation register, use data translation cache otherwise.
+ * @param tr Translation register if dtr is true, ignored otherwise.
+ */
+void dtlb_kernel_mapping_insert(__address page, __address frame, bool dtr, index_t tr)
+{
+ tlb_entry_t entry;
+
+ entry.word[0] = 0;
+ entry.word[1] = 0;
+
+ entry.p = true; /* present */
+ entry.ma = MA_WRITEBACK;
+ entry.a = true; /* already accessed */
+ entry.d = true; /* already dirty */
+ entry.pl = PL_KERNEL;
+ entry.ar = AR_READ | AR_WRITE;
+ entry.ppn = frame >> PPN_SHIFT;
+ entry.ps = PAGE_WIDTH;
+
+ if (dtr)
+ dtr_mapping_insert(page, ASID_KERNEL, entry, tr);
+ else
+ dtc_mapping_insert(page, ASID_KERNEL, entry);
+}
+
+/** Copy content of PTE into data translation cache.
+ *
+ * @param t PTE.
+ */
+void dtc_pte_copy(pte_t *t)
+{
+ tlb_entry_t entry;
+
+ entry.word[0] = 0;
+ entry.word[1] = 0;
+
+ entry.p = t->p;
+ entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE;
+ entry.a = t->a;
+ entry.d = t->d;
+ entry.pl = t->k ? PL_KERNEL : PL_USER;
+ entry.ar = t->w ? AR_WRITE : AR_READ;
+ entry.ppn = t->frame >> PPN_SHIFT;
+ entry.ps = PAGE_WIDTH;
+
+ dtc_mapping_insert(t->page, t->as->asid, entry);
+#ifdef CONFIG_VHPT
+ vhpt_mapping_insert(t->page, t->as->asid, entry);
+#endif
+}
+
+/** Copy content of PTE into instruction translation cache.
+ *
+ * @param t PTE.
+ */
+void itc_pte_copy(pte_t *t)
+{
+ tlb_entry_t entry;
+
+ entry.word[0] = 0;
+ entry.word[1] = 0;
+
+ ASSERT(t->x);
+
+ entry.p = t->p;
+ entry.ma = t->c ? MA_WRITEBACK : MA_UNCACHEABLE;
+ entry.a = t->a;
+ entry.pl = t->k ? PL_KERNEL : PL_USER;
+ entry.ar = t->x ? (AR_EXECUTE | AR_READ) : AR_READ;
+ entry.ppn = t->frame >> PPN_SHIFT;
+ entry.ps = PAGE_WIDTH;
+
+ itc_mapping_insert(t->page, t->as->asid, entry);
+#ifdef CONFIG_VHPT
+ vhpt_mapping_insert(t->page, t->as->asid, entry);
+#endif
+}
+
+/** Instruction TLB fault handler for faults with VHPT turned off.
+ *
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ */
+void alternate_instruction_tlb_fault(__u64 vector, istate_t *istate)
+{
+ region_register rr;
+ rid_t rid;
+ __address va;
+ pte_t *t;
+
+ va = istate->cr_ifa; /* faulting address */
+ rr.word = rr_read(VA2VRN(va));
+ rid = rr.map.rid;
+
+ page_table_lock(AS, true);
+ t = page_mapping_find(AS, va);
+ if (t) {
+ /*
+ * The mapping was found in software page hash table.
+ * Insert it into data translation cache.
+ */
+ itc_pte_copy(t);
+ page_table_unlock(AS, true);
+ } else {
+ /*
+ * Forward the page fault to address space page fault handler.
+ */
+ page_table_unlock(AS, true);
+ if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
+ fault_if_from_uspace(istate,"Page fault at %P",va);
+ panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
+ }
+ }
+}
+
+/** Data TLB fault handler for faults with VHPT turned off.
+ *
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ */
+void alternate_data_tlb_fault(__u64 vector, istate_t *istate)
+{
+ region_register rr;
+ rid_t rid;
+ __address va;
+ pte_t *t;
+
+ va = istate->cr_ifa; /* faulting address */
+ rr.word = rr_read(VA2VRN(va));
+ rid = rr.map.rid;
+ if (RID2ASID(rid) == ASID_KERNEL) {
+ if (VA2VRN(va) == VRN_KERNEL) {
+ /*
+ * Provide KA2PA(identity) mapping for faulting piece of
+ * kernel address space.
+ */
+ dtlb_kernel_mapping_insert(va, KA2PA(va), false, 0);
+ return;
+ }
+ }
+
+ page_table_lock(AS, true);
+ t = page_mapping_find(AS, va);
+ if (t) {
+ /*
+ * The mapping was found in software page hash table.
+ * Insert it into data translation cache.
+ */
+ dtc_pte_copy(t);
+ page_table_unlock(AS, true);
+ } else {
+ /*
+ * Forward the page fault to address space page fault handler.
+ */
+ page_table_unlock(AS, true);
+ if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
+ fault_if_from_uspace(istate,"Page fault at %P",va);
+ panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
+ }
+ }
+}
+
+/** Data nested TLB fault handler.
+ *
+ * This fault should not occur.
+ *
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ */
+void data_nested_tlb_fault(__u64 vector, istate_t *istate)
+{
+ panic("%s\n", __FUNCTION__);
+}
+
+/** Data Dirty bit fault handler.
+ *
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ */
+void data_dirty_bit_fault(__u64 vector, istate_t *istate)
+{
+ region_register rr;
+ rid_t rid;
+ __address va;
+ pte_t *t;
+
+ va = istate->cr_ifa; /* faulting address */
+ rr.word = rr_read(VA2VRN(va));
+ rid = rr.map.rid;
+
+ page_table_lock(AS, true);
+ t = page_mapping_find(AS, va);
+ ASSERT(t && t->p);
+ if (t && t->p && t->w) {
+ /*
+ * Update the Dirty bit in page tables and reinsert
+ * the mapping into DTC.
+ */
+ t->d = true;
+ dtc_pte_copy(t);
+ } else {
+ if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
+ fault_if_from_uspace(istate,"Page fault at %P",va);
+ panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
+ t->d = true;
+ dtc_pte_copy(t);
+ }
+ }
+ page_table_unlock(AS, true);
+}
+
+/** Instruction access bit fault handler.
+ *
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ */
+void instruction_access_bit_fault(__u64 vector, istate_t *istate)
+{
+ region_register rr;
+ rid_t rid;
+ __address va;
+ pte_t *t;
+
+ va = istate->cr_ifa; /* faulting address */
+ rr.word = rr_read(VA2VRN(va));
+ rid = rr.map.rid;
+
+ page_table_lock(AS, true);
+ t = page_mapping_find(AS, va);
+ ASSERT(t && t->p);
+ if (t && t->p && t->x) {
+ /*
+ * Update the Accessed bit in page tables and reinsert
+ * the mapping into ITC.
+ */
+ t->a = true;
+ itc_pte_copy(t);
+ } else {
+ if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
+ fault_if_from_uspace(istate,"Page fault at %P",va);
+ panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
+ t->a = true;
+ itc_pte_copy(t);
+ }
+ }
+ page_table_unlock(AS, true);
+}
+
+/** Data access bit fault handler.
+ *
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ */
+void data_access_bit_fault(__u64 vector, istate_t *istate)
+{
+ region_register rr;
+ rid_t rid;
+ __address va;
+ pte_t *t;
+
+ va = istate->cr_ifa; /* faulting address */
+ rr.word = rr_read(VA2VRN(va));
+ rid = rr.map.rid;
+
+ page_table_lock(AS, true);
+ t = page_mapping_find(AS, va);
+ ASSERT(t && t->p);
+ if (t && t->p) {
+ /*
+ * Update the Accessed bit in page tables and reinsert
+ * the mapping into DTC.
+ */
+ t->a = true;
+ dtc_pte_copy(t);
+ } else {
+ if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
+ fault_if_from_uspace(istate,"Page fault at %P",va);
+ panic("%s: va=%p, rid=%d, iip=%p\n", __FUNCTION__, va, rid, istate->cr_iip);
+ t->a = true;
+ itc_pte_copy(t);
+ }
+ }
+ page_table_unlock(AS, true);
+}
+
+/** Page not present fault handler.
+ *
+ * @param vector Interruption vector.
+ * @param istate Structure with saved interruption state.
+ */
+void page_not_present(__u64 vector, istate_t *istate)
+{
+ region_register rr;
+ rid_t rid;
+ __address va;
+ pte_t *t;
+
+ va = istate->cr_ifa; /* faulting address */
+ rr.word = rr_read(VA2VRN(va));
+ rid = rr.map.rid;
+
+ page_table_lock(AS, true);
+ t = page_mapping_find(AS, va);
+ ASSERT(t);
+
+ if (t->p) {
+ /*
+ * If the Present bit is set in page hash table, just copy it
+ * and update ITC/DTC.
+ */
+ if (t->x)
+ itc_pte_copy(t);
+ else
+ dtc_pte_copy(t);
+ page_table_unlock(AS, true);
+ } else {
+ page_table_unlock(AS, true);
+ if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
+ fault_if_from_uspace(istate,"Page fault at %P",va);
+ panic("%s: va=%p, rid=%d\n", __FUNCTION__, va, rid);
+ }
+ }
+}

/tags/0.2.0/kernel/arch/ia64/src/mm/vhpt.c
0,0 → 1,88
/*
* Copyright (C) 2006 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/vhpt.h>
#include <mm/frame.h>
#include <print.h>
static vhpt_entry_t* vhpt_base;
__address vhpt_set_up(void)
{
vhpt_base=(vhpt_entry_t*) PA2KA(PFN2ADDR(frame_alloc(VHPT_WIDTH-FRAME_WIDTH,FRAME_KA)));
if(!vhpt_base) panic("Kernel configured with VHPT but no memory for table.");
vhpt_invalidate_all();
return (__address) vhpt_base;
}
void vhpt_mapping_insert(__address va, asid_t asid, tlb_entry_t entry)
{
region_register rr_save, rr;
index_t vrn;
rid_t rid;
__u64 tag;
vhpt_entry_t *ventry;
vrn = va >> VRN_SHIFT;
rid = ASID2RID(asid, vrn);
rr_save.word = rr_read(vrn);
rr.word = rr_save.word;
rr.map.rid = rid;
rr_write(vrn, rr.word);
srlz_i();
ventry = (vhpt_entry_t *) thash(va);
tag = ttag(va);
rr_write(vrn, rr_save.word);
srlz_i();
srlz_d();
ventry->word[0]=entry.word[0];
ventry->word[1]=entry.word[1];
ventry->present.tag.tag_word = tag;
}
void vhpt_invalidate_all()
{
memsetb((__address)vhpt_base,1<<VHPT_WIDTH,0);
}
void vhpt_invalidate_asid(asid_t asid)
{
vhpt_invalidate_all();
}

/tags/0.2.0/kernel/arch/ia64/src/mm/page.c
0,0 → 1,258
/*
* Copyright (C) 2006 Jakub Jermar
* Copyright (C) 2006 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/page.h>
#include <genarch/mm/page_ht.h>
#include <mm/asid.h>
#include <arch/mm/asid.h>
#include <arch/mm/vhpt.h>
#include <arch/types.h>
#include <typedefs.h>
#include <print.h>
#include <mm/page.h>
#include <mm/frame.h>
#include <config.h>
#include <panic.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <memstr.h>
static void set_environment(void);
/** Initialize ia64 virtual address translation subsystem. */
void page_arch_init(void)
{
page_mapping_operations = &ht_mapping_operations;
pk_disable();
set_environment();
}
/** Initialize VHPT and region registers. */
void set_environment(void)
{
region_register rr;
pta_register pta;
int i;
#ifdef CONFIG_VHPT
__address vhpt_base;
#endif
/*
* First set up kernel region register.
* This is redundant (see start.S) but we keep it here just for sure.
*/
rr.word = rr_read(VRN_KERNEL);
rr.map.ve = 0; /* disable VHPT walker */
rr.map.ps = PAGE_WIDTH;
rr.map.rid = ASID2RID(ASID_KERNEL, VRN_KERNEL);
rr_write(VRN_KERNEL, rr.word);
srlz_i();
srlz_d();
/*
* And setup the rest of region register.
*/
for(i = 0; i < REGION_REGISTERS; i++) {
/* skip kernel rr */
if (i == VRN_KERNEL)
continue;
rr.word = rr_read(i);
rr.map.ve = 0; /* disable VHPT walker */
rr.map.rid = RID_KERNEL;
rr.map.ps = PAGE_WIDTH;
rr_write(i, rr.word);
srlz_i();
srlz_d();
}
#ifdef CONFIG_VHPT
vhpt_base = vhpt_set_up();
#endif
/*
* Set up PTA register.
*/
pta.word = pta_read();
#ifndef CONFIG_VHPT
pta.map.ve = 0; /* disable VHPT walker */
pta.map.base = 0 >> PTA_BASE_SHIFT;
#else
pta.map.ve = 1; /* enable VHPT walker */
pta.map.base = vhpt_base >> PTA_BASE_SHIFT;
#endif
pta.map.vf = 1; /* large entry format */
pta.map.size = VHPT_WIDTH;
pta_write(pta.word);
srlz_i();
srlz_d();
}
/** Calculate address of collision chain from VPN and ASID.
*
* Interrupts must be disabled.
*
* @param page Address of virtual page including VRN bits.
* @param asid Address space identifier.
*
* @return VHPT entry address.
*/
vhpt_entry_t *vhpt_hash(__address page, asid_t asid)
{
region_register rr_save, rr;
index_t vrn;
rid_t rid;
vhpt_entry_t *v;
vrn = page >> VRN_SHIFT;
rid = ASID2RID(asid, vrn);
rr_save.word = rr_read(vrn);
if (rr_save.map.rid == rid) {
/*
* The RID is already in place, compute thash and return.
*/
v = (vhpt_entry_t *) thash(page);
return v;
}
/*
* The RID must be written to some region register.
* To speed things up, register indexed by vrn is used.
*/
rr.word = rr_save.word;
rr.map.rid = rid;
rr_write(vrn, rr.word);
srlz_i();
v = (vhpt_entry_t *) thash(page);
rr_write(vrn, rr_save.word);
srlz_i();
srlz_d();
return v;
}
/** Compare ASID and VPN against PTE.
*
* Interrupts must be disabled.
*
* @param page Address of virtual page including VRN bits.
* @param asid Address space identifier.
*
* @return True if page and asid match the page and asid of t, false otherwise.
*/
bool vhpt_compare(__address page, asid_t asid, vhpt_entry_t *v)
{
region_register rr_save, rr;
index_t vrn;
rid_t rid;
bool match;
ASSERT(v);
vrn = page >> VRN_SHIFT;
rid = ASID2RID(asid, vrn);
rr_save.word = rr_read(vrn);
if (rr_save.map.rid == rid) {
/*
* The RID is already in place, compare ttag with t and return.
*/
return ttag(page) == v->present.tag.tag_word;
}
/*
* The RID must be written to some region register.
* To speed things up, register indexed by vrn is used.
*/
rr.word = rr_save.word;
rr.map.rid = rid;
rr_write(vrn, rr.word);
srlz_i();
match = (ttag(page) == v->present.tag.tag_word);
rr_write(vrn, rr_save.word);
srlz_i();
srlz_d();
return match;
}
/** Set up one VHPT entry.
*
* @param t VHPT entry to be set up.
* @param page Virtual address of the page mapped by the entry.
* @param asid Address space identifier of the address space to which page belongs.
* @param frame Physical address of the frame to wich page is mapped.
* @param flags Different flags for the mapping.
*/
void vhpt_set_record(vhpt_entry_t *v, __address page, asid_t asid, __address frame, int flags)
{
region_register rr_save, rr;
index_t vrn;
rid_t rid;
__u64 tag;
ASSERT(v);
vrn = page >> VRN_SHIFT;
rid = ASID2RID(asid, vrn);
/*
* Compute ttag.
*/
rr_save.word = rr_read(vrn);
rr.word = rr_save.word;
rr.map.rid = rid;
rr_write(vrn, rr.word);
srlz_i();
tag = ttag(page);
rr_write(vrn, rr_save.word);
srlz_i();
srlz_d();
/*
* Clear the entry.
*/
v->word[0] = 0;
v->word[1] = 0;
v->word[2] = 0;
v->word[3] = 0;
v->present.p = true;
v->present.ma = (flags & PAGE_CACHEABLE) ? MA_WRITEBACK : MA_UNCACHEABLE;
v->present.a = false; /* not accessed */
v->present.d = false; /* not dirty */
v->present.pl = (flags & PAGE_USER) ? PL_USER : PL_KERNEL;
v->present.ar = (flags & PAGE_WRITE) ? AR_WRITE : AR_READ;
v->present.ar |= (flags & PAGE_EXEC) ? AR_EXECUTE : 0;
v->present.ppn = frame >> PPN_SHIFT;
v->present.ed = false; /* exception not deffered */
v->present.ps = PAGE_WIDTH;
v->present.key = 0;
v->present.tag.tag_word = tag;
}

/tags/0.2.0/kernel/arch/ia64/src/mm/as.c
0,0 → 1,80
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/as.h>
#include <arch/mm/asid.h>
#include <arch/mm/page.h>
#include <genarch/mm/as_ht.h>
#include <genarch/mm/asid_fifo.h>
#include <mm/asid.h>
#include <arch.h>
#include <arch/barrier.h>
#include <synch/spinlock.h>
/** Architecture dependent address space init. */
void as_arch_init(void)
{
as_operations = &as_ht_operations;
asid_fifo_init();
}
/** Prepare registers for switching to another address space.
*
* @param as Address space.
*/
void as_install_arch(as_t *as)
{
ipl_t ipl;
region_register rr;
int i;
ipl = interrupts_disable();
spinlock_lock(&as->lock);
ASSERT(as->asid != ASID_INVALID);
/*
* Load respective ASID (7 consecutive RIDs) to
* region registers.
*/
for (i = 0; i < REGION_REGISTERS; i++) {
if (i == VRN_KERNEL)
continue;
rr.word = rr_read(i);
rr.map.ve = false; /* disable VHPT walker */
rr.map.rid = ASID2RID(as->asid, i);
rr.map.ps = PAGE_WIDTH;
rr_write(i, rr.word);
}
srlz_d();
srlz_i();
spinlock_unlock(&as->lock);
interrupts_restore(ipl);
}

/tags/0.2.0/kernel/arch/ia64/src/mm/frame.c
0,0 → 1,49
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/frame.h>
#include <mm/frame.h>
#include <config.h>
#include <panic.h>
/*
* This is Ski-specific and certainly not sufficient
* for real ia64 systems that provide memory map.
*/
#define ROM_BASE 0xa0000
#define ROM_SIZE (384*1024)
void frame_arch_init(void)
{
zone_create(0, config.memory_size >> FRAME_WIDTH, 1, 0);
/*
* Blacklist ROM regions.
*/
frame_mark_unavailable(ADDR2PFN(ROM_BASE), ROM_SIZE >> FRAME_WIDTH);
}

/tags/0.2.0/kernel/arch/ia64/src/interrupt.c
0,0 → 1,274
/*
* Copyright (C) 2005 Jakub Jermar
* Copyright (C) 2005 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <arch/interrupt.h>
#include <panic.h>
#include <print.h>
#include <console/console.h>
#include <arch/types.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/register.h>
#include <arch/drivers/it.h>
#include <arch.h>
#include <symtab.h>
#include <debug.h>
#include <syscall/syscall.h>
#include <print.h>
#include <proc/scheduler.h>
#include <ipc/sysipc.h>
#include <ipc/irq.h>
#include <ipc/ipc.h>
#include <interrupt.h>
#define VECTORS_64_BUNDLE 20
#define VECTORS_16_BUNDLE 48
#define VECTORS_16_BUNDLE_START 0x5000
#define VECTOR_MAX 0x7f00
#define BUNDLE_SIZE 16
char *vector_names_64_bundle[VECTORS_64_BUNDLE] = {
"VHPT Translation vector",
"Instruction TLB vector",
"Data TLB vector",
"Alternate Instruction TLB vector",
"Alternate Data TLB vector",
"Data Nested TLB vector",
"Instruction Key Miss vector",
"Data Key Miss vector",
"Dirty-Bit vector",
"Instruction Access-Bit vector",
"Data Access-Bit vector"
"Break Instruction vector",
"External Interrupt vector"
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved"
};
char *vector_names_16_bundle[VECTORS_16_BUNDLE] = {
"Page Not Present vector",
"Key Permission vector",
"Instruction Access rights vector",
"Data Access Rights vector",
"General Exception vector",
"Disabled FP-Register vector",
"NaT Consumption vector",
"Speculation vector",
"Reserved",
"Debug vector",
"Unaligned Reference vector",
"Unsupported Data Reference vector",
"Floating-point Fault vector",
"Floating-point Trap vector",
"Lower-Privilege Transfer Trap vector",
"Taken Branch Trap vector",
"Single STep Trap vector",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"IA-32 Exception vector",
"IA-32 Intercept vector",
"IA-32 Interrupt vector",
"Reserved",
"Reserved",
"Reserved"
};
static char *vector_to_string(__u16 vector);
static void dump_interrupted_context(istate_t *istate);
char *vector_to_string(__u16 vector)
{
ASSERT(vector <= VECTOR_MAX);
if (vector >= VECTORS_16_BUNDLE_START)
return vector_names_16_bundle[(vector-VECTORS_16_BUNDLE_START)/(16*BUNDLE_SIZE)];
else
return vector_names_64_bundle[vector/(64*BUNDLE_SIZE)];
}
void dump_interrupted_context(istate_t *istate)
{
char *ifa, *iipa, *iip;
ifa = get_symtab_entry(istate->cr_ifa);
iipa = get_symtab_entry(istate->cr_iipa);
iip = get_symtab_entry(istate->cr_iip);
putchar('\n');
printf("Interrupted context dump:\n");
printf("ar.bsp=%p\tar.bspstore=%p\n", istate->ar_bsp, istate->ar_bspstore);
printf("ar.rnat=%#018llx\tar.rsc=%#018llx\n", istate->ar_rnat, istate->ar_rsc);
printf("ar.ifs=%#018llx\tar.pfs=%#018llx\n", istate->ar_ifs, istate->ar_pfs);
printf("cr.isr=%#018llx\tcr.ipsr=%#018llx\t\n", istate->cr_isr.value, istate->cr_ipsr);
printf("cr.iip=%#018llx, #%d\t(%s)\n", istate->cr_iip, istate->cr_isr.ei, iip);
printf("cr.iipa=%#018llx\t(%s)\n", istate->cr_iipa, iipa);
printf("cr.ifa=%#018llx\t(%s)\n", istate->cr_ifa, ifa);
}
void general_exception(__u64 vector, istate_t *istate)
{
char *desc = "";
switch (istate->cr_isr.ge_code) {
case GE_ILLEGALOP:
desc = "Illegal Operation fault";
break;
case GE_PRIVOP:
desc = "Privileged Operation fault";
break;
case GE_PRIVREG:
desc = "Privileged Register fault";
break;
case GE_RESREGFLD:
desc = "Reserved Register/Field fault";
break;
case GE_DISBLDISTRAN:
desc = "Disabled Instruction Set Transition fault";
break;
case GE_ILLEGALDEP:
desc = "Illegal Dependency fault";
break;
default:
desc = "unknown";
break;
}
fault_if_from_uspace(istate, "General Exception (%s)", desc);
dump_interrupted_context(istate);
panic("General Exception (%s)\n", desc);
}
void fpu_enable(void);
void disabled_fp_register(__u64 vector, istate_t *istate)
{
#ifdef CONFIG_FPU_LAZY
scheduler_fpu_lazy_request();
#else
fault_if_from_uspace(istate, "Interruption: %#hx (%s)", (__u16) vector, vector_to_string(vector));
dump_interrupted_context(istate);
panic("Interruption: %#hx (%s)\n", (__u16) vector, vector_to_string(vector));
#endif
}
void nop_handler(__u64 vector, istate_t *istate)
{
}
/** Handle syscall. */
int break_instruction(__u64 vector, istate_t *istate)
{
/*
* Move to next instruction after BREAK.
*/
if (istate->cr_ipsr.ri == 2) {
istate->cr_ipsr.ri = 0;
istate->cr_iip += 16;
} else {
istate->cr_ipsr.ri++;
}
if (istate->in4 < SYSCALL_END)
return syscall_table[istate->in4](istate->in0, istate->in1, istate->in2, istate->in3);
else
panic("Undefined syscall %d", istate->in4);
return -1;
}
void universal_handler(__u64 vector, istate_t *istate)
{
fault_if_from_uspace(istate,"Interruption: %#hx (%s)\n",(__u16) vector, vector_to_string(vector));
dump_interrupted_context(istate);
panic("Interruption: %#hx (%s)\n", (__u16) vector, vector_to_string(vector));
}
void external_interrupt(__u64 vector, istate_t *istate)
{
cr_ivr_t ivr;
ivr.value = ivr_read();
srlz_d();
switch(ivr.vector) {
case INTERRUPT_TIMER:
it_interrupt();
break;
case INTERRUPT_SPURIOUS:
printf("cpu%d: spurious interrupt\n", CPU->id);
break;
default:
panic("\nUnhandled External Interrupt Vector %d\n", ivr.vector);
break;
}
}
void virtual_interrupt(__u64 irq,void *param)
{
switch(irq) {
case IRQ_KBD:
if(kbd_uspace) ipc_irq_send_notif(irq);
break;
default:
panic("\nUnhandled Virtual Interrupt request %d\n", irq);
break;
}
}
/* Reregister irq to be IPC-ready */
void irq_ipc_bind_arch(__native irq)
{
if(irq==IRQ_KBD) {
kbd_uspace=1;
return;
}
return;
panic("not implemented\n");
/* TODO */
}

/tags/0.2.0/kernel/arch/ia64/src/asm.S
0,0 → 1,184
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/register.h>
.text
/** Copy memory from/to userspace.
*
* This memcpy() has been taken from the assembler output of
* the generic _memcpy() and modified to have the failover part.
*
* @param in0 Destination address.
* @param in1 Source address.
* @param in2 Number of byte to copy.
*/
.global memcpy
.global memcpy_from_uspace
.global memcpy_to_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace_failover_address
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
alloc loc0 = ar.pfs, 3, 1, 0, 0
adds r14 = 7, in1
mov r2 = ar.lc
mov r8 = in1 ;;
and r14 = -8, r14 ;;
cmp.ne p6, p7 = r14, in1
(p7) br.cond.dpnt 3f ;;
0:
cmp.ne p6, p7 = 0, in2
(p7) br.cond.dpnt 2f ;;
(p6) adds r14 = -1, in2
(p6) mov r16 = r0
(p6) mov r17 = r0 ;;
(p6) mov ar.lc = r14
1:
add r14 = r16, r8
add r15 = r16, in0
adds r17 = 1, r17 ;;
ld1 r14 = [r14]
mov r16 = r17 ;;
st1 [r15] = r14
br.cloop.sptk.few 1b ;;
2:
mov ar.lc = r2
mov ar.pfs = loc0
br.ret.sptk.many rp
3:
adds r14 = 7, in0 ;;
and r14 = -8, r14 ;;
cmp.eq p6, p7 = r14, in0
(p7) br.cond.dptk 0b
shr.u r18 = in2, 3 ;;
cmp.ne p6, p7 = 0, r18
(p7) br.cond.dpnt 5f ;;
(p6) adds r14 = -1, r18
(p6) mov r16 = r0
(p6) mov r17 = r0 ;;
(p6) mov ar.lc = r14
4:
shladd r14 = r16, 3, r0
adds r16 = 1, r17 ;;
add r15 = r8, r14
add r14 = in0, r14
mov r17 = r16 ;;
ld8 r15 = [r15] ;;
st8 [r14] = r15
br.cloop.sptk.few 4b
5:
and r15 = 7, in2
shladd r14 = r18, 3, r0
mov r16 = r0
mov r18 = r0 ;;
cmp.eq p6, p7 = 0, r15
add in0 = r14, in0
adds r15 = -1, r15
add r17 = r14, r8
(p6) br.cond.dpnt 2b ;;
mov ar.lc = r15
6:
add r14 = r16, r17
add r15 = r16, in0
adds r16 = 1, r18 ;;
ld1 r14 = [r14]
mov r18 = r16 ;;
st1 [r15] = r14
br.cloop.sptk.few 6b ;;
mov ar.lc = r2
mov ar.pfs = loc0
br.ret.sptk.many rp
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
mov r8 = r0 /* return 0 on failure */
mov ar.pfs = loc0
br.ret.sptk.many rp
.global memsetb
memsetb:
br _memsetb
.global cpu_halt
cpu_halt:
br cpu_halt
.global panic_printf
panic_printf:
{
br.call.sptk.many b0=printf
}
br halt
/** Switch to userspace - low level code.
*
* @param in0 Userspace entry point address.
* @param in1 Userspace stack pointer address.
* @param in2 Userspace register stack pointer address.
* @param in3 Userspace address of thread uspace_arg_t structure.
* @param in4 Value to be stored in IPSR.
* @param in5 Value to be stored in RSC.
*/
.global switch_to_userspace
switch_to_userspace:
alloc loc0 = ar.pfs, 6, 3, 0, 0
rsm (PSR_IC_MASK | PSR_I_MASK) /* disable interruption collection and interrupts */
srlz.d ;;
srlz.i ;;
mov cr.ipsr = in4
mov cr.iip = in0
mov r12 = in1
xor r1 = r1, r1
mov loc1 = cr.ifs
movl loc2 = PFM_MASK ;;
and loc1 = loc2, loc1 ;;
mov cr.ifs = loc1 ;; /* prevent decrementing BSP by rfi */
invala
mov loc1 = ar.rsc ;;
and loc1 = ~3, loc1 ;;
mov ar.rsc = loc1 ;; /* put RSE into enforced lazy mode */
flushrs ;;
mov ar.bspstore = in2 ;;
mov ar.rsc = in5 ;;
mov r8 = in3
rfi ;;

/tags/0.2.0/kernel/arch/ia64/src/ia64.c
0,0 → 1,147
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <arch/ski/ski.h>
#include <arch/drivers/it.h>
#include <arch/interrupt.h>
#include <arch/barrier.h>
#include <arch/asm.h>
#include <arch/register.h>
#include <arch/types.h>
#include <arch/context.h>
#include <arch/stack.h>
#include <arch/mm/page.h>
#include <mm/as.h>
#include <config.h>
#include <userspace.h>
#include <console/console.h>
#include <proc/uarg.h>
#include <syscall/syscall.h>
static int kbd_release=0;
void arch_pre_main(void)
{
/* Setup usermode init tasks. */
init.cnt = 8;
init.tasks[0].addr = INIT0_ADDRESS;
init.tasks[0].size = INIT0_SIZE;
init.tasks[1].addr = INIT0_ADDRESS + 0x400000;
init.tasks[1].size = INIT0_SIZE;
init.tasks[2].addr = INIT0_ADDRESS + 0x800000;
init.tasks[2].size = INIT0_SIZE;
init.tasks[3].addr = INIT0_ADDRESS + 0xc00000;
init.tasks[3].size = INIT0_SIZE;
init.tasks[4].addr = INIT0_ADDRESS + 0x1000000;
init.tasks[4].size = INIT0_SIZE;
init.tasks[5].addr = INIT0_ADDRESS + 0x1400000;
init.tasks[5].size = INIT0_SIZE;
init.tasks[6].addr = INIT0_ADDRESS + 0x1800000;
init.tasks[6].size = INIT0_SIZE;
init.tasks[7].addr = INIT0_ADDRESS + 0x1c00000;
init.tasks[7].size = INIT0_SIZE;
}
void arch_pre_mm_init(void)
{
/* Set Interruption Vector Address (i.e. location of interruption vector table). */
iva_write((__address) &ivt);
srlz_d();
ski_init_console();
it_init();
}
void arch_post_mm_init(void)
{
ski_set_console_sysinfo();
}
void arch_pre_smp_init(void)
{
}
void arch_post_smp_init(void)
{
}
/** Enter userspace and never return. */
void userspace(uspace_arg_t *kernel_uarg)
{
psr_t psr;
rsc_t rsc;
psr.value = psr_read();
psr.cpl = PL_USER;
psr.i = true; /* start with interrupts enabled */
psr.ic = true;
psr.ri = 0; /* start with instruction #0 */
psr.bn = 1; /* start in bank 0 */
__asm__ volatile ("mov %0 = ar.rsc\n" : "=r" (rsc.value));
rsc.loadrs = 0;
rsc.be = false;
rsc.pl = PL_USER;
rsc.mode = 3; /* eager mode */
switch_to_userspace((__address) kernel_uarg->uspace_entry,
((__address) kernel_uarg->uspace_stack)+PAGE_SIZE-ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT),
((__address) kernel_uarg->uspace_stack)+PAGE_SIZE,
(__address) kernel_uarg->uspace_uarg,
psr.value, rsc.value);
while (1) {
;
}
}
/** Set thread-local-storage pointer.
*
* We use r13 (a.k.a. tp) for this purpose.
*/
__native sys_tls_set(__native addr)
{
return 0;
}
/** Acquire console back for kernel
*
*/
void arch_grab_console(void)
{
kbd_release=kbd_uspace;
kbd_uspace=0;
}
/** Return console to userspace
*
*/
void arch_release_console(void)
{
kbd_uspace=kbd_release;
}

/tags/0.2.0/kernel/arch/ia64/src/ski/ski.c
0,0 → 1,195
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/ski/ski.h>
#include <console/console.h>
#include <console/chardev.h>
#include <arch/interrupt.h>
#include <sysinfo/sysinfo.h>
chardev_t ski_console;
chardev_t ski_uconsole;
static bool kb_disable;
int kbd_uspace=0;
static void ski_putchar(chardev_t *d, const char ch);
static __s32 ski_getchar(void);
/** Display character on debug console
*
* Use SSC (Simulator System Call) to
* display character on debug console.
*
* @param d Character device.
* @param ch Character to be printed.
*/
void ski_putchar(chardev_t *d, const char ch)
{
__asm__ volatile (
"mov r15=%0\n"
"mov r32=%1\n" /* r32 is in0 */
"break 0x80000\n" /* modifies r8 */
:
: "i" (SKI_PUTCHAR), "r" (ch)
: "r15", "in0", "r8"
);
if (ch == '\n')
ski_putchar(d, '\r');
}
/** Ask debug console if a key was pressed.
*
* Use SSC (Simulator System Call) to
* get character from debug console.
*
* This call is non-blocking.
*
* @return ASCII code of pressed key or 0 if no key pressed.
*/
__s32 ski_getchar(void)
{
__u64 ch;
__asm__ volatile (
"mov r15=%1\n"
"break 0x80000;;\n" /* modifies r8 */
"mov %0=r8;;\n"
: "=r" (ch)
: "i" (SKI_GETCHAR)
: "r15", "r8"
);
return (__s32) ch;
}
/**
* This is a blocking wrapper for ski_getchar().
* To be used when the kernel crashes.
*/
static char ski_getchar_blocking(chardev_t *d)
{
int ch;
while(!(ch=ski_getchar()))
;
if(ch == '\r')
ch = '\n';
return (char) ch;
}
/** Ask keyboard if a key was pressed. */
void poll_keyboard(void)
{
char ch;
static char last;
if (kb_disable)
return;
ch = ski_getchar();
if(ch == '\r')
ch = '\n';
if (ch){
if(kbd_uspace){
chardev_push_character(&ski_uconsole, ch);
virtual_interrupt(IRQ_KBD,NULL);
}
else {
chardev_push_character(&ski_console, ch);
}
last = ch;
return;
}
if (last){
if(kbd_uspace){
chardev_push_character(&ski_uconsole, 0);
virtual_interrupt(IRQ_KBD,NULL);
}
else {
}
last = 0;
}
}
/* Called from getc(). */
static void ski_kb_enable(chardev_t *d)
{
kb_disable = false;
}
/* Called from getc(). */
static void ski_kb_disable(chardev_t *d)
{
kb_disable = true;
}
static chardev_operations_t ski_ops = {
.resume = ski_kb_enable,
.suspend = ski_kb_disable,
.write = ski_putchar,
.read = ski_getchar_blocking
};
/** Initialize debug console
*
* Issue SSC (Simulator System Call) to
* to open debug console.
*/
void ski_init_console(void)
{
__asm__ volatile (
"mov r15=%0\n"
"break 0x80000\n"
:
: "i" (SKI_INIT_CONSOLE)
: "r15", "r8"
);
chardev_initialize("ski_console", &ski_console, &ski_ops);
chardev_initialize("ski_uconsole", &ski_uconsole, &ski_ops);
stdin = &ski_console;
stdout = &ski_console;
}
/** Setup console sysinfo (i.e. Keyboard IRQ)
*
* Because sysinfo neads memory allocation/dealocation
* this functions should be called separetely from init.
*
*/
void ski_set_console_sysinfo(void)
{
sysinfo_set_item_val("kbd",NULL,true);
sysinfo_set_item_val("kbd.irq",NULL,IRQ_KBD);
}

/tags/0.2.0/kernel/arch/ia64/src/drivers/it.c
0,0 → 1,96
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** Interval Timer driver. */
#include <arch/drivers/it.h>
#include <arch/ski/ski.h>
#include <arch/interrupt.h>
#include <arch/register.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <time/clock.h>
#include <arch.h>
#define IT_SERVICE_CLOCKS 64
/** Initialize Interval Timer. */
void it_init(void)
{
cr_itv_t itv;
/* initialize Interval Timer external interrupt vector */
itv.value = itv_read();
itv.vector = INTERRUPT_TIMER;
itv.m = 0;
itv_write(itv.value);
/* set Interval Timer Counter to zero */
itc_write(0);
/* generate first Interval Timer interrupt in IT_DELTA ticks */
itm_write(IT_DELTA);
/* propagate changes */
srlz_d();
}
/** Process Interval Timer interrupt. */
void it_interrupt(void)
{
__s64 c;
__s64 m;
eoi_write(EOI);
m=itm_read();
while(1)
{
c=itc_read();
c+=IT_SERVICE_CLOCKS;
m+=IT_DELTA;
if(m-c<0)
{
CPU->missed_clock_ticks++;
}
else break;
}
itm_write(m);
srlz_d(); /* propagate changes */
clock();
poll_keyboard();
}

/tags/0.2.0/kernel/arch/ia64/src/ddi/ddi.c
0,0 → 1,47
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <ddi/ddi.h>
#include <proc/task.h>
#include <arch/types.h>
#include <typedefs.h>
/** Enable I/O space range for task.
*
* Interrupts are disabled and task is locked.
*
* @param task Task.
* @param ioaddr Startign I/O space address.
* @param size Size of the enabled I/O range.
*
* @return 0 on success or an error code from errno.h.
*/
int ddi_iospace_enable_arch(task_t *task, __address ioaddr, size_t size)
{
return 0;
}

/tags/0.2.0/kernel/arch/ia64/src/start.S
0,0 → 1,139
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/register.h>
#include <arch/mm/page.h>
#include <arch/mm/asid.h>
#include <mm/asid.h>
#define RR_MASK (0xFFFFFFFF00000002)
#define RID_SHIFT 8
#define PS_SHIFT 2
#define KERNEL_TRANSLATION_I 0x0010000000000661
#define KERNEL_TRANSLATION_D 0x0010000000000661
.section K_TEXT_START, "ax"
.global kernel_image_start
stack0:
kernel_image_start:
.auto
# Fill TR.i and TR.d using Region Register #VRN_KERNEL
movl r8=(VRN_KERNEL<<VRN_SHIFT)
mov r9=rr[r8]
movl r10=(RR_MASK)
and r9=r10,r9
movl r10=((RID_KERNEL<<RID_SHIFT)|(KERNEL_PAGE_WIDTH<<PS_SHIFT))
or r9=r10,r9
mov rr[r8]=r9
movl r8=(VRN_KERNEL<<VRN_SHIFT)
mov cr.ifa=r8
movl r10=(KERNEL_PAGE_WIDTH<<PS_SHIFT)
mov cr.itir=r10
movl r10=(KERNEL_TRANSLATION_I)
itr.i itr[r0]=r10
movl r10=(KERNEL_TRANSLATION_D)
itr.d dtr[r0]=r10
# initialize PSR
mov psr.l = r0
srlz.i
srlz.d
movl r10=(PSR_DT_MASK|PSR_RT_MASK|PSR_IT_MASK|PSR_IC_MASK) /* Enable paging */
mov r9=psr
or r10=r10,r9
mov cr.ipsr=r10
mov cr.ifs=r0
movl r8=paging_start
mov cr.iip=r8
srlz.d
srlz.i
.explicit
/*
* Return From Interupt is the only the way to fill upper half word of PSR.
*/
rfi;;
.global paging_start
paging_start:
/*
* Now we are paging.
*/
# switch to register bank 1
bsw.1
# initialize register stack
mov ar.rsc = r0
movl r8=(VRN_KERNEL<<VRN_SHIFT) ;;
mov ar.bspstore = r8
loadrs
# initialize memory stack to some sane value
movl r12 = stack0;;
add r12 = - 16, r12 /* allocate a scratch area on the stack */
# initialize gp (Global Pointer) register
movl r1 = _hardcoded_load_address
/*
* Initialize hardcoded_* variables.
*/
movl r14 = _hardcoded_ktext_size
movl r15 = _hardcoded_kdata_size
movl r16 = _hardcoded_load_address ;;
addl r17 = @gprel(hardcoded_ktext_size), gp
addl r18 = @gprel(hardcoded_kdata_size), gp
addl r19 = @gprel(hardcoded_load_address), gp
;;
st8 [r17] = r14
st8 [r18] = r15
st8 [r19] = r16
ssm (1<<19);; /*Disable f32 - f127*/
srlz.i;
srlz.d;;
br.call.sptk.many b0 = arch_pre_main
movl r18=main_bsp ;;
mov b1=r18 ;;
br.call.sptk.many b0=b1
0:
br 0b

/tags/0.2.0/kernel/arch/ia64/src/proc/scheduler.c
0,0 → 1,78
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <proc/scheduler.h>
#include <proc/thread.h>
#include <arch.h>
#include <arch/register.h>
#include <arch/context.h>
#include <arch/stack.h>
#include <arch/mm/tlb.h>
#include <config.h>
#include <align.h>
/** Perform ia64 specific tasks needed before the new task is run. */
void before_task_runs_arch(void)
{
}
/** Prepare kernel stack pointers in bank 0 r22 and r23 and make sure the stack is mapped in DTR. */
void before_thread_runs_arch(void)
{
__address base;
base = ALIGN_DOWN(config.base, 1<<KERNEL_PAGE_WIDTH);
if ((__address) THREAD->kstack < base || (__address) THREAD->kstack > base + (1<<(KERNEL_PAGE_WIDTH))) {
/*
* Kernel stack of this thread is not mapped by DTR[TR_KERNEL].
* Use DTR[TR_KSTACK1] and DTR[TR_KSTACK2] to map it.
*/
dtlb_kernel_mapping_insert((__address) THREAD->kstack, KA2PA(THREAD->kstack), true, DTR_KSTACK1);
dtlb_kernel_mapping_insert((__address) THREAD->kstack + PAGE_SIZE, KA2PA(THREAD->kstack) + FRAME_SIZE, true, DTR_KSTACK2);
}
/*
* Record address of kernel backing store to bank 0 r22.
* Record address of kernel stack to bank 0 r23.
* These values will be found there after switch from userspace.
*/
__asm__ volatile (
"bsw.0\n"
"mov r22 = %0\n"
"mov r23 = %1\n"
"bsw.1\n"
:
: "r" (&THREAD->kstack[THREAD_STACK_SIZE]),
"r" (&THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA])
);
}
void after_thread_ran_arch(void)
{
}

/tags/0.2.0/kernel/arch/ia64/src/ivt.S
0,0 → 1,582
#
# Copyright (C) 2005 Jakub Vana
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/stack.h>
#include <arch/register.h>
#include <arch/mm/page.h>
#include <align.h>
#define FRS_TO_SAVE 30
#define STACK_ITEMS (19 + FRS_TO_SAVE*2)
#define STACK_FRAME_SIZE ALIGN_UP((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE, STACK_ALIGNMENT)
#if (STACK_ITEMS % 2 == 0)
# define STACK_FRAME_BIAS 8
#else
# define STACK_FRAME_BIAS 16
#endif
/** Partitioning of bank 0 registers. */
#define R_OFFS r16
#define R_HANDLER r17
#define R_RET r18
#define R_TMP r19
#define R_KSTACK_BSP r22 /* keep in sync with before_thread_runs_arch() */
#define R_KSTACK r23 /* keep in sync with before_thread_runs_arch() */
/** Heavyweight interrupt handler
*
* This macro roughly follows steps from 1 to 19 described in
* Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
*
* HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
* This goal is achieved by using procedure calls after RSE becomes operational.
*
* Some steps are skipped (enabling and disabling interrupts).
*
* @param offs Offset from the beginning of IVT.
* @param handler Interrupt handler address.
*/
.macro HEAVYWEIGHT_HANDLER offs, handler=universal_handler
.org ivt + \offs
mov R_OFFS = \offs
movl R_HANDLER = \handler ;;
br heavyweight_handler
.endm
.global heavyweight_handler
heavyweight_handler:
/* 1. copy interrupt registers into bank 0 */
/*
* Note that r24-r31 from bank 0 can be used only as long as PSR.ic = 0.
*/
/* Set up FPU as in interrupted context. */
mov r24 = psr
mov r25 = cr.ipsr
mov r26 = PSR_DFH_MASK
mov r27 = ~PSR_DFH_MASK ;;
and r26 = r25, r26
and r24 = r24, r27;;
or r24 = r24, r26;;
mov psr.l = r24;;
srlz.i
srlz.d;;
mov r24 = cr.iip
mov r25 = cr.ipsr
mov r26 = cr.iipa
mov r27 = cr.isr
mov r28 = cr.ifa
/* 2. preserve predicate register into bank 0 */
mov r29 = pr ;;
/* 3. switch to kernel memory stack */
mov r30 = cr.ipsr
shr.u r31 = r12, VRN_SHIFT ;;
shr.u r30 = r30, PSR_CPL_SHIFT ;;
and r30 = PSR_CPL_MASK_SHIFTED, r30 ;;
/*
* Set p3 to true if the interrupted context executed in kernel mode.
* Set p4 to false if the interrupted context didn't execute in kernel mode.
*/
cmp.eq p3, p4 = r30, r0 ;;
cmp.eq p1, p2 = r30, r0 ;; /* remember IPSR setting in p1 and p2 */
/*
* Set p3 to true if the stack register references kernel address space.
* Set p4 to false if the stack register doesn't reference kernel address space.
*/
(p3) cmp.eq p3, p4 = VRN_KERNEL, r31 ;;
/*
* Now, p4 is true iff the stack needs to be switched to kernel stack.
*/
mov r30 = r12
(p4) mov r12 = R_KSTACK ;;
add r31 = -STACK_FRAME_BIAS, r12 ;;
add r12 = -STACK_FRAME_SIZE, r12
/* 4. save registers in bank 0 into memory stack */
/*
* If this is break_instruction handler,
* copy input parameters to stack.
*/
mov R_TMP = 0x2c00 ;;
cmp.eq p6,p5 = R_OFFS, R_TMP ;;
/*
* From now on, if this is break_instruction handler, p6 is true and p5 is false.
* Otherwise p6 is false and p5 is true.
* Note that p5 is a preserved predicate register and we make use of it.
*/
(p6) st8 [r31] = r36, -8 ;; /* save in4 */
(p6) st8 [r31] = r35, -8 ;; /* save in3 */
(p6) st8 [r31] = r34, -8 ;; /* save in2 */
(p6) st8 [r31] = r33, -8 ;; /* save in1 */
(p6) st8 [r31] = r32, -8 ;; /* save in0 */
(p5) add r31 = -40, r31 ;;
st8 [r31] = r30, -8 ;; /* save old stack pointer */
st8 [r31] = r29, -8 ;; /* save predicate registers */
st8 [r31] = r24, -8 ;; /* save cr.iip */
st8 [r31] = r25, -8 ;; /* save cr.ipsr */
st8 [r31] = r26, -8 ;; /* save cr.iipa */
st8 [r31] = r27, -8 ;; /* save cr.isr */
st8 [r31] = r28, -8 ;; /* save cr.ifa */
/* 5. RSE switch from interrupted context */
mov r24 = ar.rsc
mov r25 = ar.pfs
cover
mov r26 = cr.ifs
st8 [r31] = r24, -8 ;; /* save ar.rsc */
st8 [r31] = r25, -8 ;; /* save ar.pfs */
st8 [r31] = r26, -8 /* save ar.ifs */
and r24 = ~(RSC_PL_MASK), r24 ;;
and r30 = ~(RSC_MODE_MASK), r24 ;;
mov ar.rsc = r30 ;; /* update RSE state */
mov r27 = ar.rnat
mov r28 = ar.bspstore ;;
/*
* Inspect BSPSTORE to figure out whether it is necessary to switch to kernel BSPSTORE.
*/
(p1) shr.u r30 = r28, VRN_SHIFT ;;
(p1) cmp.eq p1, p2 = VRN_KERNEL, r30 ;;
/*
* If BSPSTORE needs to be switched, p1 is false and p2 is true.
*/
(p1) mov r30 = r28
(p2) mov r30 = R_KSTACK_BSP ;;
(p2) mov ar.bspstore = r30 ;;
mov r29 = ar.bsp
st8 [r31] = r27, -8 ;; /* save ar.rnat */
st8 [r31] = r30, -8 ;; /* save new value written to ar.bspstore */
st8 [r31] = r28, -8 ;; /* save ar.bspstore */
st8 [r31] = r29, -8 /* save ar.bsp */
mov ar.rsc = r24 /* restore RSE's setting + kernel privileges */
/* steps 6 - 15 are done by heavyweight_handler_inner() */
mov R_RET = b0 /* save b0 belonging to interrupted context */
br.call.sptk.many b0 = heavyweight_handler_inner
0: mov b0 = R_RET /* restore b0 belonging to the interrupted context */
/* 16. RSE switch to interrupted context */
cover /* allocate zerro size frame (step 1 (from Intel Docs)) */
add r31 = (STACK_SCRATCH_AREA_SIZE+(FRS_TO_SAVE*2*8)), r12 ;;
ld8 r30 = [r31], +8 ;; /* load ar.bsp */
ld8 r29 = [r31], +8 ;; /* load ar.bspstore */
ld8 r28 = [r31], +8 ;; /* load ar.bspstore_new */
sub r27 = r30 , r28 ;; /* calculate loadrs (step 2) */
shl r27 = r27, 16
mov r24 = ar.rsc ;;
and r30 = ~3, r24 ;;
or r24 = r30 , r27 ;;
mov ar.rsc = r24 ;; /* place RSE in enforced lazy mode */
loadrs /* (step 3) */
ld8 r27 = [r31], +8 ;; /* load ar.rnat */
ld8 r26 = [r31], +8 ;; /* load cr.ifs */
ld8 r25 = [r31], +8 ;; /* load ar.pfs */
ld8 r24 = [r31], +8 ;; /* load ar.rsc */
mov ar.bspstore = r29 ;; /* (step 4) */
mov ar.rnat = r27 /* (step 5) */
mov ar.pfs = r25 /* (step 6) */
mov cr.ifs = r26
mov ar.rsc = r24 /* (step 7) */
/* 17. restore interruption state from memory stack */
ld8 r28 = [r31], +8 ;; /* load cr.ifa */
ld8 r27 = [r31], +8 ;; /* load cr.isr */
ld8 r26 = [r31], +8 ;; /* load cr.iipa */
ld8 r25 = [r31], +8 ;; /* load cr.ipsr */
ld8 r24 = [r31], +8 ;; /* load cr.iip */
mov cr.iip = r24;;
mov cr.iipa = r26
mov cr.isr = r27
mov cr.ifa = r28
/* Set up FPU as in exception. */
mov r24 = psr
mov r26 = PSR_DFH_MASK
mov r27 = ~PSR_DFH_MASK ;;
and r25 = r25, r27
and r24 = r24, r26 ;;
or r25 = r25, r24;;
mov cr.ipsr = r25
/* 18. restore predicate registers from memory stack */
ld8 r29 = [r31], +8 ;; /* load predicate registers */
mov pr = r29
/* 19. return from interruption */
ld8 r12 = [r31] /* load stack pointer */
rfi ;;
.global heavyweight_handler_inner
heavyweight_handler_inner:
/*
* From this point, the rest of the interrupted context
* will be preserved in stacked registers and backing store.
*/
alloc loc0 = ar.pfs, 0, 48, 2, 0 ;;
/* bank 0 is going to be shadowed, copy essential data from there */
mov loc1 = R_RET /* b0 belonging to interrupted context */
mov loc2 = R_HANDLER
mov out0 = R_OFFS
add out1 = STACK_SCRATCH_AREA_SIZE, r12
/* 6. switch to bank 1 and reenable PSR.ic */
ssm PSR_IC_MASK
bsw.1 ;;
srlz.d
/* 7. preserve branch and application registers */
mov loc3 = ar.unat
mov loc4 = ar.lc
mov loc5 = ar.ec
mov loc6 = ar.ccv
mov loc7 = ar.csd
mov loc8 = ar.ssd
mov loc9 = b0
mov loc10 = b1
mov loc11 = b2
mov loc12 = b3
mov loc13 = b4
mov loc14 = b5
mov loc15 = b6
mov loc16 = b7
/* 8. preserve general and floating-point registers */
mov loc17 = r1
mov loc18 = r2
mov loc19 = r3
mov loc20 = r4
mov loc21 = r5
mov loc22 = r6
mov loc23 = r7
(p5) mov loc24 = r8 /* only if not in break_instruction handler */
mov loc25 = r9
mov loc26 = r10
mov loc27 = r11
/* skip r12 (stack pointer) */
mov loc28 = r13
mov loc29 = r14
mov loc30 = r15
mov loc31 = r16
mov loc32 = r17
mov loc33 = r18
mov loc34 = r19
mov loc35 = r20
mov loc36 = r21
mov loc37 = r22
mov loc38 = r23
mov loc39 = r24
mov loc40 = r25
mov loc41 = r26
mov loc42 = r27
mov loc43 = r28
mov loc44 = r29
mov loc45 = r30
mov loc46 = r31
add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12
add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12
add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12
add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12
add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12
add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12
add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12
add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;
stf.spill [r26] = f2, 0x80
stf.spill [r27] = f3, 0x80
stf.spill [r28] = f4, 0x80
stf.spill [r29] = f5, 0x80
stf.spill [r30] = f6, 0x80
stf.spill [r31] = f7, 0x80 ;;
stf.spill [r24] = f8, 0x80
stf.spill [r25] = f9, 0x80
stf.spill [r26] = f10, 0x80
stf.spill [r27] = f11, 0x80
stf.spill [r28] = f12, 0x80
stf.spill [r29] = f13, 0x80
stf.spill [r30] = f14, 0x80
stf.spill [r31] = f15, 0x80 ;;
stf.spill [r24] = f16, 0x80
stf.spill [r25] = f17, 0x80
stf.spill [r26] = f18, 0x80
stf.spill [r27] = f19, 0x80
stf.spill [r28] = f20, 0x80
stf.spill [r29] = f21, 0x80
stf.spill [r30] = f22, 0x80
stf.spill [r31] = f23, 0x80 ;;
stf.spill [r24] = f24, 0x80
stf.spill [r25] = f25, 0x80
stf.spill [r26] = f26, 0x80
stf.spill [r27] = f27, 0x80
stf.spill [r28] = f28, 0x80
stf.spill [r29] = f29, 0x80
stf.spill [r30] = f30, 0x80
stf.spill [r31] = f31, 0x80 ;;
mov loc47 = ar.fpsr /* preserve floating point status register */
/* 9. skipped (will not enable interrupts) */
/*
* ssm PSR_I_MASK
* ;;
* srlz.d
*/
/* 10. call handler */
movl r1 = _hardcoded_load_address
mov b1 = loc2
br.call.sptk.many b0 = b1
/* 11. return from handler */
0:
/* 12. skipped (will not disable interrupts) */
/*
* rsm PSR_I_MASK
* ;;
* srlz.d
*/
/* 13. restore general and floating-point registers */
add r24 = 96 + STACK_SCRATCH_AREA_SIZE, r12
add r25 = 112 + STACK_SCRATCH_AREA_SIZE, r12
add r26 = 0 + STACK_SCRATCH_AREA_SIZE, r12
add r27 = 16 + STACK_SCRATCH_AREA_SIZE, r12
add r28 = 32 + STACK_SCRATCH_AREA_SIZE, r12
add r29 = 48 + STACK_SCRATCH_AREA_SIZE, r12
add r30 = 64 + STACK_SCRATCH_AREA_SIZE, r12
add r31 = 80 + STACK_SCRATCH_AREA_SIZE, r12 ;;
ldf.fill f2 = [r26], 0x80
ldf.fill f3 = [r27], 0x80
ldf.fill f4 = [r28], 0x80
ldf.fill f5 = [r29], 0x80
ldf.fill f6 = [r30], 0x80
ldf.fill f7 = [r31], 0x80 ;;
ldf.fill f8 = [r24], 0x80
ldf.fill f9 = [r25], 0x80
ldf.fill f10 = [r26], 0x80
ldf.fill f11 = [r27], 0x80
ldf.fill f12 = [r28], 0x80
ldf.fill f13 = [r29], 0x80
ldf.fill f14 = [r30], 0x80
ldf.fill f15 = [r31], 0x80 ;;
ldf.fill f16 = [r24], 0x80
ldf.fill f17 = [r25], 0x80
ldf.fill f18 = [r26], 0x80
ldf.fill f19 = [r27], 0x80
ldf.fill f20 = [r28], 0x80
ldf.fill f21 = [r29], 0x80
ldf.fill f22 = [r30], 0x80
ldf.fill f23 = [r31], 0x80 ;;
ldf.fill f24 = [r24], 0x80
ldf.fill f25 = [r25], 0x80
ldf.fill f26 = [r26], 0x80
ldf.fill f27 = [r27], 0x80
ldf.fill f28 = [r28], 0x80
ldf.fill f29 = [r29], 0x80
ldf.fill f30 = [r30], 0x80
ldf.fill f31 = [r31], 0x80 ;;
mov r1 = loc17
mov r2 = loc18
mov r3 = loc19
mov r4 = loc20
mov r5 = loc21
mov r6 = loc22
mov r7 = loc23
(p5) mov r8 = loc24 /* only if not in break_instruction handler */
mov r9 = loc25
mov r10 = loc26
mov r11 = loc27
/* skip r12 (stack pointer) */
mov r13 = loc28
mov r14 = loc29
mov r15 = loc30
mov r16 = loc31
mov r17 = loc32
mov r18 = loc33
mov r19 = loc34
mov r20 = loc35
mov r21 = loc36
mov r22 = loc37
mov r23 = loc38
mov r24 = loc39
mov r25 = loc40
mov r26 = loc41
mov r27 = loc42
mov r28 = loc43
mov r29 = loc44
mov r30 = loc45
mov r31 = loc46
mov ar.fpsr = loc47 /* restore floating point status register */
/* 14. restore branch and application registers */
mov ar.unat = loc3
mov ar.lc = loc4
mov ar.ec = loc5
mov ar.ccv = loc6
mov ar.csd = loc7
mov ar.ssd = loc8
mov b0 = loc9
mov b1 = loc10
mov b2 = loc11
mov b3 = loc12
mov b4 = loc13
mov b5 = loc14
mov b6 = loc15
mov b7 = loc16
/* 15. disable PSR.ic and switch to bank 0 */
rsm PSR_IC_MASK
bsw.0 ;;
srlz.d
mov R_RET = loc1
mov ar.pfs = loc0
br.ret.sptk.many b0
.global ivt
.align 32768
ivt:
HEAVYWEIGHT_HANDLER 0x0000
HEAVYWEIGHT_HANDLER 0x0400
HEAVYWEIGHT_HANDLER 0x0800
HEAVYWEIGHT_HANDLER 0x0c00 alternate_instruction_tlb_fault
HEAVYWEIGHT_HANDLER 0x1000 alternate_data_tlb_fault
HEAVYWEIGHT_HANDLER 0x1400 data_nested_tlb_fault
HEAVYWEIGHT_HANDLER 0x1800
HEAVYWEIGHT_HANDLER 0x1c00
HEAVYWEIGHT_HANDLER 0x2000 data_dirty_bit_fault
HEAVYWEIGHT_HANDLER 0x2400 instruction_access_bit_fault
HEAVYWEIGHT_HANDLER 0x2800 data_access_bit_fault
HEAVYWEIGHT_HANDLER 0x2c00 break_instruction
HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */
HEAVYWEIGHT_HANDLER 0x3400
HEAVYWEIGHT_HANDLER 0x3800
HEAVYWEIGHT_HANDLER 0x3c00
HEAVYWEIGHT_HANDLER 0x4000
HEAVYWEIGHT_HANDLER 0x4400
HEAVYWEIGHT_HANDLER 0x4800
HEAVYWEIGHT_HANDLER 0x4c00
HEAVYWEIGHT_HANDLER 0x5000 page_not_present
HEAVYWEIGHT_HANDLER 0x5100
HEAVYWEIGHT_HANDLER 0x5200
HEAVYWEIGHT_HANDLER 0x5300
HEAVYWEIGHT_HANDLER 0x5400 general_exception
HEAVYWEIGHT_HANDLER 0x5500 disabled_fp_register
HEAVYWEIGHT_HANDLER 0x5600
HEAVYWEIGHT_HANDLER 0x5700
HEAVYWEIGHT_HANDLER 0x5800
HEAVYWEIGHT_HANDLER 0x5900
HEAVYWEIGHT_HANDLER 0x5a00
HEAVYWEIGHT_HANDLER 0x5b00
HEAVYWEIGHT_HANDLER 0x5c00
HEAVYWEIGHT_HANDLER 0x5d00
HEAVYWEIGHT_HANDLER 0x5e00
HEAVYWEIGHT_HANDLER 0x5f00
HEAVYWEIGHT_HANDLER 0x6000
HEAVYWEIGHT_HANDLER 0x6100
HEAVYWEIGHT_HANDLER 0x6200
HEAVYWEIGHT_HANDLER 0x6300
HEAVYWEIGHT_HANDLER 0x6400
HEAVYWEIGHT_HANDLER 0x6500
HEAVYWEIGHT_HANDLER 0x6600
HEAVYWEIGHT_HANDLER 0x6700
HEAVYWEIGHT_HANDLER 0x6800
HEAVYWEIGHT_HANDLER 0x6900
HEAVYWEIGHT_HANDLER 0x6a00
HEAVYWEIGHT_HANDLER 0x6b00
HEAVYWEIGHT_HANDLER 0x6c00
HEAVYWEIGHT_HANDLER 0x6d00
HEAVYWEIGHT_HANDLER 0x6e00
HEAVYWEIGHT_HANDLER 0x6f00
HEAVYWEIGHT_HANDLER 0x7000
HEAVYWEIGHT_HANDLER 0x7100
HEAVYWEIGHT_HANDLER 0x7200
HEAVYWEIGHT_HANDLER 0x7300
HEAVYWEIGHT_HANDLER 0x7400
HEAVYWEIGHT_HANDLER 0x7500
HEAVYWEIGHT_HANDLER 0x7600
HEAVYWEIGHT_HANDLER 0x7700
HEAVYWEIGHT_HANDLER 0x7800
HEAVYWEIGHT_HANDLER 0x7900
HEAVYWEIGHT_HANDLER 0x7a00
HEAVYWEIGHT_HANDLER 0x7b00
HEAVYWEIGHT_HANDLER 0x7c00
HEAVYWEIGHT_HANDLER 0x7d00
HEAVYWEIGHT_HANDLER 0x7e00
HEAVYWEIGHT_HANDLER 0x7f00

/tags/0.2.0/kernel/arch/ia64/src/context.S
0,0 → 1,246
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
.global context_save_arch
.global context_restore_arch
context_save_arch:
alloc loc0 = ar.pfs, 1, 8, 0, 0
mov loc1 = ar.unat ;;
/* loc2 */
mov loc3 = ar.rsc
.auto
/*
* Flush dirty registers to backing store.
* After this ar.bsp and ar.bspstore are equal.
*/
flushrs
mov loc4 = ar.bsp
/*
* Put RSE to enforced lazy mode.
* So that ar.rnat can be read.
*/
and loc5 = ~3, loc3
mov ar.rsc = loc5
mov loc5 = ar.rnat
.explicit
mov loc6 = ar.lc
/*
* Save application registers
*/
st8 [in0] = loc0, 8 ;; /* save ar.pfs */
st8 [in0] = loc1, 8 ;; /* save ar.unat (caller) */
mov loc2 = in0 ;;
add in0 = 8, in0 ;; /* skip ar.unat (callee) */
st8 [in0] = loc3, 8 ;; /* save ar.rsc */
st8 [in0] = loc4, 8 ;; /* save ar.bsp */
st8 [in0] = loc5, 8 ;; /* save ar.rnat */
st8 [in0] = loc6, 8 ;; /* save ar.lc */
/*
* Save general registers including NaT bits
*/
st8.spill [in0] = r1, 8 ;;
st8.spill [in0] = r4, 8 ;;
st8.spill [in0] = r5, 8 ;;
st8.spill [in0] = r6, 8 ;;
st8.spill [in0] = r7, 8 ;;
st8.spill [in0] = r12, 8 ;; /* save sp */
st8.spill [in0] = r13, 8 ;;
mov loc3 = ar.unat ;;
st8 [loc2] = loc3 /* save ar.unat (callee) */
/*
* Save branch registers
*/
mov loc2 = b0 ;;
st8 [in0] = loc2, 8 /* save pc */
mov loc3 = b1 ;;
st8 [in0] = loc3, 8
mov loc4 = b2 ;;
st8 [in0] = loc4, 8
mov loc5 = b3 ;;
st8 [in0] = loc5, 8
mov loc6 = b4 ;;
st8 [in0] = loc6, 8
mov loc7 = b5 ;;
st8 [in0] = loc7, 8
/*
* Save predicate registers
*/
mov loc2 = pr ;;
st8 [in0] = loc2, 16;; /* Next fpu registers should be spilled to 16B aligned address */
/*
* Save floating-point registers.
*/
stf.spill [in0] = f2, 16 ;;
stf.spill [in0] = f3, 16 ;;
stf.spill [in0] = f4, 16 ;;
stf.spill [in0] = f5, 16 ;;
stf.spill [in0] = f16, 16 ;;
stf.spill [in0] = f17, 16 ;;
stf.spill [in0] = f18, 16 ;;
stf.spill [in0] = f19, 16 ;;
stf.spill [in0] = f20, 16 ;;
stf.spill [in0] = f21, 16 ;;
stf.spill [in0] = f22, 16 ;;
stf.spill [in0] = f23, 16 ;;
stf.spill [in0] = f24, 16 ;;
stf.spill [in0] = f25, 16 ;;
stf.spill [in0] = f26, 16 ;;
stf.spill [in0] = f27, 16 ;;
stf.spill [in0] = f28, 16 ;;
stf.spill [in0] = f29, 16 ;;
stf.spill [in0] = f30, 16 ;;
stf.spill [in0] = f31, 16 ;;
mov ar.unat = loc1
add r8 = r0, r0, 1 /* context_save returns 1 */
br.ret.sptk.many b0
context_restore_arch:
alloc loc0 = ar.pfs, 1, 9, 0, 0 ;;
ld8 loc0 = [in0], 8 ;; /* load ar.pfs */
ld8 loc1 = [in0], 8 ;; /* load ar.unat (caller) */
ld8 loc2 = [in0], 8 ;; /* load ar.unat (callee) */
ld8 loc3 = [in0], 8 ;; /* load ar.rsc */
ld8 loc4 = [in0], 8 ;; /* load ar.bsp */
ld8 loc5 = [in0], 8 ;; /* load ar.rnat */
ld8 loc6 = [in0], 8 ;; /* load ar.lc */
.auto
/*
* Invalidate the ALAT
*/
invala
/*
* Put RSE to enforced lazy mode.
* So that ar.bspstore and ar.rnat can be written.
*/
movl loc8 = ~3
and loc8 = loc3, loc8
mov ar.rsc = loc8
/*
* Flush dirty registers to backing store.
* We do this because we want the following move
* to ar.bspstore to assign the same value to ar.bsp.
*/
flushrs
/*
* Restore application registers
*/
mov ar.bspstore = loc4 /* rse.bspload = ar.bsp = ar.bspstore = loc4 */
mov ar.rnat = loc5
mov ar.pfs = loc0
mov ar.rsc = loc3
.explicit
mov ar.unat = loc2 ;;
mov ar.lc = loc6
/*
* Restore general registers including NaT bits
*/
ld8.fill r1 = [in0], 8 ;;
ld8.fill r4 = [in0], 8 ;;
ld8.fill r5 = [in0], 8 ;;
ld8.fill r6 = [in0], 8 ;;
ld8.fill r7 = [in0], 8 ;;
ld8.fill r12 = [in0], 8 ;; /* restore sp */
ld8.fill r13 = [in0], 8 ;;
/*
* Restore branch registers
*/
ld8 loc2 = [in0], 8 ;; /* restore pc */
mov b0 = loc2
ld8 loc3 = [in0], 8 ;;
mov b1 = loc3
ld8 loc4 = [in0], 8 ;;
mov b2 = loc4
ld8 loc5 = [in0], 8 ;;
mov b3 = loc5
ld8 loc6 = [in0], 8 ;;
mov b4 = loc6
ld8 loc7 = [in0], 8 ;;
mov b5 = loc7
/*
* Restore predicate registers
*/
ld8 loc2 = [in0], 16 ;;
mov pr = loc2, ~0
/*
* Restore floating-point registers.
*/
ldf.fill f2 = [in0], 16 ;;
ldf.fill f3 = [in0], 16 ;;
ldf.fill f4 = [in0], 16 ;;
ldf.fill f5 = [in0], 16 ;;
ldf.fill f16 = [in0], 16 ;;
ldf.fill f17 = [in0], 16 ;;
ldf.fill f18 = [in0], 16 ;;
ldf.fill f19 = [in0], 16 ;;
ldf.fill f20 = [in0], 16 ;;
ldf.fill f21 = [in0], 16 ;;
ldf.fill f22 = [in0], 16 ;;
ldf.fill f23 = [in0], 16 ;;
ldf.fill f24 = [in0], 16 ;;
ldf.fill f25 = [in0], 16 ;;
ldf.fill f26 = [in0], 16 ;;
ldf.fill f27 = [in0], 16 ;;
ldf.fill f28 = [in0], 16 ;;
ldf.fill f29 = [in0], 16 ;;
ldf.fill f30 = [in0], 16 ;;
ldf.fill f31 = [in0], 16 ;;
mov ar.unat = loc1
mov r8 = r0 /* context_restore returns 0 */
br.ret.sptk.many b0

/tags/0.2.0/kernel/arch/ia64/src/fpu_context.c
0,0 → 1,475
/*
* Copyright (C) 2005 Jakub Vana
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <fpu_context.h>
#include <arch/register.h>
#include <print.h>
void fpu_context_save(fpu_context_t *fctx){
asm volatile(
"stf.spill [%0]=f32,0x80\n"
"stf.spill [%1]=f33,0x80\n"
"stf.spill [%2]=f34,0x80\n"
"stf.spill [%3]=f35,0x80\n"
"stf.spill [%4]=f36,0x80\n"
"stf.spill [%5]=f37,0x80\n"
"stf.spill [%6]=f38,0x80\n"
"stf.spill [%7]=f39,0x80\n;;"
"stf.spill [%0]=f40,0x80\n"
"stf.spill [%1]=f41,0x80\n"
"stf.spill [%2]=f42,0x80\n"
"stf.spill [%3]=f43,0x80\n"
"stf.spill [%4]=f44,0x80\n"
"stf.spill [%5]=f45,0x80\n"
"stf.spill [%6]=f46,0x80\n"
"stf.spill [%7]=f47,0x80\n;;"
"stf.spill [%0]=f48,0x80\n"
"stf.spill [%1]=f49,0x80\n"
"stf.spill [%2]=f50,0x80\n"
"stf.spill [%3]=f51,0x80\n"
"stf.spill [%4]=f52,0x80\n"
"stf.spill [%5]=f53,0x80\n"
"stf.spill [%6]=f54,0x80\n"
"stf.spill [%7]=f55,0x80\n;;"
"stf.spill [%0]=f56,0x80\n"
"stf.spill [%1]=f57,0x80\n"
"stf.spill [%2]=f58,0x80\n"
"stf.spill [%3]=f59,0x80\n"
"stf.spill [%4]=f60,0x80\n"
"stf.spill [%5]=f61,0x80\n"
"stf.spill [%6]=f62,0x80\n"
"stf.spill [%7]=f63,0x80\n;;"
"stf.spill [%0]=f64,0x80\n"
"stf.spill [%1]=f65,0x80\n"
"stf.spill [%2]=f66,0x80\n"
"stf.spill [%3]=f67,0x80\n"
"stf.spill [%4]=f68,0x80\n"
"stf.spill [%5]=f69,0x80\n"
"stf.spill [%6]=f70,0x80\n"
"stf.spill [%7]=f71,0x80\n;;"
"stf.spill [%0]=f72,0x80\n"
"stf.spill [%1]=f73,0x80\n"
"stf.spill [%2]=f74,0x80\n"
"stf.spill [%3]=f75,0x80\n"
"stf.spill [%4]=f76,0x80\n"
"stf.spill [%5]=f77,0x80\n"
"stf.spill [%6]=f78,0x80\n"
"stf.spill [%7]=f79,0x80\n;;"
"stf.spill [%0]=f80,0x80\n"
"stf.spill [%1]=f81,0x80\n"
"stf.spill [%2]=f82,0x80\n"
"stf.spill [%3]=f83,0x80\n"
"stf.spill [%4]=f84,0x80\n"
"stf.spill [%5]=f85,0x80\n"
"stf.spill [%6]=f86,0x80\n"
"stf.spill [%7]=f87,0x80\n;;"
"stf.spill [%0]=f88,0x80\n"
"stf.spill [%1]=f89,0x80\n"
"stf.spill [%2]=f90,0x80\n"
"stf.spill [%3]=f91,0x80\n"
"stf.spill [%4]=f92,0x80\n"
"stf.spill [%5]=f93,0x80\n"
"stf.spill [%6]=f94,0x80\n"
"stf.spill [%7]=f95,0x80\n;;"
"stf.spill [%0]=f96,0x80\n"
"stf.spill [%1]=f97,0x80\n"
"stf.spill [%2]=f98,0x80\n"
"stf.spill [%3]=f99,0x80\n"
"stf.spill [%4]=f100,0x80\n"
"stf.spill [%5]=f101,0x80\n"
"stf.spill [%6]=f102,0x80\n"
"stf.spill [%7]=f103,0x80\n;;"
"stf.spill [%0]=f104,0x80\n"
"stf.spill [%1]=f105,0x80\n"
"stf.spill [%2]=f106,0x80\n"
"stf.spill [%3]=f107,0x80\n"
"stf.spill [%4]=f108,0x80\n"
"stf.spill [%5]=f109,0x80\n"
"stf.spill [%6]=f110,0x80\n"
"stf.spill [%7]=f111,0x80\n;;"
"stf.spill [%0]=f112,0x80\n"
"stf.spill [%1]=f113,0x80\n"
"stf.spill [%2]=f114,0x80\n"
"stf.spill [%3]=f115,0x80\n"
"stf.spill [%4]=f116,0x80\n"
"stf.spill [%5]=f117,0x80\n"
"stf.spill [%6]=f118,0x80\n"
"stf.spill [%7]=f119,0x80\n;;"
"stf.spill [%0]=f120,0x80\n"
"stf.spill [%1]=f121,0x80\n"
"stf.spill [%2]=f122,0x80\n"
"stf.spill [%3]=f123,0x80\n"
"stf.spill [%4]=f124,0x80\n"
"stf.spill [%5]=f125,0x80\n"
"stf.spill [%6]=f126,0x80\n"
"stf.spill [%7]=f127,0x80\n;;"
:
:"r" (&((fctx->fr)[0])),"r" (&((fctx->fr)[1])),"r" (&((fctx->fr)[2])),"r" (&((fctx->fr)[3])),
"r" (&((fctx->fr)[4])),"r" (&((fctx->fr)[5])),"r" (&((fctx->fr)[6])),"r" (&((fctx->fr)[7]))
);
}
void fpu_context_restore(fpu_context_t *fctx)
{
asm volatile(
"ldf.fill f32=[%0],0x80\n"
"ldf.fill f33=[%1],0x80\n"
"ldf.fill f34=[%2],0x80\n"
"ldf.fill f35=[%3],0x80\n"
"ldf.fill f36=[%4],0x80\n"
"ldf.fill f37=[%5],0x80\n"
"ldf.fill f38=[%6],0x80\n"
"ldf.fill f39=[%7],0x80\n;;"
"ldf.fill f40=[%0],0x80\n"
"ldf.fill f41=[%1],0x80\n"
"ldf.fill f42=[%2],0x80\n"
"ldf.fill f43=[%3],0x80\n"
"ldf.fill f44=[%4],0x80\n"
"ldf.fill f45=[%5],0x80\n"
"ldf.fill f46=[%6],0x80\n"
"ldf.fill f47=[%7],0x80\n;;"
"ldf.fill f48=[%0],0x80\n"
"ldf.fill f49=[%1],0x80\n"
"ldf.fill f50=[%2],0x80\n"
"ldf.fill f51=[%3],0x80\n"
"ldf.fill f52=[%4],0x80\n"
"ldf.fill f53=[%5],0x80\n"
"ldf.fill f54=[%6],0x80\n"
"ldf.fill f55=[%7],0x80\n;;"
"ldf.fill f56=[%0],0x80\n"
"ldf.fill f57=[%1],0x80\n"
"ldf.fill f58=[%2],0x80\n"
"ldf.fill f59=[%3],0x80\n"
"ldf.fill f60=[%4],0x80\n"
"ldf.fill f61=[%5],0x80\n"
"ldf.fill f62=[%6],0x80\n"
"ldf.fill f63=[%7],0x80\n;;"
"ldf.fill f64=[%0],0x80\n"
"ldf.fill f65=[%1],0x80\n"
"ldf.fill f66=[%2],0x80\n"
"ldf.fill f67=[%3],0x80\n"
"ldf.fill f68=[%4],0x80\n"
"ldf.fill f69=[%5],0x80\n"
"ldf.fill f70=[%6],0x80\n"
"ldf.fill f71=[%7],0x80\n;;"
"ldf.fill f72=[%0],0x80\n"
"ldf.fill f73=[%1],0x80\n"
"ldf.fill f74=[%2],0x80\n"
"ldf.fill f75=[%3],0x80\n"
"ldf.fill f76=[%4],0x80\n"
"ldf.fill f77=[%5],0x80\n"
"ldf.fill f78=[%6],0x80\n"
"ldf.fill f79=[%7],0x80\n;;"
"ldf.fill f80=[%0],0x80\n"
"ldf.fill f81=[%1],0x80\n"
"ldf.fill f82=[%2],0x80\n"
"ldf.fill f83=[%3],0x80\n"
"ldf.fill f84=[%4],0x80\n"
"ldf.fill f85=[%5],0x80\n"
"ldf.fill f86=[%6],0x80\n"
"ldf.fill f87=[%7],0x80\n;;"
"ldf.fill f88=[%0],0x80\n"
"ldf.fill f89=[%1],0x80\n"
"ldf.fill f90=[%2],0x80\n"
"ldf.fill f91=[%3],0x80\n"
"ldf.fill f92=[%4],0x80\n"
"ldf.fill f93=[%5],0x80\n"
"ldf.fill f94=[%6],0x80\n"
"ldf.fill f95=[%7],0x80\n;;"
"ldf.fill f96=[%0],0x80\n"
"ldf.fill f97=[%1],0x80\n"
"ldf.fill f98=[%2],0x80\n"
"ldf.fill f99=[%3],0x80\n"
"ldf.fill f100=[%4],0x80\n"
"ldf.fill f101=[%5],0x80\n"
"ldf.fill f102=[%6],0x80\n"
"ldf.fill f103=[%7],0x80\n;;"
"ldf.fill f104=[%0],0x80\n"
"ldf.fill f105=[%1],0x80\n"
"ldf.fill f106=[%2],0x80\n"
"ldf.fill f107=[%3],0x80\n"
"ldf.fill f108=[%4],0x80\n"
"ldf.fill f109=[%5],0x80\n"
"ldf.fill f110=[%6],0x80\n"
"ldf.fill f111=[%7],0x80\n;;"
"ldf.fill f112=[%0],0x80\n"
"ldf.fill f113=[%1],0x80\n"
"ldf.fill f114=[%2],0x80\n"
"ldf.fill f115=[%3],0x80\n"
"ldf.fill f116=[%4],0x80\n"
"ldf.fill f117=[%5],0x80\n"
"ldf.fill f118=[%6],0x80\n"
"ldf.fill f119=[%7],0x80\n;;"
"ldf.fill f120=[%0],0x80\n"
"ldf.fill f121=[%1],0x80\n"
"ldf.fill f122=[%2],0x80\n"
"ldf.fill f123=[%3],0x80\n"
"ldf.fill f124=[%4],0x80\n"
"ldf.fill f125=[%5],0x80\n"
"ldf.fill f126=[%6],0x80\n"
"ldf.fill f127=[%7],0x80\n;;"
:
:"r" (&((fctx->fr)[0])),"r" (&((fctx->fr)[1])),"r" (&((fctx->fr)[2])),"r" (&((fctx->fr)[3])),
"r" (&((fctx->fr)[4])),"r" (&((fctx->fr)[5])),"r" (&((fctx->fr)[6])),"r" (&((fctx->fr)[7]))
);
}
void fpu_enable(void)
{
__u64 a = 0 ;
asm volatile(
"rsm %0;;"
"srlz.i\n"
"srlz.d;;\n"
:
:"i" (PSR_DFH_MASK)
);
asm volatile
(
"mov %0=ar.fpsr;;\n"
"or %0=%0,%1;;\n"
"mov ar.fpsr=%0;;\n"
: "+r" (a)
: "r" (0x38)
);
}
void fpu_disable(void)
{
__u64 a = 0 ;
asm volatile(
"ssm %0;;\n"
"srlz.i\n"
"srlz.d;;\n"
:
:"i" (PSR_DFH_MASK)
);
asm volatile
(
"mov %0=ar.fpsr;;\n"
"or %0=%0,%1;;\n"
"mov ar.fpsr=%0;;\n"
: "+r" (a)
: "r" (0x38)
);
}
void fpu_init(void)
{
__u64 a = 0 ;
asm volatile
(
"mov %0=ar.fpsr;;\n"
"or %0=%0,%1;;\n"
"mov ar.fpsr=%0;;\n"
: "+r" (a)
: "r" (0x38)
);
asm volatile(
"mov f2=f0\n"
"mov f3=f0\n"
"mov f4=f0\n"
"mov f5=f0\n"
"mov f6=f0\n"
"mov f7=f0\n"
"mov f8=f0\n"
"mov f9=f0\n"
"mov f10=f0\n"
"mov f11=f0\n"
"mov f12=f0\n"
"mov f13=f0\n"
"mov f14=f0\n"
"mov f15=f0\n"
"mov f16=f0\n"
"mov f17=f0\n"
"mov f18=f0\n"
"mov f19=f0\n"
"mov f20=f0\n"
"mov f21=f0\n"
"mov f22=f0\n"
"mov f23=f0\n"
"mov f24=f0\n"
"mov f25=f0\n"
"mov f26=f0\n"
"mov f27=f0\n"
"mov f28=f0\n"
"mov f29=f0\n"
"mov f30=f0\n"
"mov f31=f0\n"
"mov f32=f0\n"
"mov f33=f0\n"
"mov f34=f0\n"
"mov f35=f0\n"
"mov f36=f0\n"
"mov f37=f0\n"
"mov f38=f0\n"
"mov f39=f0\n"
"mov f40=f0\n"
"mov f41=f0\n"
"mov f42=f0\n"
"mov f43=f0\n"
"mov f44=f0\n"
"mov f45=f0\n"
"mov f46=f0\n"
"mov f47=f0\n"
"mov f48=f0\n"
"mov f49=f0\n"
"mov f50=f0\n"
"mov f51=f0\n"
"mov f52=f0\n"
"mov f53=f0\n"
"mov f54=f0\n"
"mov f55=f0\n"
"mov f56=f0\n"
"mov f57=f0\n"
"mov f58=f0\n"
"mov f59=f0\n"
"mov f60=f0\n"
"mov f61=f0\n"
"mov f62=f0\n"
"mov f63=f0\n"
"mov f64=f0\n"
"mov f65=f0\n"
"mov f66=f0\n"
"mov f67=f0\n"
"mov f68=f0\n"
"mov f69=f0\n"
"mov f70=f0\n"
"mov f71=f0\n"
"mov f72=f0\n"
"mov f73=f0\n"
"mov f74=f0\n"
"mov f75=f0\n"
"mov f76=f0\n"
"mov f77=f0\n"
"mov f78=f0\n"
"mov f79=f0\n"
"mov f80=f0\n"
"mov f81=f0\n"
"mov f82=f0\n"
"mov f83=f0\n"
"mov f84=f0\n"
"mov f85=f0\n"
"mov f86=f0\n"
"mov f87=f0\n"
"mov f88=f0\n"
"mov f89=f0\n"
"mov f90=f0\n"
"mov f91=f0\n"
"mov f92=f0\n"
"mov f93=f0\n"
"mov f94=f0\n"
"mov f95=f0\n"
"mov f96=f0\n"
"mov f97=f0\n"
"mov f98=f0\n"
"mov f99=f0\n"
"mov f100=f0\n"
"mov f101=f0\n"
"mov f102=f0\n"
"mov f103=f0\n"
"mov f104=f0\n"
"mov f105=f0\n"
"mov f106=f0\n"
"mov f107=f0\n"
"mov f108=f0\n"
"mov f109=f0\n"
"mov f110=f0\n"
"mov f111=f0\n"
"mov f112=f0\n"
"mov f113=f0\n"
"mov f114=f0\n"
"mov f115=f0\n"
"mov f116=f0\n"
"mov f117=f0\n"
"mov f118=f0\n"
"mov f119=f0\n"
"mov f120=f0\n"
"mov f121=f0\n"
"mov f122=f0\n"
"mov f123=f0\n"
"mov f124=f0\n"
"mov f125=f0\n"
"mov f126=f0\n"
"mov f127=f0\n"
);
}

/tags/0.2.0/kernel/arch/ia64/src/dummy.s
0,0 → 1,42
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
.global calibrate_delay_loop
.global asm_delay_loop
.global cpu_sleep
.global dummy
calibrate_delay_loop:
asm_delay_loop:
cpu_sleep:
dummy:
br.ret.sptk.many b0

/tags/0.2.0/kernel/arch/ia64/src/putchar.c
0,0 → 1,35
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <putchar.h>
#include <arch/ski/ski.h>
void putchar(const char ch)
{
ski_write(ch);
}

/tags/0.2.0/kernel/arch/ia64/src/cpu/cpu.c
0,0 → 1,67
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <cpu.h>
#include <arch.h>
#include <arch/register.h>
#include <print.h>
void cpu_arch_init(void)
{
}
void cpu_identify(void)
{
CPU->arch.cpuid0 = cpuid_read(0);
CPU->arch.cpuid1 = cpuid_read(1);
CPU->arch.cpuid3.value = cpuid_read(3);
}
void cpu_print_report(cpu_t *m)
{
char *family_str;
char vendor[2*sizeof(__u64)+1];
*((__u64 *) &vendor[0*sizeof(__u64)]) = CPU->arch.cpuid0;
*((__u64 *) &vendor[1*sizeof(__u64)]) = CPU->arch.cpuid1;
vendor[sizeof(vendor)-1] = '\0';
switch(m->arch.cpuid3.family) {
case FAMILY_ITANIUM:
family_str = "Itanium";
break;
case FAMILY_ITANIUM2:
family_str = "Itanium 2";
break;
default:
family_str = "Unknown";
break;
}
printf("cpu%d: %s (%s), archrev=%d, model=%d, revision=%d\n", CPU->id, family_str, vendor, CPU->arch.cpuid3.archrev, CPU->arch.cpuid3.model, CPU->arch.cpuid3.revision);
}

/tags/0.2.0/kernel/arch/ia64/Makefile.inc
0,0 → 1,86
#
# Copyright (C) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
## Toolchain configuration
#
BFD_NAME = elf64-little
BFD_ARCH = ia64-elf64
BFD = elf64-ia64-little
TARGET = ia64-pc-linux-gnu
TOOLCHAIN_DIR = /usr/local/ia64/bin
## Make some default assumptions
#
INIT0_ADDRESS = 0xe000000000400000
INIT0_SIZE = 0x100000
CFLAGS += -mconstant-gp -fno-unwind-tables -mfixed-range=f32-f127
LFLAGS += -EL
AFLAGS += -mconstant-gp
DEFS += -D__64_BITS__ -DINIT0_ADDRESS=$(INIT0_ADDRESS) -DINIT0_SIZE=$(INIT0_SIZE)
## Compile with page hash table support.
#
CONFIG_PAGE_HT = y
DEFS += -DCONFIG_PAGE_HT
## Compile with support for address space identifiers.
#
CONFIG_ASID = y
CONFIG_ASID_FIFO = y
## Compile with support for software integer division.
#
CONFIG_SOFTINT = y
ARCH_SOURCES = \
arch/$(ARCH)/src/start.S \
arch/$(ARCH)/src/asm.S \
arch/$(ARCH)/src/dummy.s \
arch/$(ARCH)/src/ia64.c \
arch/$(ARCH)/src/fpu_context.c \
arch/$(ARCH)/src/context.S \
arch/$(ARCH)/src/ski/ski.c \
arch/$(ARCH)/src/cpu/cpu.c \
arch/$(ARCH)/src/ivt.S \
arch/$(ARCH)/src/interrupt.c \
arch/$(ARCH)/src/mm/as.c \
arch/$(ARCH)/src/mm/frame.c \
arch/$(ARCH)/src/mm/page.c \
arch/$(ARCH)/src/mm/tlb.c \
arch/$(ARCH)/src/mm/vhpt.c \
arch/$(ARCH)/src/proc/scheduler.c \
arch/$(ARCH)/src/ddi/ddi.c \
arch/$(ARCH)/src/drivers/it.c

/tags/0.2.0/kernel/arch/ia64/_link.ld.in
0,0 → 1,46
/** IA-64 linker script
*
* It is ELF format, but its only section looks like this:
* kernel text
* kernel data
*
*/
#define __ASM__
ENTRY(kernel_image_start)
SECTIONS {
.image 0xe000000000100000: AT (0x0000000000100000) {
ktext_start = .;
*(K_TEXT_START);
*(.text)
ktext_end = .;
kdata_start = .;
*(K_DATA_START)
*(.rodata .rodata.*)
*(.opd)
*(.data .data.*)
*(.got .got.*)
*(.sdata)
*(.sbss)
*(.scommon)
*(.bss)
*(COMMON);
symbol_table = .;
*(symtab.*); /* Symbol table, must be LAST symbol!*/
kdata_end = .;
}
/DISCARD/ : {
*(*);
}
_hardcoded_ktext_size = ktext_end - ktext_start;
_hardcoded_kdata_size = kdata_end - kdata_start;
_hardcoded_load_address = 0xe000000000100000;
}

/tags/0.2.0/kernel/arch/sparc64/include/interrupt.h
0,0 → 1,68
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_INTERRUPT_H__
#define __sparc64_INTERRUPT_H__
#include <typedefs.h>
#include <arch/types.h>
#define IRQ_COUNT 1 /* TODO */
#define IVT_ITEMS 15
#define IVT_FIRST 1
/* Dummy macros. */
#define IRQ_KBD 2
#define VECTOR_KBD IRQ_KBD
#define trap_virtual_enable_irqs(x)
#define trap_virtual_eoi()
struct istate {
};
static inline void istate_set_retaddr(istate_t *istate, __address retaddr)
{
/* TODO */
}
static inline int istate_from_uspace(istate_t *istate)
{
/* TODO */
return 0;
}
static inline __native istate_get_pc(istate_t *istate)
{
/* TODO */
return 0;
}
extern void interrupt_register(int n, const char *name, iroutine f);
#endif

/tags/0.2.0/kernel/arch/sparc64/include/proc/task.h
0,0 → 1,38
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_TASK_H__
#define __sparc64_TASK_H__
typedef struct {
} task_arch_t;
#define task_create_arch(t)
#define task_destroy_arch(t)
#endif

/tags/0.2.0/kernel/arch/sparc64/include/proc/thread.h
0,0 → 1,37
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_THREAD_H__
#define __sparc64_THREAD_H__
typedef struct {
} thread_arch_t;
#define thread_create_arch(t)
#endif

/tags/0.2.0/kernel/arch/sparc64/include/mm/as.h
0,0 → 1,45
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_AS_H__
#define __sparc64_AS_H__
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1
#define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000
#define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff
#define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000
#define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff
#define USTACK_ADDRESS_ARCH (0x7fffffffffffffff-(PAGE_SIZE-1))
#define as_install_arch(as)
extern void as_arch_init(void);
#endif

/tags/0.2.0/kernel/arch/sparc64/include/mm/page.h
0,0 → 1,60
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_PAGE_H__
#define __sparc64_PAGE_H__
#include <arch/mm/frame.h>
#define PAGE_WIDTH FRAME_WIDTH
#define PAGE_SIZE FRAME_SIZE
#ifdef KERNEL
#include <mm/page.h>
#include <arch/types.h>
#include <genarch/mm/page_ht.h>
#define KA2PA(x) ((__address) (x))
#define PA2KA(x) ((__address) (x))
union page_address {
__address address;
struct {
__u64 vpn : 51; /**< Virtual Page Number. */
unsigned offset : 13; /**< Offset. */
} __attribute__ ((packed));
};
typedef union page_address page_address_t;
extern void page_arch_init(void);
#endif /* KERNEL */
#endif

/tags/0.2.0/kernel/arch/sparc64/include/mm/frame.h
0,0 → 1,56
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_FRAME_H__
#define __sparc64_FRAME_H__
#define FRAME_WIDTH 13 /* 8K */
#define FRAME_SIZE (1<<FRAME_WIDTH)
#ifdef KERNEL
#ifndef __ASM__
#include <arch/types.h>
union frame_address {
__address address;
struct {
unsigned : 23;
__u64 pfn : 28; /**< Physical Frame Number. */
unsigned offset : 13; /**< Offset. */
} __attribute__ ((packed));
};
typedef union frame_address frame_address_t;
extern void frame_arch_init(void);
#endif
#endif
#endif

/tags/0.2.0/kernel/arch/sparc64/include/mm/tlb.h
0,0 → 1,413
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_TLB_H__
#define __sparc64_TLB_H__
#include <arch/mm/tte.h>
#include <arch/mm/mmu.h>
#include <arch/mm/page.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
#include <typedefs.h>
#define ITLB_ENTRY_COUNT 64
#define DTLB_ENTRY_COUNT 64
/** Page sizes. */
#define PAGESIZE_8K 0
#define PAGESIZE_64K 1
#define PAGESIZE_512K 2
#define PAGESIZE_4M 3
/** Bit width of the TLB-locked portion of kernel address space. */
#define KERNEL_PAGE_WIDTH 22 /* 4M */
union tlb_context_reg {
__u64 v;
struct {
unsigned long : 51;
unsigned context : 13; /**< Context/ASID. */
} __attribute__ ((packed));
};
typedef union tlb_context_reg tlb_context_reg_t;
/** I-/D-TLB Data In/Access Register type. */
typedef tte_data_t tlb_data_t;
/** I-/D-TLB Data Access Address in Alternate Space. */
union tlb_data_access_addr {
__u64 value;
struct {
__u64 : 55;
unsigned tlb_entry : 6;
unsigned : 3;
} __attribute__ ((packed));
};
typedef union tlb_data_access_addr tlb_data_access_addr_t;
typedef union tlb_data_access_addr tlb_tag_read_addr_t;
/** I-/D-TLB Tag Read Register. */
union tlb_tag_read_reg {
__u64 value;
struct {
__u64 vpn : 51; /**< Virtual Address bits 63:13. */
unsigned context : 13; /**< Context identifier. */
} __attribute__ ((packed));
};
typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
/** TLB Demap Operation types. */
#define TLB_DEMAP_PAGE 0
#define TLB_DEMAP_CONTEXT 1
/** TLB Demap Operation Context register encodings. */
#define TLB_DEMAP_PRIMARY 0
#define TLB_DEMAP_SECONDARY 1
#define TLB_DEMAP_NUCLEUS 2
/** TLB Demap Operation Address. */
union tlb_demap_addr {
__u64 value;
struct {
__u64 vpn: 51; /**< Virtual Address bits 63:13. */
unsigned : 6; /**< Ignored. */
unsigned type : 1; /**< The type of demap operation. */
unsigned context : 2; /**< Context register selection. */
unsigned : 4; /**< Zero. */
} __attribute__ ((packed));
};
typedef union tlb_demap_addr tlb_demap_addr_t;
/** TLB Synchronous Fault Status Register. */
union tlb_sfsr_reg {
__u64 value;
struct {
unsigned long : 39; /**< Implementation dependent. */
unsigned nf : 1; /**< Nonfaulting load. */
unsigned asi : 8; /**< ASI. */
unsigned tm : 1; /**< TLB miss. */
unsigned : 1;
unsigned ft : 7; /**< Fault type. */
unsigned e : 1; /**< Side-effect bit. */
unsigned ct : 2; /**< Context Register selection. */
unsigned pr : 1; /**< Privilege bit. */
unsigned w : 1; /**< Write bit. */
unsigned ow : 1; /**< Overwrite bit. */
unsigned fv : 1; /**< Fault Valid bit. */
} __attribute__ ((packed));
};
typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
/** Read MMU Primary Context Register.
*
* @return Current value of Primary Context Register.
*/
static inline __u64 mmu_primary_context_read(void)
{
return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
}
/** Write MMU Primary Context Register.
*
* @param v New value of Primary Context Register.
*/
static inline void mmu_primary_context_write(__u64 v)
{
asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
flush();
}
/** Read MMU Secondary Context Register.
*
* @return Current value of Secondary Context Register.
*/
static inline __u64 mmu_secondary_context_read(void)
{
return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
}
/** Write MMU Primary Context Register.
*
* @param v New value of Primary Context Register.
*/
static inline void mmu_secondary_context_write(__u64 v)
{
asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
flush();
}
/** Read IMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Data Access Register.
*/
static inline __u64 itlb_data_access_read(index_t entry)
{
tlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
/** Write IMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void itlb_data_access_write(index_t entry, __u64 value)
{
tlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
flush();
}
/** Read DMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Data Access Register.
*/
static inline __u64 dtlb_data_access_read(index_t entry)
{
tlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
/** Write DMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void dtlb_data_access_write(index_t entry, __u64 value)
{
tlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
flush();
}
/** Read IMMU TLB Tag Read Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Tag Read Register.
*/
static inline __u64 itlb_tag_read_read(index_t entry)
{
tlb_tag_read_addr_t tag;
tag.value = 0;
tag.tlb_entry = entry;
return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
/** Read DMMU TLB Tag Read Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Tag Read Register.
*/
static inline __u64 dtlb_tag_read_read(index_t entry)
{
tlb_tag_read_addr_t tag;
tag.value = 0;
tag.tlb_entry = entry;
return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
/** Write IMMU TLB Tag Access Register.
*
* @param v Value to be written.
*/
static inline void itlb_tag_access_write(__u64 v)
{
asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
flush();
}
/** Read IMMU TLB Tag Access Register.
*
* @return Current value of IMMU TLB Tag Access Register.
*/
static inline __u64 itlb_tag_access_read(void)
{
return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
}
/** Write DMMU TLB Tag Access Register.
*
* @param v Value to be written.
*/
static inline void dtlb_tag_access_write(__u64 v)
{
asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
flush();
}
/** Read DMMU TLB Tag Access Register.
*
* @return Current value of DMMU TLB Tag Access Register.
*/
static inline __u64 dtlb_tag_access_read(void)
{
return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
}
/** Write IMMU TLB Data in Register.
*
* @param v Value to be written.
*/
static inline void itlb_data_in_write(__u64 v)
{
asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
flush();
}
/** Write DMMU TLB Data in Register.
*
* @param v Value to be written.
*/
static inline void dtlb_data_in_write(__u64 v)
{
asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
flush();
}
/** Read ITLB Synchronous Fault Status Register.
*
* @return Current content of I-SFSR register.
*/
static inline __u64 itlb_sfsr_read(void)
{
return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
}
/** Write ITLB Synchronous Fault Status Register.
*
* @param v New value of I-SFSR register.
*/
static inline void itlb_sfsr_write(__u64 v)
{
asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
flush();
}
/** Read DTLB Synchronous Fault Status Register.
*
* @return Current content of D-SFSR register.
*/
static inline __u64 dtlb_sfsr_read(void)
{
return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
}
/** Write DTLB Synchronous Fault Status Register.
*
* @param v New value of D-SFSR register.
*/
static inline void dtlb_sfsr_write(__u64 v)
{
asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
flush();
}
/** Read DTLB Synchronous Fault Address Register.
*
* @return Current content of D-SFAR register.
*/
static inline __u64 dtlb_sfar_read(void)
{
return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
}
/** Perform IMMU TLB Demap Operation.
*
* @param type Selects between context and page demap.
* @param context_encoding Specifies which Context register has Context ID for demap.
* @param page Address which is on the page to be demapped.
*/
static inline void itlb_demap(int type, int context_encoding, __address page)
{
tlb_demap_addr_t da;
page_address_t pg;
da.value = 0;
pg.address = page;
da.type = type;
da.context = context_encoding;
da.vpn = pg.vpn;
asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
flush();
}
/** Perform DMMU TLB Demap Operation.
*
* @param type Selects between context and page demap.
* @param context_encoding Specifies which Context register has Context ID for demap.
* @param page Address which is on the page to be demapped.
*/
static inline void dtlb_demap(int type, int context_encoding, __address page)
{
tlb_demap_addr_t da;
page_address_t pg;
da.value = 0;
pg.address = page;
da.type = type;
da.context = context_encoding;
da.vpn = pg.vpn;
asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
flush();
}
extern void fast_instruction_access_mmu_miss(void);
extern void fast_data_access_mmu_miss(void);
extern void fast_data_access_protection(void);
extern void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable);
#endif

/tags/0.2.0/kernel/arch/sparc64/include/mm/memory_init.h
0,0 → 1,36
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_MEMORY_INIT_H__
#define __sparc64_MEMORY_INIT_H__
#include <typedefs.h>
extern size_t get_memory_size(void);
#endif

/tags/0.2.0/kernel/arch/sparc64/include/mm/mmu.h
0,0 → 1,127
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_MMU_H__
#define __sparc64_MMU_H__
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
#include <typedefs.h>
/** LSU Control Register ASI. */
#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */
/** I-MMU ASIs. */
#define ASI_IMMU 0x50
#define ASI_IMMU_TSB_8KB_PTR_REG 0x51
#define ASI_IMMU_TSB_64KB_PTR_REG 0x52
#define ASI_ITLB_DATA_IN_REG 0x54
#define ASI_ITLB_DATA_ACCESS_REG 0x55
#define ASI_ITLB_TAG_READ_REG 0x56
#define ASI_IMMU_DEMAP 0x57
/** Virtual Addresses within ASI_IMMU. */
#define VA_IMMU_TAG_TARGET 0x0 /**< IMMU tag target register. */
#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */
#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */
#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */
/** D-MMU ASIs. */
#define ASI_DMMU 0x58
#define ASI_DMMU_TSB_8KB_PTR_REG 0x59
#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a
#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
#define ASI_DTLB_DATA_IN_REG 0x5c
#define ASI_DTLB_DATA_ACCESS_REG 0x5d
#define ASI_DTLB_TAG_READ_REG 0x5e
#define ASI_DMMU_DEMAP 0x5f
/** Virtual Addresses within ASI_DMMU. */
#define VA_DMMU_TAG_TARGET 0x0 /**< DMMU tag target register. */
#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */
#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */
#define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */
#define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */
#define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */
#define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */
#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */
#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */
/** LSU Control Register. */
union lsu_cr_reg {
__u64 value;
struct {
unsigned : 23;
unsigned pm : 8;
unsigned vm : 8;
unsigned pr : 1;
unsigned pw : 1;
unsigned vr : 1;
unsigned vw : 1;
unsigned : 1;
unsigned fm : 16;
unsigned dm : 1; /**< D-MMU enable. */
unsigned im : 1; /**< I-MMU enable. */
unsigned dc : 1; /**< D-Cache enable. */
unsigned ic : 1; /**< I-Cache enable. */
} __attribute__ ((packed));
};
typedef union lsu_cr_reg lsu_cr_reg_t;
#define immu_enable() immu_set(true)
#define immu_disable() immu_set(false)
#define dmmu_enable() dmmu_set(true)
#define dmmu_disable() dmmu_set(false)
/** Disable or Enable IMMU. */
static inline void immu_set(bool enable)
{
lsu_cr_reg_t cr;
cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
cr.im = enable;
asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
membar();
}
/** Disable or Enable DMMU. */
static inline void dmmu_set(bool enable)
{
lsu_cr_reg_t cr;
cr.value = asi_u64_read(ASI_LSU_CONTROL_REG, 0);
cr.dm = enable;
asi_u64_write(ASI_LSU_CONTROL_REG, 0, cr.value);
membar();
}
#endif

/tags/0.2.0/kernel/arch/sparc64/include/mm/asid.h
0,0 → 1,41
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_ASID_H__
#define __sparc64_ASID_H__
#include <arch/types.h>
/*
* On SPARC, Context means the same thing as ASID trough out the kernel.
*/
typedef __u16 asid_t;
#define ASID_MAX_ARCH 8191 /* 2^13 - 1 */
#endif

/tags/0.2.0/kernel/arch/sparc64/include/mm/tte.h
0,0 → 1,72
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_TTE_H__
#define __sparc64_TTE_H__
#include <arch/types.h>
/** Translation Table Entry - Tag. */
union tte_tag {
__u64 value;
struct {
unsigned g : 1; /**< Global. */
unsigned : 2; /**< Reserved. */
unsigned context : 13; /**< Context identifier. */
unsigned : 6; /**< Reserved. */
__u64 va_tag : 42; /**< Virtual Address Tag, bits 63:22. */
} __attribute__ ((packed));
};
typedef union tte_tag tte_tag_t;
/** Translation Table Entry - Data. */
union tte_data {
__u64 value;
struct {
unsigned v : 1; /**< Valid. */
unsigned size : 2; /**< Page size of this entry. */
unsigned nfo : 1; /**< No-Fault-Only. */
unsigned ie : 1; /**< Invert Endianness. */
unsigned soft2 : 9; /**< Software defined field. */
unsigned diag : 9; /**< Diagnostic data. */
unsigned pfn : 28; /**< Physical Address bits, bits 40:13. */
unsigned soft : 6; /**< Software defined field. */
unsigned l : 1; /**< Lock. */
unsigned cp : 1; /**< Cacheable in physically indexed cache. */
unsigned cv : 1; /**< Cacheable in virtually indexed cache. */
unsigned e : 1; /**< Side-effect. */
unsigned p : 1; /**< Privileged. */
unsigned w : 1; /**< Writable. */
unsigned g : 1; /**< Global. */
} __attribute__ ((packed));
};
typedef union tte_data tte_data_t;
#endif

/tags/0.2.0/kernel/arch/sparc64/include/drivers/i8042.h
0,0 → 1,66
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_I8042_H__
#define __sparc64_I8042_H__
#include <arch/types.h>
#define KBD_PHYS_ADDRESS 0x1fff8904000ULL
#define STATUS_REG 4
#define COMMAND_REG 4
#define DATA_REG 6
#define LAST_REG DATA_REG
extern volatile __u8 *kbd_virt_address;
static inline void i8042_data_write(__u8 data)
{
kbd_virt_address[DATA_REG] = data;
}
static inline __u8 i8042_data_read(void)
{
return kbd_virt_address[DATA_REG];
}
static inline __u8 i8042_status_read(void)
{
return kbd_virt_address[STATUS_REG];
}
static inline void i8042_command_write(__u8 command)
{
kbd_virt_address[COMMAND_REG] = command;
}
extern void kbd_init(void);
#endif

/tags/0.2.0/kernel/arch/sparc64/include/drivers/fb.h
0,0 → 1,39
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_FB_H__
#define __sparc64_FB_H__
#define FB_PHYS_ADDRESS 0x1c901000000ULL
#define FB_X_RES 1152
#define FB_Y_RES 900
#define FB_COLOR_DEPTH 8
#endif

/tags/0.2.0/kernel/arch/sparc64/include/drivers/tick.h
0,0 → 1,39
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_TICK_H__
#define __sparc64_TICK_H__
#include <typedefs.h>
#define TICK_DELTA 500000
extern void tick_init(void);
extern void tick_interrupt(int n, istate_t *istate);
#endif

/tags/0.2.0/kernel/arch/sparc64/include/atomic.h
0,0 → 1,94
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_ATOMIC_H__
#define __sparc64_ATOMIC_H__
#include <arch/types.h>
#include <typedefs.h>
/** Atomic add operation.
*
* Use atomic compare and swap operation to atomically add signed value.
*
* @param val Atomic variable.
* @param i Signed value to be added.
*
* @return Value of the atomic variable as it existed before addition.
*/
static inline long atomic_add(atomic_t *val, int i)
{
__u64 a, b;
volatile __u64 x = (__u64) &val->count;
__asm__ volatile (
"0:\n"
"ldx %0, %1\n"
"add %1, %3, %2\n"
"casx %0, %1, %2\n"
"cmp %1, %2\n"
"bne 0b\n" /* The operation failed and must be attempted again if a != b. */
"nop\n"
: "=m" (*((__u64 *)x)), "=r" (a), "=r" (b)
: "r" (i)
);
return a;
}
static inline long atomic_preinc(atomic_t *val)
{
return atomic_add(val, 1) + 1;
}
static inline long atomic_postinc(atomic_t *val)
{
return atomic_add(val, 1);
}
static inline long atomic_predec(atomic_t *val)
{
return atomic_add(val, -1) - 1;
}
static inline long atomic_postdec(atomic_t *val)
{
return atomic_add(val, -1);
}
static inline void atomic_inc(atomic_t *val)
{
(void) atomic_add(val, 1);
}
static inline void atomic_dec(atomic_t *val)
{
(void) atomic_add(val, -1);
}
#endif

/tags/0.2.0/kernel/arch/sparc64/include/types.h
0,0 → 1,56
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_TYPES_H__
#define __sparc64_TYPES_H__
#define NULL 0
typedef signed char __s8;
typedef signed short __s16;
typedef signed int __s32;
typedef signed long __s64;
typedef unsigned char __u8;
typedef unsigned short __u16;
typedef unsigned int __u32;
typedef unsigned long __u64;
typedef __u64 __address;
typedef __u64 pfn_t;
typedef __u64 ipl_t;
typedef __u64 __native;
typedef __s64 __snative;
typedef struct pte pte_t;
typedef __u8 asi_t;
#endif

/tags/0.2.0/kernel/arch/sparc64/include/elf.h
0,0 → 1,36
/*
* Copyright (C) 2006 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_ELF_H__
#define __sparc64_ELF_H__
#define ELF_MACHINE EM_SPARCV9
#define ELF_DATA_ENCODING ELFDATA2MSB
#define ELF_CLASS ELFCLASS64
#endif

/tags/0.2.0/kernel/arch/sparc64/include/trap/exception.h
0,0 → 1,44
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_EXCEPTION_H__
#define __sparc64_EXCEPTION_H__
#define TT_INSTRUCTION_ACCESS_EXCEPTION 0x08
#define TT_ILLEGAL_INSTRUCTION 0x10
#define TT_DATA_ACCESS_ERROR 0x32
#define TT_MEM_ADDRESS_NOT_ALIGNED 0x34
#ifndef __ASM__
extern void do_instruction_access_exc(void);
extern void do_mem_address_not_aligned(void);
extern void do_data_access_error(void);
extern void do_illegal_instruction(void);
#endif /* !__ASM__ */
#endif

/tags/0.2.0/kernel/arch/sparc64/include/trap/mmu.h
0,0 → 1,70
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* This file contains fast MMU trap handlers.
*/
#ifndef __sparc64_MMU_TRAP_H__
#define __sparc64_MMU_TRAP_H__
#include <arch/stack.h>
#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68
#define TT_FAST_DATA_ACCESS_PROTECTION 0x6c
#define FAST_MMU_HANDLER_SIZE 128
#ifdef __ASM__
.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
call fast_instruction_access_mmu_miss
nop
restore
retry
.endm
.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER
save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
call fast_data_access_mmu_miss
nop
restore
retry
.endm
.macro FAST_DATA_ACCESS_PROTECTION_HANDLER
save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
call fast_data_access_protection
nop
restore
retry
.endm
#endif /* __ASM__ */
#endif

/tags/0.2.0/kernel/arch/sparc64/include/trap/trap.h
0,0 → 1,44
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_TRAP_H__
#define __sparc64_TRAP_H__
#include <arch/trap/trap_table.h>
#include <arch/asm.h>
/** Switch to in-kernel trap table. */
static inline void trap_switch_trap_table(void)
{
/* Point TBA to kernel copy of OFW's trap table. */
tba_write((__u64) trap_table);
}
extern void trap_init(void);
#endif

/tags/0.2.0/kernel/arch/sparc64/include/trap/interrupt.h
0,0 → 1,73
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* This file contains interrupt vector trap handler.
*/
#ifndef __sparc64_TRAP_INTERRUPT_H__
#define __sparc64_TRAP_INTERRUPT_H__
#include <arch/trap/trap_table.h>
#include <arch/stack.h>
#define TT_INTERRUPT_LEVEL_1 0x41
#define TT_INTERRUPT_LEVEL_2 0x42
#define TT_INTERRUPT_LEVEL_3 0x43
#define TT_INTERRUPT_LEVEL_4 0x44
#define TT_INTERRUPT_LEVEL_5 0x45
#define TT_INTERRUPT_LEVEL_6 0x46
#define TT_INTERRUPT_LEVEL_7 0x47
#define TT_INTERRUPT_LEVEL_8 0x48
#define TT_INTERRUPT_LEVEL_9 0x49
#define TT_INTERRUPT_LEVEL_10 0x4a
#define TT_INTERRUPT_LEVEL_11 0x4b
#define TT_INTERRUPT_LEVEL_12 0x4c
#define TT_INTERRUPT_LEVEL_13 0x4d
#define TT_INTERRUPT_LEVEL_14 0x4e
#define TT_INTERRUPT_LEVEL_15 0x4f
#define TT_INTERRUPT_VECTOR_TRAP 0x60
#define INTERRUPT_LEVEL_N_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE
#define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE
#ifdef __ASM__
.macro INTERRUPT_LEVEL_N_HANDLER n
save %sp, -PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE, %sp
mov \n - 1, %o0
mov %fp, %o1
PREEMPTIBLE_HANDLER exc_dispatch
.endm
.macro INTERRUPT_VECTOR_TRAP_HANDLER
retry
.endm
#endif /* __ASM__ */
#endif

/tags/0.2.0/kernel/arch/sparc64/include/trap/trap_table.h
0,0 → 1,92
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_TRAP_TABLE_H__
#define __sparc64_TRAP_TABLE_H__
#ifndef __ASM__
#include <arch/types.h>
#endif /* __ASM__ */
#include <arch/stack.h>
#define TRAP_TABLE_ENTRY_COUNT 1024
#define TRAP_TABLE_ENTRY_SIZE 32
#define TRAP_TABLE_SIZE (TRAP_TABLE_ENTRY_COUNT*TRAP_TABLE_ENTRY_SIZE)
#ifndef __ASM__
struct trap_table_entry {
__u8 octets[TRAP_TABLE_ENTRY_SIZE];
} __attribute__ ((packed));
typedef struct trap_table_entry trap_table_entry_t;
extern trap_table_entry_t trap_table[TRAP_TABLE_ENTRY_COUNT];
extern trap_table_entry_t trap_table_save[TRAP_TABLE_ENTRY_COUNT];
#endif /* !__ASM__ */
#ifdef __ASM__
.macro SAVE_GLOBALS
mov %g1, %l1
mov %g2, %l2
mov %g3, %l3
mov %g4, %l4
mov %g5, %l5
mov %g6, %l6
mov %g7, %l7
.endm
.macro RESTORE_GLOBALS
mov %l1, %g1
mov %l2, %g2
mov %l3, %g3
mov %l4, %g4
mov %l5, %g5
mov %l6, %g6
mov %l7, %g7
.endm
#define PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE (STACK_WINDOW_SAVE_AREA_SIZE+(4*8))
#define SAVED_TSTATE -(1*8)
#define SAVED_TPC -(2*8)
#define SAVED_TNPC -(3*8)
#define SAVED_PSTATE -(4*8)
.macro PREEMPTIBLE_HANDLER f
set \f, %l0
b preemptible_handler
nop
.endm
.macro SIMPLE_HANDLER f
call \f
nop
.endm
#endif /* __ASM__ */
#endif

/tags/0.2.0/kernel/arch/sparc64/include/trap/regwin.h
0,0 → 1,133
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* This file contains register window trap handlers.
*/
#ifndef __sparc64_REGWIN_H__
#define __sparc64_REGWIN_H__
#include <arch/stack.h>
#define TT_CLEAN_WINDOW 0x24
#define TT_SPILL_0_NORMAL 0x80
#define TT_FILL_0_NORMAL 0xc0
#define REGWIN_HANDLER_SIZE 128
#define CLEAN_WINDOW_HANDLER_SIZE REGWIN_HANDLER_SIZE
#define SPILL_HANDLER_SIZE REGWIN_HANDLER_SIZE
#define FILL_HANDLER_SIZE REGWIN_HANDLER_SIZE
/** Window Save Area offsets. */
#define L0_OFFSET 0
#define L1_OFFSET 8
#define L2_OFFSET 16
#define L3_OFFSET 24
#define L4_OFFSET 32
#define L5_OFFSET 40
#define L6_OFFSET 48
#define L7_OFFSET 56
#define I0_OFFSET 64
#define I1_OFFSET 72
#define I2_OFFSET 80
#define I3_OFFSET 88
#define I4_OFFSET 96
#define I5_OFFSET 104
#define I6_OFFSET 112
#define I7_OFFSET 120
#ifdef __ASM__
.macro SPILL_NORMAL_HANDLER
stx %l0, [%sp + STACK_BIAS + L0_OFFSET]
stx %l1, [%sp + STACK_BIAS + L1_OFFSET]
stx %l2, [%sp + STACK_BIAS + L2_OFFSET]
stx %l3, [%sp + STACK_BIAS + L3_OFFSET]
stx %l4, [%sp + STACK_BIAS + L4_OFFSET]
stx %l5, [%sp + STACK_BIAS + L5_OFFSET]
stx %l6, [%sp + STACK_BIAS + L6_OFFSET]
stx %l7, [%sp + STACK_BIAS + L7_OFFSET]
stx %i0, [%sp + STACK_BIAS + I0_OFFSET]
stx %i1, [%sp + STACK_BIAS + I1_OFFSET]
stx %i2, [%sp + STACK_BIAS + I2_OFFSET]
stx %i3, [%sp + STACK_BIAS + I3_OFFSET]
stx %i4, [%sp + STACK_BIAS + I4_OFFSET]
stx %i5, [%sp + STACK_BIAS + I5_OFFSET]
stx %i6, [%sp + STACK_BIAS + I6_OFFSET]
stx %i7, [%sp + STACK_BIAS + I7_OFFSET]
saved
retry
.endm
.macro FILL_NORMAL_HANDLER
ldx [%sp + STACK_BIAS + L0_OFFSET], %l0
ldx [%sp + STACK_BIAS + L1_OFFSET], %l1
ldx [%sp + STACK_BIAS + L2_OFFSET], %l2
ldx [%sp + STACK_BIAS + L3_OFFSET], %l3
ldx [%sp + STACK_BIAS + L4_OFFSET], %l4
ldx [%sp + STACK_BIAS + L5_OFFSET], %l5
ldx [%sp + STACK_BIAS + L6_OFFSET], %l6
ldx [%sp + STACK_BIAS + L7_OFFSET], %l7
ldx [%sp + STACK_BIAS + I0_OFFSET], %i0
ldx [%sp + STACK_BIAS + I1_OFFSET], %i1
ldx [%sp + STACK_BIAS + I2_OFFSET], %i2
ldx [%sp + STACK_BIAS + I3_OFFSET], %i3
ldx [%sp + STACK_BIAS + I4_OFFSET], %i4
ldx [%sp + STACK_BIAS + I5_OFFSET], %i5
ldx [%sp + STACK_BIAS + I6_OFFSET], %i6
ldx [%sp + STACK_BIAS + I7_OFFSET], %i7
restored
retry
.endm
.macro CLEAN_WINDOW_HANDLER
rdpr %cleanwin, %l0
add %l0, 1, %l0
wrpr %l0, 0, %cleanwin
mov %r0, %l0
mov %r0, %l1
mov %r0, %l2
mov %r0, %l3
mov %r0, %l4
mov %r0, %l5
mov %r0, %l6
mov %r0, %l7
mov %r0, %o0
mov %r0, %o1
mov %r0, %o2
mov %r0, %o3
mov %r0, %o4
mov %r0, %o5
mov %r0, %o6
mov %r0, %o7
retry
.endm
#endif /* __ASM__ */
#endif

/tags/0.2.0/kernel/arch/sparc64/include/console.h
0,0 → 1,37
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_CONSOLE_H__
#define __sparc64_CONSOLE_H__
extern void kofwinput(void *arg);
extern void kkbdpoll(void *arg);
extern void ofw_sparc64_console_init(void);
extern void standalone_sparc64_console_init(void);
#endif

/tags/0.2.0/kernel/arch/sparc64/include/asm.h
0,0 → 1,307
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_ASM_H__
#define __sparc64_ASM_H__
#include <typedefs.h>
#include <arch/types.h>
#include <arch/register.h>
#include <config.h>
/** Read Processor State register.
*
* @return Value of PSTATE register.
*/
static inline __u64 pstate_read(void)
{
__u64 v;
__asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
return v;
}
/** Write Processor State register.
*
* @param New value of PSTATE register.
*/
static inline void pstate_write(__u64 v)
{
__asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
}
/** Read TICK_compare Register.
*
* @return Value of TICK_comapre register.
*/
static inline __u64 tick_compare_read(void)
{
__u64 v;
__asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
return v;
}
/** Write TICK_compare Register.
*
* @param New value of TICK_comapre register.
*/
static inline void tick_compare_write(__u64 v)
{
__asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
}
/** Read TICK Register.
*
* @return Value of TICK register.
*/
static inline __u64 tick_read(void)
{
__u64 v;
__asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
return v;
}
/** Write TICK Register.
*
* @param New value of TICK register.
*/
static inline void tick_write(__u64 v)
{
__asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
}
/** Read SOFTINT Register.
*
* @return Value of SOFTINT register.
*/
static inline __u64 softint_read(void)
{
__u64 v;
__asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
return v;
}
/** Write SOFTINT Register.
*
* @param New value of SOFTINT register.
*/
static inline void softint_write(__u64 v)
{
__asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
}
/** Write CLEAR_SOFTINT Register.
*
* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
*
* @param New value of CLEAR_SOFTINT register.
*/
static inline void clear_softint_write(__u64 v)
{
__asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
}
/** Enable interrupts.
*
* Enable interrupts and return previous
* value of IPL.
*
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_enable(void) {
pstate_reg_t pstate;
__u64 value;
value = pstate_read();
pstate.value = value;
pstate.ie = true;
pstate_write(pstate.value);
return (ipl_t) value;
}
/** Disable interrupts.
*
* Disable interrupts and return previous
* value of IPL.
*
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_disable(void) {
pstate_reg_t pstate;
__u64 value;
value = pstate_read();
pstate.value = value;
pstate.ie = false;
pstate_write(pstate.value);
return (ipl_t) value;
}
/** Restore interrupt priority level.
*
* Restore IPL.
*
* @param ipl Saved interrupt priority level.
*/
static inline void interrupts_restore(ipl_t ipl) {
pstate_reg_t pstate;
pstate.value = pstate_read();
pstate.ie = ((pstate_reg_t) ipl).ie;
pstate_write(pstate.value);
}
/** Return interrupt priority level.
*
* Return IPL.
*
* @return Current interrupt priority level.
*/
static inline ipl_t interrupts_read(void) {
return (ipl_t) pstate_read();
}
/** Return base address of current stack.
*
* Return the base address of the current stack.
* The stack is assumed to be STACK_SIZE bytes long.
* The stack must start on page boundary.
*/
static inline __address get_stack_base(void)
{
__address v;
__asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
return v;
}
/** Read Version Register.
*
* @return Value of VER register.
*/
static inline __u64 ver_read(void)
{
__u64 v;
__asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
return v;
}
/** Read Trap Base Address register.
*
* @return Current value in TBA.
*/
static inline __u64 tba_read(void)
{
__u64 v;
__asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
return v;
}
/** Read Trap Program Counter register.
*
* @return Current value in TPC.
*/
static inline __u64 tpc_read(void)
{
__u64 v;
__asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));
return v;
}
/** Read Trap Level register.
*
* @return Current value in TL.
*/
static inline __u64 tl_read(void)
{
__u64 v;
__asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));
return v;
}
/** Write Trap Base Address register.
*
* @param New value of TBA.
*/
static inline void tba_write(__u64 v)
{
__asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
}
/** Load __u64 from alternate space.
*
* @param asi ASI determining the alternate space.
* @param va Virtual address within the ASI.
*
* @return Value read from the virtual address in the specified address space.
*/
static inline __u64 asi_u64_read(asi_t asi, __address va)
{
__u64 v;
__asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
return v;
}
/** Store __u64 to alternate space.
*
* @param asi ASI determining the alternate space.
* @param va Virtual address within the ASI.
* @param v Value to be written.
*/
static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
{
__asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory");
}
void cpu_halt(void);
void cpu_sleep(void);
void asm_delay_loop(__u32 t);
#endif

/tags/0.2.0/kernel/arch/sparc64/include/barrier.h
0,0 → 1,64
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_BARRIER_H__
#define __sparc64_BARRIER_H__
/*
* TODO: Implement true SPARC V9 memory barriers for macros below.
*/
#define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory")
#define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory")
#define memory_barrier()
#define read_barrier()
#define write_barrier()
/** Flush Instruction Memory instruction. */
static inline void flush(void)
{
/*
* The FLUSH instruction takes address parameter.
* As such, it may trap if the address is not found in DTLB.
* However, JPS1 implementations are free to ignore the trap.
*/
/*
* %i7 should provide address that is always mapped in DTLB
* as it is a pointer to kernel code.
*/
__asm__ volatile ("flush %i7\n");
}
/** Memory Barrier instruction. */
static inline void membar(void)
{
__asm__ volatile ("membar #Sync\n");
}
#endif

/tags/0.2.0/kernel/arch/sparc64/include/context_offset.h
0,0 → 1,21
/* This file is automatically generated by gencontext.c. */
/* struct context */
#define OFFSET_SP 0x0
#define OFFSET_PC 0x8
#define OFFSET_I0 0x10
#define OFFSET_I1 0x18
#define OFFSET_I2 0x20
#define OFFSET_I3 0x28
#define OFFSET_I4 0x30
#define OFFSET_I5 0x38
#define OFFSET_FP 0x40
#define OFFSET_I7 0x48
#define OFFSET_L0 0x50
#define OFFSET_L1 0x58
#define OFFSET_L2 0x60
#define OFFSET_L3 0x68
#define OFFSET_L4 0x70
#define OFFSET_L5 0x78
#define OFFSET_L6 0x80
#define OFFSET_L7 0x88
#define OFFSET_CLEANWIN 0x98

/tags/0.2.0/kernel/arch/sparc64/include/boot/boot.h
0,0 → 1,35
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_BOOT_H__
#define __sparc64_BOOT_H__
#define VMA 0x400000
#define LMA 0x4000
#endif

/tags/0.2.0/kernel/arch/sparc64/include/context.h
0,0 → 1,84
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_CONTEXT_H__
#define __sparc64_CONTEXT_H__
#ifndef __sparc64_STACK_H__
# include <arch/stack.h>
#endif
#ifndef __sparc64_TYPES_H__
# include <arch/types.h>
#endif
#ifndef __ALIGN_H__
# include <align.h>
#endif
#define SP_DELTA STACK_WINDOW_SAVE_AREA_SIZE
#ifdef context_set
#undef context_set
#endif
#define context_set(c, _pc, stack, size) \
(c)->pc = ((__address) _pc) - 8; \
(c)->sp = ((__address) stack) + ALIGN_UP((size), STACK_ALIGNMENT) - (STACK_BIAS + SP_DELTA); \
(c)->fp = -STACK_BIAS; \
(c)->cleanwin = 0
/*
* Only save registers that must be preserved across
* function calls.
*/
struct context {
__address sp; /* %o6 */
__address pc; /* %o7 */
__u64 i0;
__u64 i1;
__u64 i2;
__u64 i3;
__u64 i4;
__u64 i5;
__address fp; /* %i6 */
__address i7;
__u64 l0;
__u64 l1;
__u64 l2;
__u64 l3;
__u64 l4;
__u64 l5;
__u64 l6;
__u64 l7;
ipl_t ipl;
__u64 cleanwin;
};
#endif

/tags/0.2.0/kernel/arch/sparc64/include/register.h
0,0 → 1,101
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_REGISTER_H__
#define __sparc64_REGISTER_H__
#include <arch/types.h>
/** Version Register. */
union ver_reg {
__u64 value;
struct {
__u16 manuf; /**< Manufacturer code. */
__u16 impl; /**< Implementation code. */
__u8 mask; /**< Mask set revision. */
unsigned : 8;
__u8 maxtl;
unsigned : 3;
unsigned maxwin : 5;
} __attribute__ ((packed));
};
typedef union ver_reg ver_reg_t;
/** Processor State Register. */
union pstate_reg {
__u64 value;
struct {
__u64 : 52;
unsigned ig : 1; /**< Interrupt Globals. */
unsigned mg : 1; /**< MMU Globals. */
unsigned cle : 1; /**< Current Little Endian. */
unsigned tle : 1; /**< Trap Little Endian. */
unsigned mm : 2; /**< Memory Model. */
unsigned red : 1; /**< RED state. */
unsigned pef : 1; /**< Enable floating-point. */
unsigned am : 1; /**< 32-bit Address Mask. */
unsigned priv : 1; /**< Privileged Mode. */
unsigned ie : 1; /**< Interrupt Enable. */
unsigned ag : 1; /**< Alternate Globals*/
} __attribute__ ((packed));
};
typedef union pstate_reg pstate_reg_t;
/** TICK Register. */
union tick_reg {
__u64 value;
struct {
unsigned npt : 1; /**< Non-privileged Trap enable. */
__u64 counter : 63; /**< Elapsed CPU clck cycle counter. */
} __attribute__ ((packed));
};
typedef union tick_reg tick_reg_t;
/** TICK_compare Register. */
union tick_compare_reg {
__u64 value;
struct {
unsigned int_dis : 1; /**< TICK_INT interrupt disabled flag. */
__u64 tick_cmpr : 63; /**< Compare value for TICK interrupts. */
} __attribute__ ((packed));
};
typedef union tick_compare_reg tick_compare_reg_t;
/** SOFTINT Register. */
union softint_reg {
__u64 value;
struct {
__u64 : 47;
unsigned stick_int : 1;
unsigned int_level : 15;
unsigned tick_int : 1;
} __attribute__ ((packed));
};
typedef union softint_reg softint_reg_t;
#endif

/tags/0.2.0/kernel/arch/sparc64/include/cpu.h
0,0 → 1,51
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_CPU_H__
#define __sparc64_CPU_H__
#include <arch/register.h>
#define MANUF_FUJITSU 0x04
#define MANUF_ULTRASPARC 0x17 /**< UltraSPARC I, UltraSPARC II */
#define MANUF_SUN 0x3e
#define IMPL_ULTRASPARCI 0x10
#define IMPL_ULTRASPARCII 0x11
#define IMPL_ULTRASPARCII_I 0x12
#define IMPL_ULTRASPARCII_E 0x13
#define IMPL_ULTRASPARCIII 0x15
#define IMPL_ULTRASPARCIV_PLUS 0x19
#define IMPL_SPARC64V 0x5
struct cpu_arch {
ver_reg_t ver;
};
#endif

/tags/0.2.0/kernel/arch/sparc64/include/memstr.h
0,0 → 1,39
/*
* Copyright (C) 2005 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_MEMSTR_H__
#define __sparc64_MEMSTR_H__
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt))
extern void memsetw(__address dst, size_t cnt, __u16 x);
extern void memsetb(__address dst, size_t cnt, __u8 x);
extern int memcmp(__address src, __address dst, int cnt);
#endif

/tags/0.2.0/kernel/arch/sparc64/include/debug.h
0,0 → 1,32
/*
* Copyright (C) 2005
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_DEBUG_H__
#define __sparc64_DEBUG_H__
#endif

/tags/0.2.0/kernel/arch/sparc64/include/stack.h
0,0 → 1,47
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_STACK_H__
#define __sparc64_STACK_H__
#define STACK_ITEM_SIZE 8
/** According to SPARC Compliance Definition, every stack frame is 16-byte aligned. */
#define STACK_ALIGNMENT 16
/**
* 16-extended-word save area for %i[0-7] and %l[0-7] registers.
*/
#define STACK_WINDOW_SAVE_AREA_SIZE (16*STACK_ITEM_SIZE)
/**
* By convention, the actual top of the stack is %sp + STACK_BIAS.
*/
#define STACK_BIAS 2047
#endif

/tags/0.2.0/kernel/arch/sparc64/include/arg.h
0,0 → 1,34
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_ARG_H__
#define __sparc64_ARG_H__
#include <stdarg.h>
#endif

/tags/0.2.0/kernel/arch/sparc64/include/fpu_context.h
0,0 → 1,37
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_FPU_CONTEXT_H__
#define __sparc64_FPU_CONTEXT_H__
#include <arch/types.h>
struct fpu_context {
};
#endif

/tags/0.2.0/kernel/arch/sparc64/include/byteorder.h
0,0 → 1,45
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_BYTEORDER_H__
#define __sparc64_BYTEORDER_H__
#include <arch/types.h>
#include <byteorder.h>
static inline __u64 __u64_le2host(__u64 n)
{
return __u64_byteorder_swap(n);
}
static inline __native __native_le2host(__native n)
{
return __u64_byteorder_swap(n);
}
#endif

/tags/0.2.0/kernel/arch/sparc64/include/arch.h
0,0 → 1,32
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_ARCH_H__
#define __sparc64_ARCH_H__
#endif

/tags/0.2.0/kernel/arch/sparc64/include/faddr.h
0,0 → 1,36
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __sparc64_FADDR_H__
#define __sparc64_FADDR_H__
#include <arch/types.h>
#define FADDR(fptr) ((__address) (fptr))
#endif

/tags/0.2.0/kernel/arch/sparc64/src/sparc64.c
0,0 → 1,90
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <debug.h>
#include <arch/trap/trap.h>
#include <arch/console.h>
#include <arch/drivers/tick.h>
#include <proc/thread.h>
#include <console/console.h>
void arch_pre_mm_init(void)
{
interrupts_disable();
ofw_sparc64_console_init();
trap_init();
tick_init();
}
void arch_post_mm_init(void)
{
standalone_sparc64_console_init();
}
void arch_pre_smp_init(void)
{
}
void arch_post_smp_init(void)
{
thread_t *t;
/*
* Create thread that reads characters from OFW's input.
*/
t = thread_create(kofwinput, NULL, TASK, 0, "kofwinput");
if (!t)
panic("cannot create kofwinput\n");
thread_ready(t);
/*
* Create thread that polls keyboard.
*/
t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll");
if (!t)
panic("cannot create kkbdpoll\n");
thread_ready(t);
}
void calibrate_delay_loop(void)
{
}
/** Acquire console back for kernel
*
*/
void arch_grab_console(void)
{
}
/** Return console to userspace
*
*/
void arch_release_console(void)
{
}

/tags/0.2.0/kernel/arch/sparc64/src/console.c
0,0 → 1,178
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/console.h>
#include <arch/types.h>
#include <typedefs.h>
#include <genarch/fb/fb.h>
#include <arch/drivers/fb.h>
#include <arch/drivers/i8042.h>
#include <genarch/i8042/i8042.h>
#include <genarch/ofw/ofw.h>
#include <console/chardev.h>
#include <console/console.h>
#include <arch/asm.h>
#include <arch/register.h>
#include <proc/thread.h>
#include <synch/mutex.h>
#include <arch/mm/tlb.h>
#define KEYBOARD_POLL_PAUSE 50000 /* 50ms */
static void ofw_sparc64_putchar(chardev_t *d, const char ch);
static char ofw_sparc64_getchar(chardev_t *d);
static void ofw_sparc64_suspend(chardev_t *d);
static void ofw_sparc64_resume(chardev_t *d);
mutex_t canwork;
static volatile int ofw_console_active;
static chardev_t ofw_sparc64_console;
static chardev_operations_t ofw_sparc64_console_ops = {
.write = ofw_sparc64_putchar,
.read = ofw_sparc64_getchar,
.resume = ofw_sparc64_resume,
.suspend = ofw_sparc64_suspend
};
/** Initialize kernel console to use OpenFirmware services. */
void ofw_sparc64_console_init(void)
{
chardev_initialize("ofw_sparc64_console", &ofw_sparc64_console, &ofw_sparc64_console_ops);
stdin = &ofw_sparc64_console;
stdout = &ofw_sparc64_console;
mutex_initialize(&canwork);
ofw_console_active = 1;
}
/** Initialize kernel console to use framebuffer and keyboard directly. */
void standalone_sparc64_console_init(void)
{
ofw_console_active = 0;
stdin = NULL;
kbd_init();
fb_init(FB_PHYS_ADDRESS, FB_X_RES, FB_Y_RES, FB_COLOR_DEPTH, FB_X_RES * FB_COLOR_DEPTH / 8);
}
/** Write one character using OpenFirmware.
*
* @param d Character device (ignored).
* @param ch Character to be written.
*/
void ofw_sparc64_putchar(chardev_t *d, const char ch)
{
pstate_reg_t pstate;
/*
* 32-bit OpenFirmware depends on PSTATE.AM bit set.
*/
pstate.value = pstate_read();
pstate.am = true;
pstate_write(pstate.value);
if (ch == '\n')
ofw_putchar('\r');
ofw_putchar(ch);
pstate.am = false;
pstate_write(pstate.value);
}
/** Read one character using OpenFirmware.
*
* The call is non-blocking.
*
* @param d Character device (ignored).
* @return Character read or zero if no character was read.
*/
char ofw_sparc64_getchar(chardev_t *d)
{
char ch;
pstate_reg_t pstate;
/*
* 32-bit OpenFirmware depends on PSTATE.AM bit set.
*/
pstate.value = pstate_read();
pstate.am = true;
pstate_write(pstate.value);
ch = ofw_getchar();
pstate.am = false;
pstate_write(pstate.value);
return ch;
}
void ofw_sparc64_suspend(chardev_t *d)
{
mutex_lock(&canwork);
}
void ofw_sparc64_resume(chardev_t *d)
{
mutex_unlock(&canwork);
}
/** Kernel thread for pushing characters read from OFW to input buffer.
*
* @param arg Ignored.
*/
void kofwinput(void *arg)
{
while (ofw_console_active) {
char ch = 0;
mutex_lock(&canwork);
mutex_unlock(&canwork);
ch = ofw_sparc64_getchar(NULL);
if (ch) {
if (ch == '\r')
ch = '\n';
chardev_push_character(&ofw_sparc64_console, ch);
}
thread_usleep(KEYBOARD_POLL_PAUSE);
}
}
/** Kernel thread for polling keyboard.
*
* @param arg Ignored.
*/
void kkbdpoll(void *arg)
{
while (1) {
i8042_poll();
thread_usleep(KEYBOARD_POLL_PAUSE);
}
}

/tags/0.2.0/kernel/arch/sparc64/src/mm/page.c
0,0 → 1,78
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/page.h>
#include <arch/mm/tlb.h>
#include <genarch/mm/page_ht.h>
#include <mm/frame.h>
#include <bitops.h>
#include <debug.h>
void page_arch_init(void)
{
page_mapping_operations = &ht_mapping_operations;
}
__address hw_map(__address physaddr, size_t size)
{
unsigned int order;
int i;
struct {
int pagesize;
size_t increment;
count_t count;
} sizemap[] = {
{ PAGESIZE_8K, 0, 1 }, /* 8K */
{ PAGESIZE_8K, PAGE_SIZE, 2 }, /* 16K */
{ PAGESIZE_8K, PAGE_SIZE, 4 }, /* 32K */
{ PAGESIZE_64K, 0, 1}, /* 64K */
{ PAGESIZE_64K, 8*PAGE_SIZE, 2 }, /* 128K */
{ PAGESIZE_64K, 8*PAGE_SIZE, 4 }, /* 256K */
{ PAGESIZE_512K, 0, 1 }, /* 512K */
{ PAGESIZE_512K, 64*PAGE_SIZE, 2 }, /* 1M */
{ PAGESIZE_512K, 64*PAGE_SIZE, 4 }, /* 2M */
{ PAGESIZE_4M, 0, 1 } /* 4M */
};
ASSERT(size <= 4*1024*1024);
if (size <= FRAME_SIZE)
order = 0;
else
order = (fnzb32(size - 1) + 1) - FRAME_WIDTH;
__address virtaddr = PA2KA(PFN2ADDR(frame_alloc(order, FRAME_KA)));
for (i = 0; i < sizemap[order].count; i++)
dtlb_insert_mapping(virtaddr + i*sizemap[order].increment,
physaddr + i*sizemap[order].increment,
sizemap[order].pagesize, true, false);
return virtaddr;
}

/tags/0.2.0/kernel/arch/sparc64/src/mm/tlb.c
0,0 → 1,274
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/tlb.h>
#include <mm/tlb.h>
#include <arch/mm/frame.h>
#include <arch/mm/page.h>
#include <arch/mm/mmu.h>
#include <mm/asid.h>
#include <print.h>
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
#include <arch/trap/trap.h>
#include <panic.h>
#include <arch/asm.h>
#include <symtab.h>
#include <arch/drivers/fb.h>
#include <arch/drivers/i8042.h>
char *context_encoding[] = {
"Primary",
"Secondary",
"Nucleus",
"Reserved"
};
/** Initialize ITLB and DTLB.
*
* The goal of this function is to disable MMU
* so that both TLBs can be purged and new
* kernel 4M locked entry can be installed.
* After TLB is initialized, MMU is enabled
* again.
*
* Switching MMU off imposes the requirement for
* the kernel to run in identity mapped environment.
*/
void tlb_arch_init(void)
{
tlb_tag_access_reg_t tag;
tlb_data_t data;
frame_address_t fr;
page_address_t pg;
fr.address = config.base;
pg.address = config.base;
immu_disable();
dmmu_disable();
/*
* Demap everything, especially OpenFirmware.
*/
itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
/*
* We do identity mapping of 4M-page at 4M.
*/
tag.value = ASID_KERNEL;
tag.vpn = pg.vpn;
itlb_tag_access_write(tag.value);
dtlb_tag_access_write(tag.value);
data.value = 0;
data.v = true;
data.size = PAGESIZE_4M;
data.pfn = fr.pfn;
data.l = true;
data.cp = 1;
data.cv = 1;
data.p = true;
data.w = true;
data.g = true;
itlb_data_in_write(data.value);
dtlb_data_in_write(data.value);
/*
* Register window traps can occur before MMU is enabled again.
* This ensures that any such traps will be handled from
* kernel identity mapped trap handler.
*/
trap_switch_trap_table();
tlb_invalidate_all();
dmmu_enable();
immu_enable();
}
/** Insert privileged mapping into DMMU TLB.
*
* @param page Virtual page address.
* @param frame Physical frame address.
* @param pagesize Page size.
* @param locked True for permanent mappings, false otherwise.
* @param cacheable True if the mapping is cacheable, false otherwise.
*/
void dtlb_insert_mapping(__address page, __address frame, int pagesize, bool locked, bool cacheable)
{
tlb_tag_access_reg_t tag;
tlb_data_t data;
page_address_t pg;
frame_address_t fr;
pg.address = page;
fr.address = frame;
tag.value = ASID_KERNEL;
tag.vpn = pg.vpn;
dtlb_tag_access_write(tag.value);
data.value = 0;
data.v = true;
data.size = pagesize;
data.pfn = fr.pfn;
data.l = locked;
data.cp = cacheable;
data.cv = cacheable;
data.p = true;
data.w = true;
data.g = true;
dtlb_data_in_write(data.value);
}
/** ITLB miss handler. */
void fast_instruction_access_mmu_miss(void)
{
panic("%s\n", __FUNCTION__);
}
/** DTLB miss handler. */
void fast_data_access_mmu_miss(void)
{
tlb_tag_access_reg_t tag;
__address tpc;
char *tpc_str;
tag.value = dtlb_tag_access_read();
if (tag.context != ASID_KERNEL || tag.vpn == 0) {
tpc = tpc_read();
tpc_str = get_symtab_entry(tpc);
printf("Faulting page: %p, ASID=%d\n", tag.vpn * PAGE_SIZE, tag.context);
printf("TPC=%p, (%s)\n", tpc, tpc_str ? tpc_str : "?");
panic("%s\n", __FUNCTION__);
}
/*
* Identity map piece of faulting kernel address space.
*/
dtlb_insert_mapping(tag.vpn * PAGE_SIZE, tag.vpn * FRAME_SIZE, PAGESIZE_8K, false, true);
}
/** DTLB protection fault handler. */
void fast_data_access_protection(void)
{
panic("%s\n", __FUNCTION__);
}
/** Print contents of both TLBs. */
void tlb_print(void)
{
int i;
tlb_data_t d;
tlb_tag_read_reg_t t;
printf("I-TLB contents:\n");
for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
d.value = itlb_data_access_read(i);
t.value = itlb_tag_read_read(i);
printf("%d: vpn=%#llX, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#X, diag=%#X, pfn=%#X, soft=%#X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
}
printf("D-TLB contents:\n");
for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
d.value = dtlb_data_access_read(i);
t.value = dtlb_tag_read_read(i);
printf("%d: vpn=%#llX, context=%d, v=%d, size=%d, nfo=%d, ie=%d, soft2=%#X, diag=%#X, pfn=%#X, soft=%#X, l=%d, cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n",
i, t.vpn, t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag, d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
}
}
/** Invalidate all unlocked ITLB and DTLB entries. */
void tlb_invalidate_all(void)
{
int i;
tlb_data_t d;
tlb_tag_read_reg_t t;
for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
d.value = itlb_data_access_read(i);
if (!d.l) {
t.value = itlb_tag_read_read(i);
d.v = false;
itlb_tag_access_write(t.value);
itlb_data_access_write(i, d.value);
}
}
for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
d.value = dtlb_data_access_read(i);
if (!d.l) {
t.value = dtlb_tag_read_read(i);
d.v = false;
dtlb_tag_access_write(t.value);
dtlb_data_access_write(i, d.value);
}
}
}
/** Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).
*
* @param asid Address Space ID.
*/
void tlb_invalidate_asid(asid_t asid)
{
/* TODO: write asid to some Context register and encode the register in second parameter below. */
itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
}
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
*
* @param asid Address Space ID.
* @param page First page which to sweep out from ITLB and DTLB.
* @param cnt Number of ITLB and DTLB entries to invalidate.
*/
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
int i;
for (i = 0; i < cnt; i++) {
/* TODO: write asid to some Context register and encode the register in second parameter below. */
itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
}
}

/tags/0.2.0/kernel/arch/sparc64/src/mm/memory_init.c
0,0 → 1,36
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/memory_init.h>
#include <genarch/ofw/memory_init.h>
#include <typedefs.h>
size_t get_memory_size(void)
{
return ofw_get_memory_size();
}

/tags/0.2.0/kernel/arch/sparc64/src/mm/frame.c
0,0 → 1,46
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/frame.h>
#include <genarch/ofw/memory_init.h>
#include <mm/frame.h>
#include <config.h>
#include <align.h>
void frame_arch_init(void)
{
ofw_init_zones();
/*
* Workaround to prevent slab allocator from allocating frame 0.
* Frame 0 is
* a) not mapped by OFW
* b) would be confused with NULL error return code
*/
frame_mark_unavailable(0, 1);
}

/tags/0.2.0/kernel/arch/sparc64/src/mm/as.c
0,0 → 1,38
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/as.h>
#include <genarch/mm/as_ht.h>
#include <genarch/mm/asid_fifo.h>
/** Architecture dependent address space init. */
void as_arch_init(void)
{
as_operations = &as_ht_operations;
asid_fifo_init();
}

/tags/0.2.0/kernel/arch/sparc64/src/drivers/i8042.c
0,0 → 1,40
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/drivers/i8042.h>
#include <genarch/i8042/i8042.h>
#include <arch/types.h>
#include <arch/mm/page.h>
volatile __u8 *kbd_virt_address = NULL;
void kbd_init()
{
kbd_virt_address = (__u8 *) hw_map(KBD_PHYS_ADDRESS, LAST_REG);
i8042_init();
}

/tags/0.2.0/kernel/arch/sparc64/src/drivers/tick.c
0,0 → 1,83
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/drivers/tick.h>
#include <arch/interrupt.h>
#include <arch/asm.h>
#include <arch/register.h>
#include <debug.h>
#include <time/clock.h>
#include <typedefs.h>
/** Initialize tick interrupt. */
void tick_init(void)
{
tick_compare_reg_t compare;
interrupt_register(14, "tick_int", tick_interrupt);
compare.int_dis = false;
compare.tick_cmpr = TICK_DELTA;
tick_compare_write(compare.value);
tick_write(0);
}
/** Process tick interrupt.
*
* @param n Interrupt Level, 14, (can be ignored)
* @param istate Interrupted state.
*/
void tick_interrupt(int n, istate_t *istate)
{
softint_reg_t softint, clear;
softint.value = softint_read();
/*
* Make sure we are servicing interrupt_level_14
*/
ASSERT(n == 14);
/*
* Make sure we are servicing TICK_INT.
*/
ASSERT(softint.tick_int);
/*
* Clear tick interrupt.
*/
clear.value = 0;
clear.tick_int = 1;
clear_softint_write(clear.value);
/*
* Restart counter.
*/
tick_write(0);
clock();
}

/tags/0.2.0/kernel/arch/sparc64/src/asm.S
0,0 → 1,53
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
.global memcpy
.global memcpy_from_uspace
.global memcpy_to_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace_failover_address
.global memsetb
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
b _memcpy
nop
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
b memcpy_from_uspace_failover_address
nop
memsetb:
b _memsetb
nop

/tags/0.2.0/kernel/arch/sparc64/src/ddi/ddi.c
0,0 → 1,47
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <ddi/ddi.h>
#include <proc/task.h>
#include <arch/types.h>
#include <typedefs.h>
/** Enable I/O space range for task.
*
* Interrupts are disabled and task is locked.
*
* @param task Task.
* @param ioaddr Startign I/O space address.
* @param size Size of the enabled I/O range.
*
* @return 0 on success or an error code from errno.h.
*/
int ddi_iospace_enable_arch(task_t *task, __address ioaddr, size_t size)
{
return 0;
}

/tags/0.2.0/kernel/arch/sparc64/src/trap/interrupt.c
0,0 → 1,53
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/interrupt.h>
#include <interrupt.h>
#include <arch/types.h>
#include <debug.h>
#include <ipc/sysipc.h>
/** Register Interrupt Level Handler.
*
* @param n Interrupt Level (1 - 15).
* @param name Short descriptive string.
* @param f Handler.
*/
void interrupt_register(int n, const char *name, iroutine f)
{
ASSERT(n >= IVT_FIRST && n <= IVT_ITEMS);
exc_register(n - 1, name, f);
}
/* Reregister irq to be IPC-ready */
void irq_ipc_bind_arch(__native irq)
{
panic("not implemented\n");
/* TODO */
}

/tags/0.2.0/kernel/arch/sparc64/src/trap/exception.c
0,0 → 1,55
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/trap/exception.h>
#include <arch/asm.h>
#include <debug.h>
/** Handle instruction_access_exception. */
void do_instruction_access_exc(void)
{
panic("Instruction Access Exception\n");
}
/** Handle mem_address_not_aligned. */
void do_mem_address_not_aligned(void)
{
panic("Memory Address Not Aligned\n");
}
/** Handle data_access_error. */
void do_data_access_error(void)
{
panic("Data Access Error: %P\n", tpc_read());
}
/** Handle mem_address_not_aligned. */
void do_illegal_instruction(void)
{
panic("Illegal Instruction: %P\n", tpc_read());
}

/tags/0.2.0/kernel/arch/sparc64/src/trap/trap_table.S
0,0 → 1,379
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
/**
* This file contains kernel trap table.
*/
.register %g2, #scratch
.register %g3, #scratch
.register %g6, #scratch
.register %g7, #scratch
.text
#include <arch/trap/trap_table.h>
#include <arch/trap/regwin.h>
#include <arch/trap/interrupt.h>
#include <arch/trap/exception.h>
#include <arch/trap/mmu.h>
#include <arch/stack.h>
#define TABLE_SIZE TRAP_TABLE_SIZE
#define ENTRY_SIZE TRAP_TABLE_ENTRY_SIZE
/*
* Kernel trap table.
*/
.align TABLE_SIZE
.global trap_table
trap_table:
/* TT = 0x08, TL = 0, instruction_access_exception */
.org trap_table + TT_INSTRUCTION_ACCESS_EXCEPTION*ENTRY_SIZE
.global instruction_access_exception
instruction_access_exception:
SIMPLE_HANDLER do_instruction_access_exc
/* TT = 0x10, TL = 0, illegal_instruction */
.org trap_table + TT_ILLEGAL_INSTRUCTION*ENTRY_SIZE
.global illegal_instruction
illegal_instruction:
SIMPLE_HANDLER do_illegal_instruction
/* TT = 0x24, TL = 0, clean_window handler */
.org trap_table + TT_CLEAN_WINDOW*ENTRY_SIZE
.global clean_window_handler
clean_window_handler:
CLEAN_WINDOW_HANDLER
/* TT = 0x32, TL = 0, data_access_error */
.org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE
.global data_access_error
data_access_error:
SIMPLE_HANDLER do_data_access_error
/* TT = 0x34, TL = 0, mem_address_not_aligned */
.org trap_table + TT_MEM_ADDRESS_NOT_ALIGNED*ENTRY_SIZE
.global mem_address_not_aligned
mem_address_not_aligned:
SIMPLE_HANDLER do_mem_address_not_aligned
/* TT = 0x41, TL = 0, interrupt_level_1 handler */
.org trap_table + TT_INTERRUPT_LEVEL_1*ENTRY_SIZE
.global interrupt_level_1_handler
interrupt_level_1_handler:
INTERRUPT_LEVEL_N_HANDLER 1
/* TT = 0x42, TL = 0, interrupt_level_2 handler */
.org trap_table + TT_INTERRUPT_LEVEL_2*ENTRY_SIZE
.global interrupt_level_2_handler
interrupt_level_2_handler:
INTERRUPT_LEVEL_N_HANDLER 2
/* TT = 0x43, TL = 0, interrupt_level_3 handler */
.org trap_table + TT_INTERRUPT_LEVEL_3*ENTRY_SIZE
.global interrupt_level_3_handler
interrupt_level_3_handler:
INTERRUPT_LEVEL_N_HANDLER 3
/* TT = 0x44, TL = 0, interrupt_level_4 handler */
.org trap_table + TT_INTERRUPT_LEVEL_4*ENTRY_SIZE
.global interrupt_level_4_handler
interrupt_level_4_handler:
INTERRUPT_LEVEL_N_HANDLER 4
/* TT = 0x45, TL = 0, interrupt_level_5 handler */
.org trap_table + TT_INTERRUPT_LEVEL_5*ENTRY_SIZE
.global interrupt_level_5_handler
interrupt_level_5_handler:
INTERRUPT_LEVEL_N_HANDLER 5
/* TT = 0x46, TL = 0, interrupt_level_6 handler */
.org trap_table + TT_INTERRUPT_LEVEL_6*ENTRY_SIZE
.global interrupt_level_6_handler
interrupt_level_6_handler:
INTERRUPT_LEVEL_N_HANDLER 6
/* TT = 0x47, TL = 0, interrupt_level_7 handler */
.org trap_table + TT_INTERRUPT_LEVEL_7*ENTRY_SIZE
.global interrupt_level_7_handler
interrupt_level_7_handler:
INTERRUPT_LEVEL_N_HANDLER 7
/* TT = 0x48, TL = 0, interrupt_level_8 handler */
.org trap_table + TT_INTERRUPT_LEVEL_8*ENTRY_SIZE
.global interrupt_level_8_handler
interrupt_level_8_handler:
INTERRUPT_LEVEL_N_HANDLER 8
/* TT = 0x49, TL = 0, interrupt_level_9 handler */
.org trap_table + TT_INTERRUPT_LEVEL_9*ENTRY_SIZE
.global interrupt_level_9_handler
interrupt_level_9_handler:
INTERRUPT_LEVEL_N_HANDLER 9
/* TT = 0x4a, TL = 0, interrupt_level_10 handler */
.org trap_table + TT_INTERRUPT_LEVEL_10*ENTRY_SIZE
.global interrupt_level_10_handler
interrupt_level_10_handler:
INTERRUPT_LEVEL_N_HANDLER 10
/* TT = 0x4b, TL = 0, interrupt_level_11 handler */
.org trap_table + TT_INTERRUPT_LEVEL_11*ENTRY_SIZE
.global interrupt_level_11_handler
interrupt_level_11_handler:
INTERRUPT_LEVEL_N_HANDLER 11
/* TT = 0x4c, TL = 0, interrupt_level_12 handler */
.org trap_table + TT_INTERRUPT_LEVEL_12*ENTRY_SIZE
.global interrupt_level_12_handler
interrupt_level_12_handler:
INTERRUPT_LEVEL_N_HANDLER 12
/* TT = 0x4d, TL = 0, interrupt_level_13 handler */
.org trap_table + TT_INTERRUPT_LEVEL_13*ENTRY_SIZE
.global interrupt_level_13_handler
interrupt_level_13_handler:
INTERRUPT_LEVEL_N_HANDLER 13
/* TT = 0x4e, TL = 0, interrupt_level_14 handler */
.org trap_table + TT_INTERRUPT_LEVEL_14*ENTRY_SIZE
.global interrupt_level_14_handler
interrupt_level_14_handler:
INTERRUPT_LEVEL_N_HANDLER 14
/* TT = 0x4f, TL = 0, interrupt_level_15 handler */
.org trap_table + TT_INTERRUPT_LEVEL_15*ENTRY_SIZE
.global interrupt_level_15_handler
interrupt_level_15_handler:
INTERRUPT_LEVEL_N_HANDLER 15
/* TT = 0x60, TL = 0, interrupt_vector_trap handler */
.org trap_table + TT_INTERRUPT_VECTOR_TRAP*ENTRY_SIZE
.global interrupt_vector_trap_handler
interrupt_vector_trap_handler:
INTERRUPT_VECTOR_TRAP_HANDLER
/* TT = 0x64, TL = 0, fast_instruction_access_MMU_miss */
.org trap_table + TT_FAST_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE
.global fast_instruction_access_mmu_miss_handler
fast_instruction_access_mmu_miss_handler:
FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
/* TT = 0x68, TL = 0, fast_data_access_MMU_miss */
.org trap_table + TT_FAST_DATA_ACCESS_MMU_MISS*ENTRY_SIZE
.global fast_data_access_mmu_miss_handler
fast_data_access_mmu_miss_handler:
FAST_DATA_ACCESS_MMU_MISS_HANDLER
/* TT = 0x6c, TL = 0, fast_data_access_protection */
.org trap_table + TT_FAST_DATA_ACCESS_PROTECTION*ENTRY_SIZE
.global fast_data_access_protection_handler
fast_data_access_protection_handler:
FAST_DATA_ACCESS_PROTECTION_HANDLER
/* TT = 0x80, TL = 0, spill_0_normal handler */
.org trap_table + TT_SPILL_0_NORMAL*ENTRY_SIZE
.global spill_0_normal
spill_0_normal:
SPILL_NORMAL_HANDLER
/* TT = 0xc0, TL = 0, fill_0_normal handler */
.org trap_table + TT_FILL_0_NORMAL*ENTRY_SIZE
.global fill_0_normal
fill_0_normal:
FILL_NORMAL_HANDLER
/*
* Handlers for TL>0.
*/
/* TT = 0x08, TL > 0, instruction_access_exception */
.org trap_table + (TT_INSTRUCTION_ACCESS_EXCEPTION+512)*ENTRY_SIZE
.global instruction_access_exception_high
instruction_access_exception_high:
SIMPLE_HANDLER do_instruction_access_exc
/* TT = 0x10, TL > 0, illegal_instruction */
.org trap_table + (TT_ILLEGAL_INSTRUCTION+512)*ENTRY_SIZE
.global illegal_instruction_high
illegal_instruction_high:
SIMPLE_HANDLER do_illegal_instruction
/* TT = 0x24, TL > 0, clean_window handler */
.org trap_table + (TT_CLEAN_WINDOW+512)*ENTRY_SIZE
.global clean_window_handler_high
clean_window_handler_high:
CLEAN_WINDOW_HANDLER
/* TT = 0x32, TL > 0, data_access_error */
.org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE
.global data_access_error_high
data_access_error_high:
SIMPLE_HANDLER do_data_access_error
/* TT = 0x34, TL > 0, mem_address_not_aligned */
.org trap_table + (TT_MEM_ADDRESS_NOT_ALIGNED+512)*ENTRY_SIZE
.global mem_address_not_aligned_high
mem_address_not_aligned_high:
SIMPLE_HANDLER do_mem_address_not_aligned
/* TT = 0x64, TL > 0, fast_instruction_access_MMU_miss */
.org trap_table + (TT_FAST_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE
.global fast_instruction_access_mmu_miss_handler_high
fast_instruction_access_mmu_miss_handler_high:
FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
/* TT = 0x68, TL > 0, fast_data_access_MMU_miss */
.org trap_table + (TT_FAST_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE
.global fast_data_access_mmu_miss_handler_high
fast_data_access_mmu_miss_handler_high:
FAST_DATA_ACCESS_MMU_MISS_HANDLER
/* TT = 0x6c, TL > 0, fast_data_access_protection */
.org trap_table + (TT_FAST_DATA_ACCESS_PROTECTION+512)*ENTRY_SIZE
.global fast_data_access_protection_handler_high
fast_data_access_protection_handler_high:
FAST_DATA_ACCESS_PROTECTION_HANDLER
/* TT = 0x80, TL > 0, spill_0_normal handler */
.org trap_table + (TT_SPILL_0_NORMAL+512)*ENTRY_SIZE
.global spill_0_normal_high
spill_0_normal_high:
SPILL_NORMAL_HANDLER
/* TT = 0xc0, TL > 0, fill_0_normal handler */
.org trap_table + (TT_FILL_0_NORMAL+512)*ENTRY_SIZE
.global fill_0_normal_high
fill_0_normal_high:
FILL_NORMAL_HANDLER
/* Preemptible trap handler.
*
* This trap handler makes arrangements to
* make calling scheduler() possible.
*
* The caller is responsible for doing save
* and allocating PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE
* bytes on stack.
*
* Input registers:
* %l0 Address of function to call.
* Output registers:
* %l1 - %l7 Copy of %g1 - %g7
*/
.global preemptible_handler
preemptible_handler:
/*
* Save TSTATE, TPC, TNPC and PSTATE aside.
*/
rdpr %tstate, %g1
rdpr %tpc, %g2
rdpr %tnpc, %g3
rdpr %pstate, %g4
stx %g1, [%fp + STACK_BIAS + SAVED_TSTATE]
stx %g2, [%fp + STACK_BIAS + SAVED_TPC]
stx %g3, [%fp + STACK_BIAS + SAVED_TNPC]
stx %g4, [%fp + STACK_BIAS + SAVED_PSTATE]
/*
* Write 0 to TL.
*/
wrpr %g0, 0, %tl
/*
* Alter PSTATE.
* - switch to normal globals.
*/
and %g4, ~1, %g4 ! mask alternate globals
wrpr %g4, 0, %pstate
/*
* Save the normal globals.
*/
SAVE_GLOBALS
/*
* Call the higher-level handler.
*/
call %l0
nop
/*
* Restore the normal global register set.
*/
RESTORE_GLOBALS
/*
* Restore PSTATE from saved copy.
* Alternate globals become active.
*/
ldx [%fp + STACK_BIAS + SAVED_PSTATE], %l4
wrpr %l4, 0, %pstate
/*
* Write 1 to TL.
*/
wrpr %g0, 1, %tl
/*
* Read TSTATE, TPC and TNPC from saved copy.
*/
ldx [%fp + STACK_BIAS + SAVED_TSTATE], %g1
ldx [%fp + STACK_BIAS + SAVED_TPC], %g2
ldx [%fp + STACK_BIAS + SAVED_TNPC], %g3
/*
* Do restore to match the save instruction from the top-level handler.
*/
restore
/*
* On execution of retry instruction, CWP will be restored from TSTATE register.
* However, because of scheduling, it is possible that CWP in saved TSTATE
* is different from current CWP. The following chunk of code fixes CWP
* in the saved copy of TSTATE.
*/
rdpr %cwp, %g4 ! read current CWP
and %g1, ~0x1f, %g1 ! clear CWP field in saved TSTATE
or %g1, %g4, %g1 ! write current CWP to TSTATE
/*
* Restore TSTATE, TPC and TNPC from saved copies.
*/
wrpr %g1, 0, %tstate
wrpr %g2, 0, %tpc
wrpr %g3, 0, %tnpc
/*
* Return from interrupt.
*/
retry

/tags/0.2.0/kernel/arch/sparc64/src/trap/trap.c
0,0 → 1,45
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/trap/trap.h>
#include <arch/trap/trap_table.h>
#include <arch/trap/regwin.h>
#include <arch/trap/exception.h>
#include <arch/trap/interrupt.h>
#include <arch/trap/mmu.h>
#include <arch/asm.h>
#include <memstr.h>
#include <debug.h>
#include <arch/types.h>
#include <typedefs.h>
#include <arch/drivers/tick.h>
/** Initialize trap table. */
void trap_init(void)
{
}

/tags/0.2.0/kernel/arch/sparc64/src/proc/scheduler.c
0,0 → 1,74
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <proc/scheduler.h>
#include <proc/thread.h>
#include <arch.h>
#include <arch/mm/tlb.h>
#include <arch/mm/page.h>
#include <config.h>
#include <align.h>
/** Perform sparc64 specific tasks needed before the new task is run. */
void before_task_runs_arch(void)
{
}
/** Ensure that thread's kernel stack is locked in TLB. */
void before_thread_runs_arch(void)
{
__address base;
base = ALIGN_DOWN(config.base, 1<<KERNEL_PAGE_WIDTH);
if ((__address) THREAD->kstack < base || (__address) THREAD->kstack > base + (1<<KERNEL_PAGE_WIDTH)) {
/*
* Kernel stack of this thread is not locked in DTLB.
* First, make sure it is not mapped already.
* If not, create a locked mapping for it.
*/
dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, (__address) THREAD->kstack);
dtlb_insert_mapping((__address) THREAD->kstack, KA2PA(THREAD->kstack), PAGESIZE_8K, true, true);
}
}
/** Unlock thread's stack from TLB, if necessary. */
void after_thread_ran_arch(void)
{
__address base;
base = ALIGN_DOWN(config.base, 1<<KERNEL_PAGE_WIDTH);
if ((__address) THREAD->kstack < base || (__address) THREAD->kstack > base + (1<<KERNEL_PAGE_WIDTH)) {
/*
* Kernel stack of this thread is locked in DTLB.
* Destroy the mapping.
*/
dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, (__address) THREAD->kstack);
}
}

/tags/0.2.0/kernel/arch/sparc64/src/dummy.s
0,0 → 1,68
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
.global asm_delay_loop
.global cpu_sleep
.global fmath_dpow
.global fmath_fint
.global fmath_get_decimal_exponent
.global fmath_is_infinity
.global fmath_is_nan
.global fpu_context_restore
.global fpu_context_save
.global fpu_enable
.global fpu_init
.global userspace
.global sys_tls_set
.global dummy
asm_delay_loop:
cpu_sleep:
fmath_dpow:
fmath_fint:
fmath_get_decimal_exponent:
fmath_is_infinity:
fmath_is_nan:
fpu_context_restore:
fpu_context_save:
fpu_enable:
fpu_init:
userspace:
sys_tls_set:
dummy:
retl
nop
.global cpu_halt
cpu_halt:
b cpu_halt
nop

/tags/0.2.0/kernel/arch/sparc64/src/start.S
0,0 → 1,113
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/boot/boot.h>
.register %g2, #scratch
.register %g3, #scratch
.register %g6, #scratch
.register %g7, #scratch
.section K_TEXT_START, "ax"
/*
* Here is where the kernel is passed control.
* The code must be position independent until
* the kernel relocates itself to its VMA.
*/
.global kernel_image_start
kernel_image_start:
0:
b 1f
nop
/*
* This header forces SILO to load the kernel at 0x4000.
* More precisely, SILO will think this is an old version of Linux.
*/
.ascii "HdrS"
.word 0
.half 0
.align 8
1:
flushw ! flush all but the active register window
/*
* Prepare to copy the kernel image to 4M.
*/
set LMA, %g1 ! source address
set VMA, %g2 ! destination address
set hardcoded_ktext_size, %g3 ! link address of hardcoded_ktext_size
set hardcoded_kdata_size, %g4 ! link address of hardcoded_kdata_size
sub %g3, %g2, %g3 ! offset of hardcoded_ktext_size from the beginning of the load address
sub %g4, %g2, %g4 ! offset of hardcoded_kdata_size from the beginning of the load address
ldx [%g3 + %g1], %g3 ! hardcoded_ktext_size -> %g3
ldx [%g4 + %g1], %g4 ! hardcoded_kdata_size -> %g4
add %g3, %g4, %g3 ! size of kernel text and data
/*
* Start copying the kernel from higher addresses towards lower addresses.
*/
2: dec %g3
ldub [%g1 + %g3], %g4
stb %g4, [%g2 + %g3]
cmp %g3, 0
bnz 2b
nop
set relocated, %g1
jmp %g1
nop
relocated:
set ofw, %l0
call ofw_init
stx %o4, [%l0]
call ofw_init_memmap
nop
wrpr %r0, 0, %pil
call main_bsp
nop
/* Not reached. */
2:
b 2b
nop

/tags/0.2.0/kernel/arch/sparc64/src/panic.S
0,0 → 1,40
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
#include <arch/stack.h>
.global panic_printf
panic_printf:
call printf
nop
call halt
nop
/* Not reached. */

/tags/0.2.0/kernel/arch/sparc64/src/context.S
0,0 → 1,108
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/context_offset.h>
#include <arch/stack.h>
/**
* Both context_save_arch() and context_restore_arch() are
* leaf-optimized procedures. This kind of optimization
* is very important and prevents any implicit window
* spill/fill/clean traps in these very core kernel
* functions.
*/
.text
.global context_save_arch
.global context_restore_arch
.macro CONTEXT_STORE r
stx %sp, [\r + OFFSET_SP]
stx %o7, [\r + OFFSET_PC]
stx %i0, [\r + OFFSET_I0]
stx %i1, [\r + OFFSET_I1]
stx %i2, [\r + OFFSET_I2]
stx %i3, [\r + OFFSET_I3]
stx %i4, [\r + OFFSET_I4]
stx %i5, [\r + OFFSET_I5]
stx %fp, [\r + OFFSET_FP]
stx %i7, [\r + OFFSET_I7]
stx %l0, [\r + OFFSET_L0]
stx %l1, [\r + OFFSET_L1]
stx %l2, [\r + OFFSET_L2]
stx %l3, [\r + OFFSET_L3]
stx %l4, [\r + OFFSET_L4]
stx %l5, [\r + OFFSET_L5]
stx %l6, [\r + OFFSET_L6]
stx %l7, [\r + OFFSET_L7]
rdpr %cleanwin, %g1
stx %g1, [\r + OFFSET_CLEANWIN]
.endm
.macro CONTEXT_LOAD r
ldx [\r + OFFSET_SP], %sp
ldx [\r + OFFSET_PC], %o7
ldx [\r + OFFSET_I0], %i0
ldx [\r + OFFSET_I1], %i1
ldx [\r + OFFSET_I2], %i2
ldx [\r + OFFSET_I3], %i3
ldx [\r + OFFSET_I4], %i4
ldx [\r + OFFSET_I5], %i5
ldx [\r + OFFSET_FP], %fp
ldx [\r + OFFSET_I7], %i7
ldx [\r + OFFSET_L0], %l0
ldx [\r + OFFSET_L1], %l1
ldx [\r + OFFSET_L2], %l2
ldx [\r + OFFSET_L3], %l3
ldx [\r + OFFSET_L4], %l4
ldx [\r + OFFSET_L5], %l5
ldx [\r + OFFSET_L6], %l6
ldx [\r + OFFSET_L7], %l7
ldx [\r + OFFSET_CLEANWIN], %g1
wrpr %g1, %g0, %cleanwin
.endm
context_save_arch:
CONTEXT_STORE %o0
retl
mov 1, %o0 ! context_save_arch returns 1
context_restore_arch:
#
# Flush all active windows.
# This is essential, because CONTEXT_LOAD overwrites
# %sp of CWP - 1 with the value written to %fp of CWP.
# Flushing all active windows mitigates this problem
# as CWP - 1 becomes the overlap window.
#
flushw
CONTEXT_LOAD %o0
retl
xor %o0, %o0, %o0 ! context_restore_arch returns 0

/tags/0.2.0/kernel/arch/sparc64/src/cpu/cpu.c
0,0 → 1,91
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <cpu.h>
#include <arch.h>
#include <arch/register.h>
#include <arch/asm.h>
#include <print.h>
void cpu_arch_init(void)
{
}
void cpu_identify(void)
{
CPU->arch.ver.value = ver_read();
}
void cpu_print_report(cpu_t *m)
{
char *manuf, *impl;
switch (CPU->arch.ver.manuf) {
case MANUF_FUJITSU:
manuf = "Fujitsu";
break;
case MANUF_ULTRASPARC:
manuf = "UltraSPARC";
break;
case MANUF_SUN:
manuf = "Sun";
break;
default:
manuf = "Unknown";
break;
}
switch (CPU->arch.ver.impl) {
case IMPL_ULTRASPARCI:
impl = "UltraSPARC I";
break;
case IMPL_ULTRASPARCII:
impl = "UltraSPARC II";
break;
case IMPL_ULTRASPARCII_I:
impl = "UltraSPARC IIi";
break;
case IMPL_ULTRASPARCII_E:
impl = "UltraSPARC IIe";
break;
case IMPL_ULTRASPARCIII:
impl = "UltraSPARC III";
break;
case IMPL_ULTRASPARCIV_PLUS:
impl = "UltraSPARC IV+";
break;
case IMPL_SPARC64V:
impl = "SPARC 64V";
break;
default:
impl = "Unknown";
break;
}
printf("cpu%d: manuf=%s, impl=%s, mask=%d\n", CPU->id, manuf, impl, CPU->arch.ver.mask);
}

/tags/0.2.0/kernel/arch/sparc64/Makefile.inc
0,0 → 1,94
#
# Copyright (C) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
## Toolchain configuration
#
BFD_NAME = elf64-sparc
BFD_ARCH = sparc
BFD = elf64-sparc
TARGET = sparc64-linux-gnu
TOOLCHAIN_DIR = /usr/local/sparc64/bin
## Make some default assumptions
#
CFLAGS += -mcpu=ultrasparc -m64
LFLAGS += -no-check-sections -N
DEFS += -D__64_BITS__
## Own configuration directives
#
CONFIG_OFW = y
## Compile with page hash table support.
#
CONFIG_PAGE_HT = y
DEFS += -DCONFIG_PAGE_HT
## Compile with support for address space identifiers.
#
CONFIG_ASID = y
CONFIG_ASID_FIFO = y
## Compile with support for framebuffer.
#
CONFIG_FB = y
## Compile with support for i8042 controller.
#
CONFIG_I8042 = y
ARCH_SOURCES = \
arch/$(ARCH)/src/cpu/cpu.c \
arch/$(ARCH)/src/asm.S \
arch/$(ARCH)/src/panic.S \
arch/$(ARCH)/src/console.c \
arch/$(ARCH)/src/context.S \
arch/$(ARCH)/src/dummy.s \
arch/$(ARCH)/src/mm/as.c \
arch/$(ARCH)/src/mm/frame.c \
arch/$(ARCH)/src/mm/page.c \
arch/$(ARCH)/src/mm/tlb.c \
arch/$(ARCH)/src/mm/memory_init.c \
arch/$(ARCH)/src/sparc64.c \
arch/$(ARCH)/src/start.S \
arch/$(ARCH)/src/proc/scheduler.c \
arch/$(ARCH)/src/trap/trap_table.S \
arch/$(ARCH)/src/trap/trap.c \
arch/$(ARCH)/src/trap/exception.c \
arch/$(ARCH)/src/trap/interrupt.c \
arch/$(ARCH)/src/ddi/ddi.c \
arch/$(ARCH)/src/drivers/tick.c \
arch/$(ARCH)/src/drivers/i8042.c

/tags/0.2.0/kernel/arch/sparc64/_link.ld.in
0,0 → 1,49
/** SPARC64 linker script
*
* It is ELF format, but its only section looks like this:
* kernel text
* kernel data
*
*/
#define __ASM__
#include <arch/boot/boot.h>
ENTRY(kernel_image_start)
SECTIONS {
.image VMA: AT (LMA) {
ktext_start = .;
*(K_TEXT_START)
*(.text);
ktext_end = .;
kdata_start = .;
*(K_DATA_START)
*(.rodata);
*(.rodata.*);
*(.data); /* initialized data */
*(.sdata);
*(.sdata2);
*(.sbss);
hardcoded_ktext_size = .;
QUAD(ktext_end - ktext_start);
hardcoded_kdata_size = .;
QUAD(kdata_end - kdata_start);
hardcoded_load_address = .;
QUAD(VMA);
*(.bss); /* uninitialized static variables */
*(COMMON); /* global variables */
symbol_table = .;
*(symtab.*); /* Symbol table, must be LAST symbol!*/
kdata_end = .;
}
/DISCARD/ : {
*(.comment);
*(.note*);
}
}

/tags/0.2.0/kernel/arch/ppc64/include/exception.h
0,0 → 1,95
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_EXCEPTION_H__
#define __ppc64_EXCEPTION_H__
#ifndef __ppc64_TYPES_H__
# include <arch/types.h>
#endif
#include <typedefs.h>
struct istate {
__u64 r0;
__u64 r2;
__u64 r3;
__u64 r4;
__u64 r5;
__u64 r6;
__u64 r7;
__u64 r8;
__u64 r9;
__u64 r10;
__u64 r11;
__u64 r13;
__u64 r14;
__u64 r15;
__u64 r16;
__u64 r17;
__u64 r18;
__u64 r19;
__u64 r20;
__u64 r21;
__u64 r22;
__u64 r23;
__u64 r24;
__u64 r25;
__u64 r26;
__u64 r27;
__u64 r28;
__u64 r29;
__u64 r30;
__u64 r31;
__u64 cr;
__u64 pc;
__u64 srr1;
__u64 lr;
__u64 ctr;
__u64 xer;
__u64 r12;
__u64 sp;
};
static inline void istate_set_retaddr(istate_t *istate, __address retaddr)
{
istate->pc = retaddr;
}
/** Return true if exception happened while in userspace */
#include <panic.h>
static inline int istate_from_uspace(istate_t *istate)
{
panic("istate_from_uspace not yet implemented");
return 0;
}
static inline __native istate_get_pc(istate_t *istate)
{
return istate->pc;
}
#endif

/tags/0.2.0/kernel/arch/ppc64/include/proc/task.h
0,0 → 1,38
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_TASK_H__
#define __ppc64_TASK_H__
typedef struct {
} task_arch_t;
#define task_create_arch(t)
#define task_destroy_arch(t)
#endif

/tags/0.2.0/kernel/arch/ppc64/include/proc/thread.h
0,0 → 1,37
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_THREAD_H__
#define __ppc64_THREAD_H__
typedef struct {
} thread_arch_t;
#define thread_create_arch(t)
#endif

/tags/0.2.0/kernel/arch/ppc64/include/mm/as.h
0,0 → 1,45
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_AS_H__
#define __ppc64_AS_H__
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 0
#define KERNEL_ADDRESS_SPACE_START_ARCH ((unsigned long) 0x80000000)
#define KERNEL_ADDRESS_SPACE_END_ARCH ((unsigned long) 0xffffffff)
#define USER_ADDRESS_SPACE_START_ARCH ((unsigned long) 0x00000000)
#define USER_ADDRESS_SPACE_END_ARCH ((unsigned long) 0x7fffffff)
#define USTACK_ADDRESS_ARCH (0x7fffffff-(PAGE_SIZE-1))
#define as_install_arch(as)
extern void as_arch_init(void);
#endif

/tags/0.2.0/kernel/arch/ppc64/include/mm/asid.h
0,0 → 1,39
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_ASID_H__
#define __ppc64_ASID_H__
typedef int asid_t;
#define ASID_MAX_ARCH 3
#define asid_get() (ASID_START+1)
#define asid_put(asid)
#endif

/tags/0.2.0/kernel/arch/ppc64/include/mm/page.h
0,0 → 1,153
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_PAGE_H__
#define __ppc64_PAGE_H__
#include <arch/mm/frame.h>
#define PAGE_WIDTH FRAME_WIDTH
#define PAGE_SIZE FRAME_SIZE
#ifdef KERNEL
#ifndef __ASM__
# define KA2PA(x) (((__address) (x)) - 0x80000000)
# define PA2KA(x) (((__address) (x)) + 0x80000000)
#else
# define KA2PA(x) ((x) - 0x80000000)
# define PA2KA(x) ((x) + 0x80000000)
#endif
/*
* Implementation of generic 4-level page table interface,
* the hardware Page Hash Table is used as cache.
*
* Page table layout:
* - 32-bit virtual addressess
* - Offset is 12 bits => pages are 4K long
* - PTL0 has 1024 entries (10 bits)
* - PTL1 is not used
* - PTL2 is not used
* - PLT3 has 1024 entries (10 bits)
*/
#define PTL0_ENTRIES_ARCH 1024
#define PTL1_ENTRIES_ARCH 0
#define PTL2_ENTRIES_ARCH 0
#define PTL3_ENTRIES_ARCH 1024
#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff)
#define PTL1_INDEX_ARCH(vaddr) 0
#define PTL2_INDEX_ARCH(vaddr) 0
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff)
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) (((pte_t *) (ptl0))[(i)].pfn << 12)
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) (((pte_t *) (ptl3))[(i)].pfn << 12)
#define SET_PTL0_ADDRESS_ARCH(ptl0)
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_flags((pte_t *) (ptl0), (index_t) (i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_flags((pte_t *) (ptl3), (index_t) (i))
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
#define PTE_VALID_ARCH(pte) (*((__u32 *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte) ((pte)->p != 0)
#define PTE_GET_FRAME_ARCH(pte) ((__address) ((pte)->pfn << 12))
#define PTE_WRITABLE_ARCH(pte) 1
#define PTE_EXECUTABLE_ARCH(pte) 1
#ifndef __ASM__
#include <mm/page.h>
#include <arch/mm/frame.h>
#include <arch/types.h>
static inline int get_pt_flags(pte_t *pt, index_t i)
{
pte_t *p = &pt[i];
return (
(1 << PAGE_CACHEABLE_SHIFT) |
((!p->p) << PAGE_PRESENT_SHIFT) |
(1 << PAGE_USER_SHIFT) |
(1 << PAGE_READ_SHIFT) |
(1 << PAGE_WRITE_SHIFT) |
(1 << PAGE_EXEC_SHIFT) |
(p->g << PAGE_GLOBAL_SHIFT)
);
}
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
{
pte_t *p = &pt[i];
p->p = !(flags & PAGE_NOT_PRESENT);
p->g = (flags & PAGE_GLOBAL) != 0;
p->valid = 1;
}
extern void page_arch_init(void);
#define PHT_BITS 16
#define PHT_ORDER 4
typedef struct {
unsigned v : 1; /**< Valid */
unsigned vsid : 24; /**< Virtual Segment ID */
unsigned h : 1; /**< Primary/secondary hash */
unsigned api : 6; /**< Abbreviated Page Index */
unsigned rpn : 20; /**< Real Page Number */
unsigned reserved0 : 3;
unsigned r : 1; /**< Reference */
unsigned c : 1; /**< Change */
unsigned wimg : 4; /**< Access control */
unsigned reserved1 : 1;
unsigned pp : 2; /**< Page protection */
} phte_t;
extern void pht_refill(bool data, istate_t *istate);
extern void pht_init(void);
#endif /* __ASM__ */
#endif /* KERNEL */
#endif

/tags/0.2.0/kernel/arch/ppc64/include/mm/frame.h
0,0 → 1,47
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_FRAME_H__
#define __ppc64_FRAME_H__
#define FRAME_WIDTH 12 /* 4K */
#define FRAME_SIZE (1 << FRAME_WIDTH)
#ifdef KERNEL
#ifndef __ASM__
#include <arch/types.h>
extern __address last_frame;
extern void frame_arch_init(void);
#endif /* __ASM__ */
#endif /* KERNEL */
#endif

/tags/0.2.0/kernel/arch/ppc64/include/mm/tlb.h
0,0 → 1,33
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_TLB_H__
#define __ppc64_TLB_H__
#endif

/tags/0.2.0/kernel/arch/ppc64/include/mm/memory_init.h
0,0 → 1,38
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_MEMORY_INIT_H__
#define __ppc64_MEMORY_INIT_H__
#include <typedefs.h>
size_t get_memory_size(void);
void memory_print_map(void);
#endif

/tags/0.2.0/kernel/arch/ppc64/include/types.h
0,0 → 1,60
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_TYPES_H__
#define __ppc64_TYPES_H__
#define NULL 0
typedef signed char __s8;
typedef signed short __s16;
typedef signed int __s32;
typedef signed long __s64;
typedef unsigned char __u8;
typedef unsigned short __u16;
typedef unsigned int __u32;
typedef unsigned long __u64;
typedef __u64 __address;
typedef __u64 pfn_t;
typedef __u64 ipl_t;
typedef __u64 __native;
/** Page Table Entry. */
typedef struct {
unsigned p : 1; /**< Present bit. */
unsigned a : 1; /**< Accessed bit. */
unsigned g : 1; /**< Global bit. */
unsigned valid : 1; /**< Valid content even if not present. */
unsigned pfn : 20; /**< Physical frame number. */
} pte_t;
#endif

/tags/0.2.0/kernel/arch/ppc64/include/asm.h
0,0 → 1,152
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_ASM_H__
#define __ppc64_ASM_H__
#include <arch/types.h>
#include <config.h>
/** Enable interrupts.
*
* Enable interrupts and return previous
* value of EE.
*
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_enable(void)
{
ipl_t v;
ipl_t tmp;
asm volatile (
"mfmsr %0\n"
"mfmsr %1\n"
"ori %1, %1, 1 << 15\n"
"mtmsr %1\n"
: "=r" (v), "=r" (tmp)
);
return v;
}
/** Disable interrupts.
*
* Disable interrupts and return previous
* value of EE.
*
* @return Old interrupt priority level.
*/
static inline ipl_t interrupts_disable(void)
{
ipl_t v;
ipl_t tmp;
asm volatile (
"mfmsr %0\n"
"mfmsr %1\n"
"rlwinm %1, %1, 0, 17, 15\n"
"mtmsr %1\n"
: "=r" (v), "=r" (tmp)
);
return v;
}
/** Restore interrupt priority level.
*
* Restore EE.
*
* @param ipl Saved interrupt priority level.
*/
static inline void interrupts_restore(ipl_t ipl)
{
ipl_t tmp;
asm volatile (
"mfmsr %1\n"
"rlwimi %0, %1, 0, 17, 15\n"
"cmpw 0, %0, %1\n"
"beq 0f\n"
"mtmsr %0\n"
"0:\n"
: "=r" (ipl), "=r" (tmp)
: "0" (ipl)
: "cr0"
);
}
/** Return interrupt priority level.
*
* Return EE.
*
* @return Current interrupt priority level.
*/
static inline ipl_t interrupts_read(void)
{
ipl_t v;
asm volatile (
"mfmsr %0\n"
: "=r" (v)
);
return v;
}
/** Return base address of current stack.
*
* Return the base address of the current stack.
* The stack is assumed to be STACK_SIZE bytes long.
* The stack must start on page boundary.
*/
static inline __address get_stack_base(void)
{
__address v;
asm volatile (
"and %0, %%sp, %1\n"
: "=r" (v)
: "r" (~(STACK_SIZE - 1))
);
return v;
}
static inline void cpu_sleep(void)
{
}
static inline void cpu_halt(void)
{
asm volatile (
"b 0\n"
);
}
void asm_delay_loop(__u32 t);
extern void userspace_asm(__address uspace_uarg, __address stack, __address entry);
#endif

/tags/0.2.0/kernel/arch/ppc64/include/asm/regname.h
0,0 → 1,206
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_REGNAME_H__
#define __ppc64_REGNAME_H__
/* Condition Register Bit Fields */
#define cr0 0
#define cr1 1
#define cr2 2
#define cr3 3
#define cr4 4
#define cr5 5
#define cr6 6
#define cr7 7
/* General Purpose Registers (GPRs) */
#define r0 0
#define r1 1
#define r2 2
#define r3 3
#define r4 4
#define r5 5
#define r6 6
#define r7 7
#define r8 8
#define r9 9
#define r10 10
#define r11 11
#define r12 12
#define r13 13
#define r14 14
#define r15 15
#define r16 16
#define r17 17
#define r18 18
#define r19 19
#define r20 20
#define r21 21
#define r22 22
#define r23 23
#define r24 24
#define r25 25
#define r26 26
#define r27 27
#define r28 28
#define r29 29
#define r30 30
#define r31 31
/* GPR Aliases */
#define sp 1
/* Floating Point Registers (FPRs) */
#define fr0 0
#define fr1 1
#define fr2 2
#define fr3 3
#define fr4 4
#define fr5 5
#define fr6 6
#define fr7 7
#define fr8 8
#define fr9 9
#define fr10 10
#define fr11 11
#define fr12 12
#define fr13 13
#define fr14 14
#define fr15 15
#define fr16 16
#define fr17 17
#define fr18 18
#define fr19 19
#define fr20 20
#define fr21 21
#define fr22 22
#define fr23 23
#define fr24 24
#define fr25 25
#define fr26 26
#define fr27 27
#define fr28 28
#define fr29 29
#define fr30 30
#define fr31 31
#define vr0 0
#define vr1 1
#define vr2 2
#define vr3 3
#define vr4 4
#define vr5 5
#define vr6 6
#define vr7 7
#define vr8 8
#define vr9 9
#define vr10 10
#define vr11 11
#define vr12 12
#define vr13 13
#define vr14 14
#define vr15 15
#define vr16 16
#define vr17 17
#define vr18 18
#define vr19 19
#define vr20 20
#define vr21 21
#define vr22 22
#define vr23 23
#define vr24 24
#define vr25 25
#define vr26 26
#define vr27 27
#define vr28 28
#define vr29 29
#define vr30 30
#define vr31 31
#define evr0 0
#define evr1 1
#define evr2 2
#define evr3 3
#define evr4 4
#define evr5 5
#define evr6 6
#define evr7 7
#define evr8 8
#define evr9 9
#define evr10 10
#define evr11 11
#define evr12 12
#define evr13 13
#define evr14 14
#define evr15 15
#define evr16 16
#define evr17 17
#define evr18 18
#define evr19 19
#define evr20 20
#define evr21 21
#define evr22 22
#define evr23 23
#define evr24 24
#define evr25 25
#define evr26 26
#define evr27 27
#define evr28 28
#define evr29 29
#define evr30 30
#define evr31 31
/* Special Purpose Registers (SPRs) */
#define xer 1
#define lr 8
#define ctr 9
#define dec 22
#define sdr1 25
#define srr0 26
#define srr1 27
#define sprg0 272
#define sprg1 273
#define sprg2 274
#define sprg3 275
#define prv 287
#define hid0 1008
/* MSR bits */
#define msr_ir (1 << 4)
#define msr_dr (1 << 5)
#define msr_pr (1 << 14)
#define msr_ee (1 << 15)
/* HID0 bits */
#define hid0_ice (1 << 15)
#define hid0_dce (1 << 14)
#define hid0_icfi (1 << 11)
#define hid0_dci (1 << 10)
#endif

/tags/0.2.0/kernel/arch/ppc64/include/byteorder.h
0,0 → 1,64
/*
* Copyright (C) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_BYTEORDER_H__
#define __ppc64_BYTEORDER_H__
#include <arch/types.h>
#include <byteorder.h>
#define BIG_ENDIAN
static inline __u64 __u64_le2host(__u64 n)
{
return __u64_byteorder_swap(n);
}
/** Convert little-endian __native to host __native
*
* Convert little-endian __native parameter to host endianess.
*
* @param n Little-endian __native argument.
*
* @return Result in host endianess.
*
*/
static inline __native __native_le2host(__native n)
{
__address v;
asm volatile (
"lwbrx %0, %1, %2\n"
: "=r" (v)
: "i" (0), "r" (&n)
);
return v;
}
#endif

/tags/0.2.0/kernel/arch/ppc64/include/cpuid.h
0,0 → 1,47
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_CPUID_H__
#define __ppc64_CPUID_H__
#include <arch/types.h>
struct cpu_info {
__u16 version;
__u16 revision;
} __attribute__ ((packed));
static inline void cpu_version(struct cpu_info *info)
{
asm volatile (
"mfpvr %0\n"
: "=r" (*info)
);
}
#endif

/tags/0.2.0/kernel/arch/ppc64/include/elf.h
0,0 → 1,36
/*
* Copyright (C) 2006 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_ELF_H__
#define __ppc64_ELF_H__
#define ELF_MACHINE EM_PPC64
#define ELF_DATA_ENCODING ELFDATA2MSB
#define ELF_CLASS ELFCLASS32
#endif

/tags/0.2.0/kernel/arch/ppc64/include/atomic.h
0,0 → 1,88
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_ATOMIC_H__
#define __ppc64_ATOMIC_H__
static inline void atomic_inc(atomic_t *val)
{
long tmp;
asm volatile (
"1:\n"
"lwarx %0, 0, %2\n"
"addic %0, %0, 1\n"
"stwcx. %0, 0, %2\n"
"bne- 1b"
: "=&r" (tmp), "=m" (val->count)
: "r" (&val->count), "m" (val->count)
: "cc"
);
}
static inline void atomic_dec(atomic_t *val)
{
long tmp;
asm volatile (
"1:\n"
"lwarx %0, 0, %2\n"
"addic %0, %0, -1\n"
"stwcx. %0, 0, %2\n"
"bne- 1b"
: "=&r" (tmp), "=m" (val->count)
: "r" (&val->count), "m" (val->count)
: "cc"
);
}
static inline long atomic_postinc(atomic_t *val)
{
atomic_inc(val);
return val->count - 1;
}
static inline long atomic_postdec(atomic_t *val)
{
atomic_dec(val);
return val->count + 1;
}
static inline long atomic_preinc(atomic_t *val)
{
atomic_inc(val);
return val->count;
}
static inline long atomic_predec(atomic_t *val)
{
atomic_dec(val);
return val->count;
}
#endif

/tags/0.2.0/kernel/arch/ppc64/include/boot/boot.h
0,0 → 1,83
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_BOOT_H__
#define __ppc64_BOOT_H__
#define BOOT_OFFSET 0x4000
/* Temporary stack size for boot process */
#define TEMP_STACK_SIZE 0x100
#define TASKMAP_MAX_RECORDS 32
#define MEMMAP_MAX_RECORDS 32
#ifndef __ASM__
#include <arch/types.h>
typedef struct {
__address addr;
__u64 size;
} utask_t;
typedef struct {
__u32 count;
utask_t tasks[TASKMAP_MAX_RECORDS];
} taskmap_t;
typedef struct {
__address start;
__u64 size;
} memzone_t;
typedef struct {
__u64 total;
__u32 count;
memzone_t zones[MEMMAP_MAX_RECORDS];
} memmap_t;
typedef struct {
__address addr;
unsigned int width;
unsigned int height;
unsigned int bpp;
unsigned int scanline;
} screen_t;
typedef struct {
taskmap_t taskmap;
memmap_t memmap;
screen_t screen;
} bootinfo_t;
extern bootinfo_t bootinfo;
#endif
#endif

/tags/0.2.0/kernel/arch/ppc64/include/barrier.h
0,0 → 1,39
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_BARRIER_H__
#define __ppc64_BARRIER_H__
#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory")
#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory")
#define memory_barrier() asm volatile ("sync" ::: "memory")
#define read_barrier() asm volatile ("sync" ::: "memory")
#define write_barrier() asm volatile ("eieio" ::: "memory")
#endif

/tags/0.2.0/kernel/arch/ppc64/include/interrupt.h
0,0 → 1,43
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_INTERRUPT_H__
#define __ppc64_INTERRUPT_H__
#include <arch/exception.h>
#define IRQ_COUNT 1
#define IVT_ITEMS 15
#define INT_OFFSET 0
#define VECTOR_DECREMENTER 10
extern void start_decrementer(void);
extern void interrupt_init(void);
#endif

/tags/0.2.0/kernel/arch/ppc64/include/context_offset.h
0,0 → 1,45
/* This file is automatically generated by gencontext.c. */
/* struct context */
#define OFFSET_SP 0x0
#define OFFSET_PC 0x8
#define OFFSET_R2 0x10
#define OFFSET_R13 0x18
#define OFFSET_R14 0x20
#define OFFSET_R15 0x28
#define OFFSET_R16 0x30
#define OFFSET_R17 0x38
#define OFFSET_R18 0x40
#define OFFSET_R19 0x48
#define OFFSET_R20 0x50
#define OFFSET_R21 0x58
#define OFFSET_R22 0x60
#define OFFSET_R23 0x68
#define OFFSET_R24 0x70
#define OFFSET_R25 0x78
#define OFFSET_R26 0x80
#define OFFSET_R27 0x88
#define OFFSET_R28 0x90
#define OFFSET_R29 0x98
#define OFFSET_R30 0xa0
#define OFFSET_R31 0xa8
#define OFFSET_CR 0xb0
#define OFFSET_FR14 0x0
#define OFFSET_FR15 0x8
#define OFFSET_FR16 0x10
#define OFFSET_FR17 0x18
#define OFFSET_FR18 0x20
#define OFFSET_FR19 0x28
#define OFFSET_FR20 0x30
#define OFFSET_FR21 0x38
#define OFFSET_FR22 0x40
#define OFFSET_FR23 0x48
#define OFFSET_FR24 0x50
#define OFFSET_FR25 0x58
#define OFFSET_FR26 0x60
#define OFFSET_FR27 0x68
#define OFFSET_FR28 0x70
#define OFFSET_FR29 0x78
#define OFFSET_FR30 0x80
#define OFFSET_FR31 0x88
#define OFFSET_FPSCR 0x90

/tags/0.2.0/kernel/arch/ppc64/include/fpu_context.h
0,0 → 1,58
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_FPU_CONTEXT_H__
#define __ppc64_FPU_CONTEXT_H__
#ifndef __ppc64_TYPES_H__
# include <arch/types.h>
#endif
struct fpu_context {
__u64 fr14;
__u64 fr15;
__u64 fr16;
__u64 fr17;
__u64 fr18;
__u64 fr19;
__u64 fr20;
__u64 fr21;
__u64 fr22;
__u64 fr23;
__u64 fr24;
__u64 fr25;
__u64 fr26;
__u64 fr27;
__u64 fr28;
__u64 fr29;
__u64 fr30;
__u64 fr31;
__u32 fpscr;
} __attribute__ ((packed));
#endif

/tags/0.2.0/kernel/arch/ppc64/include/memstr.h
0,0 → 1,39
/*
* Copyright (C) 2005 Sergey Bondari
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_MEMSTR_H__
#define __ppc64_MEMSTR_H__
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt))
extern void memsetw(__address dst, size_t cnt, __u16 x);
extern void memsetb(__address dst, size_t cnt, __u8 x);
extern int memcmp(__address src, __address dst, int cnt);
#endif

/tags/0.2.0/kernel/arch/ppc64/include/arg.h
0,0 → 1,34
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_ARG_H__
#define __ppc64_ARG_H__
#include <stdarg.h>
#endif

/tags/0.2.0/kernel/arch/ppc64/include/arch.h
0,0 → 1,32
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_ARCH_H__
#define __ppc64_ARCH_H__
#endif

/tags/0.2.0/kernel/arch/ppc64/include/faddr.h
0,0 → 1,36
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_FADDR_H__
#define __ppc64_FADDR_H__
#include <arch/types.h>
#define FADDR(fptr) ((__address) (fptr))
#endif

/tags/0.2.0/kernel/arch/ppc64/include/context.h
0,0 → 1,68
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_CONTEXT_H__
#define __ppc64_CONTEXT_H__
#ifndef __ppc64_TYPES_H__
# include <arch/types.h>
#endif
#define SP_DELTA 16
struct context {
__address sp;
__address pc;
__u64 r2;
__u64 r13;
__u64 r14;
__u64 r15;
__u64 r16;
__u64 r17;
__u64 r18;
__u64 r19;
__u64 r20;
__u64 r21;
__u64 r22;
__u64 r23;
__u64 r24;
__u64 r25;
__u64 r26;
__u64 r27;
__u64 r28;
__u64 r29;
__u64 r30;
__u64 r31;
__u64 cr;
ipl_t ipl;
} __attribute__ ((packed));
#endif

/tags/0.2.0/kernel/arch/ppc64/include/debug.h
0,0 → 1,32
/*
* Copyright (C) 2005
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_DEBUG_H__
#define __ppc64_DEBUG_H__
#endif

/tags/0.2.0/kernel/arch/ppc64/include/cpu.h
0,0 → 1,39
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ppc64_CPU_H__
#define __ppc64_CPU_H__
#include <typedefs.h>
struct cpu_arch {
int version;
int revision;
};
#endif

/tags/0.2.0/kernel/arch/ppc64/src/ppc64.c
0,0 → 1,105
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <arch/boot/boot.h>
#include <arch/mm/memory_init.h>
#include <arch/interrupt.h>
#include <genarch/fb/fb.h>
#include <userspace.h>
#include <proc/uarg.h>
#include <console/console.h>
bootinfo_t bootinfo;
void arch_pre_main(void)
{
/* Setup usermode */
init.cnt = bootinfo.taskmap.count;
__u32 i;
for (i = 0; i < bootinfo.taskmap.count; i++) {
init.tasks[i].addr = PA2KA(bootinfo.taskmap.tasks[i].addr);
init.tasks[i].size = bootinfo.taskmap.tasks[i].size;
}
}
void arch_pre_mm_init(void)
{
/* Initialize dispatch table */
interrupt_init();
/* Start decrementer */
start_decrementer();
}
void arch_post_mm_init(void)
{
if (config.cpu_active == 1) {
fb_init(bootinfo.screen.addr, bootinfo.screen.width, bootinfo.screen.height, bootinfo.screen.bpp, bootinfo.screen.scanline);
/* Merge all zones to 1 big zone */
zone_merge_all();
}
}
void arch_pre_smp_init(void)
{
memory_print_map();
}
void arch_post_smp_init(void)
{
}
void calibrate_delay_loop(void)
{
}
void userspace(uspace_arg_t *kernel_uarg)
{
userspace_asm((__address) kernel_uarg->uspace_uarg, (__address) kernel_uarg->uspace_stack + THREAD_STACK_SIZE - SP_DELTA, (__address) kernel_uarg->uspace_entry);
/* Unreachable */
for (;;)
;
}
/** Acquire console back for kernel
*
*/
void arch_grab_console(void)
{
}
/** Return console to userspace
*
*/
void arch_release_console(void)
{
}

/tags/0.2.0/kernel/arch/ppc64/src/mm/page.c
0,0 → 1,298
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/page.h>
#include <genarch/mm/page_pt.h>
#include <arch/mm/frame.h>
#include <arch/asm.h>
#include <mm/frame.h>
#include <mm/page.h>
#include <mm/as.h>
#include <arch.h>
#include <arch/types.h>
#include <arch/exception.h>
#include <align.h>
#include <config.h>
#include <print.h>
#include <symtab.h>
static phte_t *phte;
/** Try to find PTE for faulting address
*
* Try to find PTE for faulting address.
* The as->lock must be held on entry to this function
* if lock is true.
*
* @param as Address space.
* @param lock Lock/unlock the address space.
* @param badvaddr Faulting virtual address.
* @param access Access mode that caused the fault.
* @param istate Pointer to interrupted state.
* @param pfrc Pointer to variable where as_page_fault() return code will be stored.
* @return PTE on success, NULL otherwise.
*
*/
static pte_t *find_mapping_and_check(as_t *as, bool lock, __address badvaddr, int access,
istate_t *istate, int *pfcr)
{
/*
* Check if the mapping exists in page tables.
*/
pte_t *pte = page_mapping_find(as, badvaddr);
if ((pte) && (pte->p)) {
/*
* Mapping found in page tables.
* Immediately succeed.
*/
return pte;
} else {
int rc;
/*
* Mapping not found in page tables.
* Resort to higher-level page fault handler.
*/
page_table_unlock(as, lock);
switch (rc = as_page_fault(badvaddr, access, istate)) {
case AS_PF_OK:
/*
* The higher-level page fault handler succeeded,
* The mapping ought to be in place.
*/
page_table_lock(as, lock);
pte = page_mapping_find(as, badvaddr);
ASSERT((pte) && (pte->p));
return pte;
case AS_PF_DEFER:
page_table_lock(as, lock);
*pfcr = rc;
return NULL;
case AS_PF_FAULT:
page_table_lock(as, lock);
printf("Page fault.\n");
*pfcr = rc;
return NULL;
default:
panic("unexpected rc (%d)\n", rc);
}
}
}
static void pht_refill_fail(__address badvaddr, istate_t *istate)
{
char *symbol = "";
char *sym2 = "";
char *s = get_symtab_entry(istate->pc);
if (s)
symbol = s;
s = get_symtab_entry(istate->lr);
if (s)
sym2 = s;
panic("%p: PHT Refill Exception at %p (%s<-%s)\n", badvaddr, istate->pc, symbol, sym2);
}
static void pht_insert(const __address vaddr, const pfn_t pfn)
{
__u32 page = (vaddr >> 12) & 0xffff;
__u32 api = (vaddr >> 22) & 0x3f;
__u32 vsid;
asm volatile (
"mfsrin %0, %1\n"
: "=r" (vsid)
: "r" (vaddr)
);
/* Primary hash (xor) */
__u32 h = 0;
__u32 hash = vsid ^ page;
__u32 base = (hash & 0x3ff) << 3;
__u32 i;
bool found = false;
/* Find unused or colliding
PTE in PTEG */
for (i = 0; i < 8; i++) {
if ((!phte[base + i].v) || ((phte[base + i].vsid == vsid) && (phte[base + i].api == api))) {
found = true;
break;
}
}
if (!found) {
/* Secondary hash (not) */
__u32 base2 = (~hash & 0x3ff) << 3;
/* Find unused or colliding
PTE in PTEG */
for (i = 0; i < 8; i++) {
if ((!phte[base2 + i].v) || ((phte[base2 + i].vsid == vsid) && (phte[base2 + i].api == api))) {
found = true;
base = base2;
h = 1;
break;
}
}
if (!found) {
// TODO: A/C precedence groups
i = page % 8;
}
}
phte[base + i].v = 1;
phte[base + i].vsid = vsid;
phte[base + i].h = h;
phte[base + i].api = api;
phte[base + i].rpn = pfn;
phte[base + i].r = 0;
phte[base + i].c = 0;
phte[base + i].pp = 2; // FIXME
}
/** Process Instruction/Data Storage Interrupt
*
* @param data True if Data Storage Interrupt.
* @param istate Interrupted register context.
*
*/
void pht_refill(bool data, istate_t *istate)
{
__address badvaddr;
pte_t *pte;
int pfcr;
as_t *as;
bool lock;
if (AS == NULL) {
as = AS_KERNEL;
lock = false;
} else {
as = AS;
lock = true;
}
if (data) {
asm volatile (
"mfdar %0\n"
: "=r" (badvaddr)
);
} else
badvaddr = istate->pc;
page_table_lock(as, lock);
pte = find_mapping_and_check(as, lock, badvaddr, PF_ACCESS_READ /* FIXME */, istate, &pfcr);
if (!pte) {
switch (pfcr) {
case AS_PF_FAULT:
goto fail;
break;
case AS_PF_DEFER:
/*
* The page fault came during copy_from_uspace()
* or copy_to_uspace().
*/
page_table_unlock(as, lock);
return;
default:
panic("Unexpected pfrc (%d)\n", pfcr);
}
}
pte->a = 1; /* Record access to PTE */
pht_insert(badvaddr, pte->pfn);
page_table_unlock(as, lock);
return;
fail:
page_table_unlock(as, lock);
pht_refill_fail(badvaddr, istate);
}
void pht_init(void)
{
memsetb((__address) phte, 1 << PHT_BITS, 0);
}
void page_arch_init(void)
{
if (config.cpu_active == 1) {
page_mapping_operations = &pt_mapping_operations;
__address cur;
int flags;
/* Frames below 128 MB are mapped using BAT,
map rest of the physical memory */
for (cur = 128 << 20; cur < last_frame; cur += FRAME_SIZE) {
flags = PAGE_CACHEABLE;
if ((PA2KA(cur) >= config.base) && (PA2KA(cur) < config.base + config.kernel_size))
flags |= PAGE_GLOBAL;
page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags);
}
/* Allocate page hash table */
phte_t *physical_phte = (phte_t *) PFN2ADDR(frame_alloc(PHT_ORDER, FRAME_KA | FRAME_PANIC));
phte = (phte_t *) PA2KA((__address) physical_phte);
ASSERT((__address) physical_phte % (1 << PHT_BITS) == 0);
pht_init();
asm volatile (
"mtsdr1 %0\n"
:
: "r" ((__address) physical_phte)
);
}
}
__address hw_map(__address physaddr, size_t size)
{
if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
panic("Unable to map physical memory %p (%d bytes)", physaddr, size)
__address virtaddr = PA2KA(last_frame);
pfn_t i;
for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++)
page_mapping_insert(AS_KERNEL, virtaddr + PFN2ADDR(i), physaddr + PFN2ADDR(i), PAGE_NOT_CACHEABLE);
last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE);
return virtaddr;
}

/tags/0.2.0/kernel/arch/ppc64/src/mm/tlb.c
0,0 → 1,77
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <mm/tlb.h>
/** Initialize Page Hash Table.
*
* Setup the Page Hash Table with no entries.
*
*/
void tlb_arch_init(void)
{
tlb_invalidate_all();
}
void tlb_invalidate_all(void)
{
asm volatile (
"tlbia\n"
"tlbsync\n"
);
}
/** Invalidate all entries in TLB that belong to specified address space.
*
* @param asid This parameter is ignored as the architecture doesn't support it.
*/
void tlb_invalidate_asid(asid_t asid)
{
tlb_invalidate_all();
}
/** Invalidate TLB entries for specified page range belonging to specified address space.
*
* @param asid This parameter is ignored as the architecture doesn't support it.
* @param page Address of the first page whose entry is to be invalidated.
* @param cnt Number of entries to invalidate.
*/
void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)
{
tlb_invalidate_all();
}
/** Print contents of Page Hash Table. */
void tlb_print(void)
{
}

/tags/0.2.0/kernel/arch/ppc64/src/mm/memory_init.c
0,0 → 1,47
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/boot/boot.h>
#include <arch/mm/memory_init.h>
#include <typedefs.h>
#include <print.h>
size_t get_memory_size(void)
{
return bootinfo.memmap.total;
}
void memory_print_map(void)
{
count_t i;
for (i = 0; i < bootinfo.memmap.count; i++)
printf("base: %#x size: %#x\n", bootinfo.memmap.zones[i].start, bootinfo.memmap.zones[i].size);
}

/tags/0.2.0/kernel/arch/ppc64/src/mm/frame.c
0,0 → 1,62
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/boot/boot.h>
#include <arch/mm/frame.h>
#include <arch/mm/memory_init.h>
#include <mm/frame.h>
#include <align.h>
#include <macros.h>
__address last_frame = 0;
void frame_arch_init(void)
{
pfn_t minconf = 2;
count_t i;
pfn_t start, conf;
size_t size;
for (i = 0; i < bootinfo.memmap.count; i++) {
start = ADDR2PFN(ALIGN_UP(bootinfo.memmap.zones[i].start, FRAME_SIZE));
size = SIZE2FRAMES(ALIGN_DOWN(bootinfo.memmap.zones[i].size, FRAME_SIZE));
if ((minconf < start) || (minconf >= start + size))
conf = start;
else
conf = minconf;
zone_create(start, size, conf, 0);
if (last_frame < ALIGN_UP(bootinfo.memmap.zones[i].start + bootinfo.memmap.zones[i].size, FRAME_SIZE))
last_frame = ALIGN_UP(bootinfo.memmap.zones[i].start + bootinfo.memmap.zones[i].size, FRAME_SIZE);
}
/* First is exception vector, second is 'implementation specific', third and fourth is reserved */
frame_mark_unavailable(0, 4);
}

/tags/0.2.0/kernel/arch/ppc64/src/mm/as.c
0,0 → 1,36
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/as.h>
#include <genarch/mm/as_pt.h>
/** Architecture dependent address space init. */
void as_arch_init(void)
{
as_operations = &as_pt_operations;
}

/tags/0.2.0/kernel/arch/ppc64/src/exception.S
0,0 → 1,237
#
# Copyright (C) 2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/regname.h>
#include <arch/mm/page.h>
.section K_UNMAPPED_TEXT_START, "ax"
.macro CONTEXT_STORE
# save R12 in SPRG1, backup CR in R12
# save SP in SPRG2
mtsprg1 r12
mfcr r12
mtsprg2 sp
# check whether SP is in kernel
andis. sp, sp, 0x8000
bne 1f
# stack is in user-space
mfsprg0 sp
b 2f
1:
# stack is in kernel
mfsprg2 sp
subis sp, sp, 0x8000
2:
subi sp, sp, 160
stw r0, 8(sp)
stw r2, 12(sp)
stw r3, 16(sp)
stw r4, 20(sp)
stw r5, 24(sp)
stw r6, 28(sp)
stw r7, 32(sp)
stw r8, 36(sp)
stw r9, 40(sp)
stw r10, 44(sp)
stw r11, 48(sp)
stw r13, 52(sp)
stw r14, 56(sp)
stw r15, 60(sp)
stw r16, 64(sp)
stw r17, 68(sp)
stw r18, 72(sp)
stw r19, 76(sp)
stw r20, 80(sp)
stw r21, 84(sp)
stw r22, 88(sp)
stw r23, 92(sp)
stw r24, 96(sp)
stw r25, 100(sp)
stw r26, 104(sp)
stw r27, 108(sp)
stw r28, 112(sp)
stw r29, 116(sp)
stw r30, 120(sp)
stw r31, 124(sp)
stw r12, 128(sp)
mfsrr0 r12
stw r12, 132(sp)
mfsrr1 r12
stw r12, 136(sp)
mflr r12
stw r12, 140(sp)
mfctr r12
stw r12, 144(sp)
mfxer r12
stw r12, 148(sp)
mfsprg1 r12
stw r12, 152(sp)
mfsprg2 r12
stw r12, 156(sp)
.endm
.org 0x060
jump_to_kernel:
lis r12, iret@ha
addi r12, r12, iret@l
mtlr r12
mfmsr r12
ori r12, r12, (msr_ir | msr_dr)@l
mtsrr1 r12
addis sp, sp, 0x8000
mr r4, sp
addi r4, r4, 8
rfi
jump_to_kernel_syscall:
lis r12, syscall_handler@ha
addi r12, r12, syscall_handler@l
mtsrr0 r12
lis r12, iret_syscall@ha
addi r12, r12, iret_syscall@l
mtlr r12
mfmsr r12
ori r12, r12, (msr_ir | msr_dr)@l
mtsrr1 r12
addis sp, sp, 0x8000
rfi
.org 0x100
.global exc_system_reset
exc_system_reset:
b exc_system_reset
.org 0x200
.global exc_machine_check
exc_machine_check:
b exc_machine_check
.org 0x300
.global exc_data_storage
exc_data_storage:
CONTEXT_STORE
lis r12, pht_refill@ha
addi r12, r12, pht_refill@l
mtsrr0 r12
li r3, 1
b jump_to_kernel
.org 0x400
.global exc_instruction_storage
exc_instruction_storage:
CONTEXT_STORE
lis r12, pht_refill@ha
addi r12, r12, pht_refill@l
mtsrr0 r12
li r3, 0
b jump_to_kernel
.org 0x500
.global exc_external
exc_external:
b exc_external
.org 0x600
.global exc_alignment
exc_alignment:
b exc_alignment
.org 0x700
.global exc_program
exc_program:
b exc_program
.org 0x800
.global exc_fp_unavailable
exc_fp_unavailable:
b exc_fp_unavailable
.org 0x900
.global exc_decrementer
exc_decrementer:
CONTEXT_STORE
lis r12, exc_dispatch@ha
addi r12, r12, exc_dispatch@l
mtsrr0 r12
li r3, 10
b jump_to_kernel
.org 0xa00
.global exc_reserved0
exc_reserved0:
b exc_reserved0
.org 0xb00
.global exc_reserved1
exc_reserved1:
b exc_reserved1
.org 0xc00
.global exc_syscall
exc_syscall:
CONTEXT_STORE
b jump_to_kernel_syscall
.org 0xd00
.global exc_trace
exc_trace:
b exc_trace

/tags/0.2.0/kernel/arch/ppc64/src/asm.S
0,0 → 1,311
#
# Copyright (C) 2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/regname.h>
.text
.global userspace_asm
.global iret
.global iret_syscall
.global memsetb
.global memcpy
.global memcpy_from_uspace
.global memcpy_to_uspace
.global memcpy_from_uspace_failover_address
.global memcpy_to_uspace_failover_address
userspace_asm:
# r3 = uspace_uarg
# r4 = stack
# r5 = entry
# disable interrupts
mfmsr r31
rlwinm r31, r31, 0, 17, 15
mtmsr r31
# set entry point
mtsrr0 r5
# set problem state, enable interrupts
ori r31, r31, msr_pr
ori r31, r31, msr_ee
mtsrr1 r31
# set stack
mr sp, r4
# jump to userspace
rfi
iret:
# disable interrupts
mfmsr r31
rlwinm r31, r31, 0, 17, 15
mtmsr r31
lwz r0, 8(sp)
lwz r2, 12(sp)
lwz r3, 16(sp)
lwz r4, 20(sp)
lwz r5, 24(sp)
lwz r6, 28(sp)
lwz r7, 32(sp)
lwz r8, 36(sp)
lwz r9, 40(sp)
lwz r10, 44(sp)
lwz r11, 48(sp)
lwz r13, 52(sp)
lwz r14, 56(sp)
lwz r15, 60(sp)
lwz r16, 64(sp)
lwz r17, 68(sp)
lwz r18, 72(sp)
lwz r19, 76(sp)
lwz r20, 80(sp)
lwz r21, 84(sp)
lwz r22, 88(sp)
lwz r23, 92(sp)
lwz r24, 96(sp)
lwz r25, 100(sp)
lwz r26, 104(sp)
lwz r27, 108(sp)
lwz r28, 112(sp)
lwz r29, 116(sp)
lwz r30, 120(sp)
lwz r31, 124(sp)
lwz r12, 128(sp)
mtcr r12
lwz r12, 132(sp)
mtsrr0 r12
lwz r12, 136(sp)
mtsrr1 r12
lwz r12, 140(sp)
mtlr r12
lwz r12, 144(sp)
mtctr r12
lwz r12, 148(sp)
mtxer r12
lwz r12, 152(sp)
lwz sp, 156(sp)
rfi
iret_syscall:
# reset decrementer
li r31, 1000
mtdec r31
# disable interrupts
mfmsr r31
rlwinm r31, r31, 0, 17, 15
mtmsr r31
lwz r0, 8(sp)
lwz r2, 12(sp)
lwz r4, 20(sp)
lwz r5, 24(sp)
lwz r6, 28(sp)
lwz r7, 32(sp)
lwz r8, 36(sp)
lwz r9, 40(sp)
lwz r10, 44(sp)
lwz r11, 48(sp)
lwz r13, 52(sp)
lwz r14, 56(sp)
lwz r15, 60(sp)
lwz r16, 64(sp)
lwz r17, 68(sp)
lwz r18, 72(sp)
lwz r19, 76(sp)
lwz r20, 80(sp)
lwz r21, 84(sp)
lwz r22, 88(sp)
lwz r23, 92(sp)
lwz r24, 96(sp)
lwz r25, 100(sp)
lwz r26, 104(sp)
lwz r27, 108(sp)
lwz r28, 112(sp)
lwz r29, 116(sp)
lwz r30, 120(sp)
lwz r31, 124(sp)
lwz r12, 128(sp)
mtcr r12
lwz r12, 132(sp)
mtsrr0 r12
lwz r12, 136(sp)
mtsrr1 r12
lwz r12, 140(sp)
mtlr r12
lwz r12, 144(sp)
mtctr r12
lwz r12, 148(sp)
mtxer r12
lwz r12, 152(sp)
lwz sp, 156(sp)
rfi
memsetb:
rlwimi r5, r5, 8, 16, 23
rlwimi r5, r5, 16, 0, 15
addi r14, r3, -4
cmplwi 0, r4, 4
blt 7f
stwu r5, 4(r14)
beqlr
andi. r15, r14, 3
add r4, r15, r4
subf r14, r15, r14
srwi r15, r4, 2
mtctr r15
bdz 6f
1:
stwu r5, 4(r14)
bdnz 1b
6:
andi. r4, r4, 3
7:
cmpwi 0, r4, 0
beqlr
mtctr r4
addi r6, r6, 3
8:
stbu r5, 1(r14)
bdnz 8b
blr
memcpy:
memcpy_from_uspace:
memcpy_to_uspace:
srwi. r7, r5, 3
addi r6, r3, -4
addi r4, r4, -4
beq 2f
andi. r0, r6, 3
mtctr r7
bne 5f
1:
lwz r7, 4(r4)
lwzu r8, 8(r4)
stw r7, 4(r6)
stwu r8, 8(r6)
bdnz 1b
andi. r5, r5, 7
2:
cmplwi 0, r5, 4
blt 3f
lwzu r0, 4(r4)
addi r5, r5, -4
stwu r0, 4(r6)
3:
cmpwi 0, r5, 0
beqlr
mtctr r5
addi r4, r4, 3
addi r6, r6, 3
4:
lbzu r0, 1(r4)
stbu r0, 1(r6)
bdnz 4b
blr
5:
subfic r0, r0, 4
mtctr r0
6:
lbz r7, 4(r4)
addi r4, r4, 1
stb r7, 4(r6)
addi r6, r6, 1
bdnz 6b
subf r5, r0, r5
rlwinm. r7, r5, 32-3, 3, 31
beq 2b
mtctr r7
b 1b
memcpy_from_uspace_failover_address:
memcpy_to_uspace_failover_address:
b memcpy_from_uspace_failover_address

/tags/0.2.0/kernel/arch/ppc64/src/boot/boot.S
0,0 → 1,81
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/regname.h>
#include <arch/boot/boot.h>
.section K_TEXT_START, "ax"
.global kernel_image_start
kernel_image_start:
# load temporal kernel stack
lis sp, kernel_stack@ha
addi sp, sp, kernel_stack@l
# set kernel stack for interrupt handling
mr r31, sp
subis r31, r31, 0x8000
mtsprg0 r31
# r3 contains physical address of bootinfo_t
# r4 contains size of bootinfo_t
addis r3, r3, 0x8000
lis r31, bootinfo@ha
addi r31, r31, bootinfo@l # r31 = bootinfo
cmpwi r4, 0
beq bootinfo_end
bootinfo_loop:
lwz r30, 0(r3)
stw r30, 0(r31)
addi r3, r3, 4
addi r31, r31, 4
subi r4, r4, 4
cmpwi r4, 0
bgt bootinfo_loop
bootinfo_end:
bl arch_pre_main
b main_bsp
.section K_DATA_START, "aw", @progbits
.align 12
kernel_stack_bottom:
.space TEMP_STACK_SIZE
kernel_stack:

/tags/0.2.0/kernel/arch/ppc64/src/proc/scheduler.c
0,0 → 1,54
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/mm/page.h>
#include <arch/boot/boot.h>
#include <proc/scheduler.h>
#include <proc/thread.h>
#include <arch.h>
/** Perform ppc64 specific tasks needed before the new task is run. */
void before_task_runs_arch(void)
{
}
/** Perform ppc64 specific tasks needed before the new thread is scheduled. */
void before_thread_runs_arch(void)
{
pht_init();
tlb_invalidate_all();
asm volatile (
"mtsprg0 %0\n"
:
: "r" (KA2PA(&THREAD->kstack[THREAD_STACK_SIZE - SP_DELTA]))
);
}
void after_thread_ran_arch(void)
{
}

/tags/0.2.0/kernel/arch/ppc64/src/dummy.s
0,0 → 1,38
#
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
.text
.global asm_delay_loop
.global sys_tls_set
sys_tls_set:
b sys_tls_set
asm_delay_loop:
blr

/tags/0.2.0/kernel/arch/ppc64/src/interrupt.c
0,0 → 1,66
/*
* Copyright (C) 2006 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <interrupt.h>
#include <arch/interrupt.h>
#include <arch/types.h>
#include <arch.h>
#include <time/clock.h>
#include <ipc/sysipc.h>
void start_decrementer(void)
{
asm volatile (
"mtdec %0\n"
:
: "r" (1000)
);
}
static void exception_decrementer(int n, istate_t *istate)
{
clock();
start_decrementer();
}
/* Initialize basic tables for exception dispatching */
void interrupt_init(void)
{
exc_register(VECTOR_DECREMENTER, "timer", exception_decrementer);
}
/* Reregister irq to be IPC-ready */
void irq_ipc_bind_arch(__native irq)
{
panic("not implemented\n");
/* TODO */
}

/tags/0.2.0/kernel/arch/ppc64/src/ddi/ddi.c
0,0 → 1,47
/*
* Copyright (C) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <ddi/ddi.h>
#include <proc/task.h>
#include <arch/types.h>
#include <typedefs.h>
/** Enable I/O space range for task.
*
* Interrupts are disabled and task is locked.
*
* @param task Task.
* @param ioaddr Startign I/O space address.
* @param size Size of the enabled I/O range.
*
* @return 0 on success or an error code from errno.h.
*/
int ddi_iospace_enable_arch(task_t *task, __address ioaddr, size_t size)
{
return 0;
}

/tags/0.2.0/kernel/arch/ppc64/src/fpu_context.S
0,0 → 1,105
#
# Copyright (C) 2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/regname.h>
#include <arch/context_offset.h>
.text
.global fpu_context_save
.global fpu_context_restore
.global fpu_init
.global fpu_enable
.global fpu_disable
.macro FPU_CONTEXT_STORE r
stfd fr14, OFFSET_FR14(\r)
stfd fr15, OFFSET_FR15(\r)
stfd fr16, OFFSET_FR16(\r)
stfd fr17, OFFSET_FR17(\r)
stfd fr18, OFFSET_FR18(\r)
stfd fr19, OFFSET_FR19(\r)
stfd fr20, OFFSET_FR20(\r)
stfd fr21, OFFSET_FR21(\r)
stfd fr22, OFFSET_FR22(\r)
stfd fr23, OFFSET_FR23(\r)
stfd fr24, OFFSET_FR24(\r)
stfd fr25, OFFSET_FR25(\r)
stfd fr26, OFFSET_FR26(\r)
stfd fr27, OFFSET_FR27(\r)
stfd fr28, OFFSET_FR28(\r)
stfd fr29, OFFSET_FR29(\r)
stfd fr30, OFFSET_FR30(\r)
stfd fr31, OFFSET_FR31(\r)
.endm
.macro FPU_CONTEXT_LOAD r
lfd fr14, OFFSET_FR14(\r)
lfd fr15, OFFSET_FR15(\r)
lfd fr16, OFFSET_FR16(\r)
lfd fr17, OFFSET_FR17(\r)
lfd fr18, OFFSET_FR18(\r)
lfd fr19, OFFSET_FR19(\r)
lfd fr20, OFFSET_FR20(\r)
lfd fr21, OFFSET_FR21(\r)
lfd fr22, OFFSET_FR22(\r)
lfd fr23, OFFSET_FR23(\r)
lfd fr24, OFFSET_FR24(\r)
lfd fr25, OFFSET_FR25(\r)
lfd fr26, OFFSET_FR26(\r)
lfd fr27, OFFSET_FR27(\r)
lfd fr28, OFFSET_FR28(\r)
lfd fr29, OFFSET_FR29(\r)
lfd fr30, OFFSET_FR30(\r)
lfd fr31, OFFSET_FR31(\r)
.endm
fpu_context_save:
// FPU_CONTEXT_STORE r3
//
// mffs fr0
// stfd fr0, OFFSET_FPSCR(r3)
blr
fpu_context_restore:
// FPU_CONTEXT_LOAD r3
//
// lfd fr0, OFFSET_FPSCR(r3)
// mtfsf 7, fr0
blr
fpu_init:
blr
fpu_enable:
blr
fpu_disable:
blr

/tags/0.2.0/kernel/arch/ppc64/src/context.S
0,0 → 1,109
#
# Copyright (C) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/regname.h>
#include <arch/context_offset.h>
.text
.global context_save_arch
.global context_restore_arch
.macro CONTEXT_STORE r
stw sp, OFFSET_SP(\r)
stw r2, OFFSET_R2(\r)
stw r13, OFFSET_R13(\r)
stw r14, OFFSET_R14(\r)
stw r15, OFFSET_R15(\r)
stw r16, OFFSET_R16(\r)
stw r17, OFFSET_R17(\r)
stw r18, OFFSET_R18(\r)
stw r19, OFFSET_R19(\r)
stw r20, OFFSET_R20(\r)
stw r21, OFFSET_R21(\r)
stw r22, OFFSET_R22(\r)
stw r23, OFFSET_R23(\r)
stw r24, OFFSET_R24(\r)
stw r25, OFFSET_R25(\r)
stw r26, OFFSET_R26(\r)
stw r27, OFFSET_R27(\r)
stw r28, OFFSET_R28(\r)
stw r29, OFFSET_R29(\r)
stw r30, OFFSET_R30(\r)
stw r31, OFFSET_R31(\r)
.endm
.macro CONTEXT_LOAD r
lwz sp, OFFSET_SP(\r)
lwz r2, OFFSET_R2(\r)
lwz r13, OFFSET_R13(\r)
lwz r14, OFFSET_R14(\r)
lwz r15, OFFSET_R15(\r)
lwz r16, OFFSET_R16(\r)
lwz r17, OFFSET_R17(\r)
lwz r18, OFFSET_R18(\r)
lwz r19, OFFSET_R19(\r)
lwz r20, OFFSET_R20(\r)
lwz r21, OFFSET_R21(\r)
lwz r22, OFFSET_R22(\r)
lwz r23, OFFSET_R23(\r)
lwz r24, OFFSET_R24(\r)
lwz r25, OFFSET_R25(\r)
lwz r26, OFFSET_R26(\r)
lwz r27, OFFSET_R27(\r)
lwz r28, OFFSET_R28(\r)
lwz r29, OFFSET_R29(\r)
lwz r30, OFFSET_R30(\r)
lwz r31, OFFSET_R31(\r)
.endm
context_save_arch:
CONTEXT_STORE r3
mflr r4
stw r4, OFFSET_PC(r3)
mfcr r4
stw r4, OFFSET_CR(r3)
# context_save returns 1
li r3, 1
blr
context_restore_arch:
CONTEXT_LOAD r3
lwz r4, OFFSET_CR(r3)
mtcr r4
lwz r4, OFFSET_PC(r3)
mtlr r4
# context_restore returns 0
li r3, 0
blr

/tags/0.2.0/kernel/arch/ppc64/src/debug/panic.s
0,0 → 1,38
#
# Copyright (C) 2005 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#include <arch/asm/macro.h>
.text
.global panic_printf
panic_printf:
lis %r14, halt@ha
addi %r14, %r14, halt@l
mtlr %r14 # fake stack to make printf return to halt
b printf

/tags/0.2.0/kernel/arch/ppc64/src/cpu/cpu.c
0,0 → 1,54
/*
* Copyright (C) 2005 Martin Decky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch/cpu.h>
#include <arch/cpuid.h>
#include <cpu.h>
#include <arch.h>
#include <typedefs.h>
#include <print.h>
void cpu_arch_init(void)
{
}
void cpu_identify(void)
{
cpu_info_t info;
cpu_version(&info);
CPU->arch.version = info.version;
CPU->arch.revision = info.revision;
}
void cpu_print_report(cpu_t *m)
{
printf("cpu%d: version=%d, revision=%d\n", m->id, m->arch.version, m->arch.revision);
}

/tags/0.2.0/kernel/arch/ppc64/Makefile.inc
0,0 → 1,75
#
# Copyright (C) 2006 Martin Decky
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
## Toolchain configuration
#
BFD_NAME = elf64-powerpc
BFD_ARCH = powerpc:common64
BFD = binary
TARGET = ppc64-linux-gnu
TOOLCHAIN_DIR = /usr/local/ppc64/bin
## Make some default assumptions
#
CFLAGS += -mcpu=powerpc64 -msoft-float -m64
AFLAGS += -a64
LFLAGS += -no-check-sections -N
DEFS += -D__64_BITS__
## Own configuration directives
#
CONFIG_FB = y
## Compile with hierarchical page tables support.
#
CONFIG_PAGE_PT = y
DEFS += -DCONFIG_PAGE_PT
ARCH_SOURCES = \
arch/$(ARCH)/src/context.S \
arch/$(ARCH)/src/debug/panic.s \
arch/$(ARCH)/src/fpu_context.S \
arch/$(ARCH)/src/boot/boot.S \
arch/$(ARCH)/src/ppc64.c \
arch/$(ARCH)/src/dummy.s \
arch/$(ARCH)/src/exception.S \
arch/$(ARCH)/src/interrupt.c \
arch/$(ARCH)/src/asm.S \
arch/$(ARCH)/src/cpu/cpu.c \
arch/$(ARCH)/src/proc/scheduler.c \
arch/$(ARCH)/src/ddi/ddi.c \
arch/$(ARCH)/src/mm/as.c \
arch/$(ARCH)/src/mm/frame.c \
arch/$(ARCH)/src/mm/memory_init.c \
arch/$(ARCH)/src/mm/page.c \
arch/$(ARCH)/src/mm/tlb.c

/tags/0.2.0/kernel/arch/ppc64/_link.ld.in
0,0 → 1,59
/** PPC64 linker script
*
* umapped section:
* kernel text
* kernel data
* mapped section:
* kernel text
* kernel data
*
*/
#define __ASM__
#include <arch/boot/boot.h>
#include <arch/mm/page.h>
ENTRY(kernel_image_start)
OUTPUT_FORMAT("elf64-powerpc")
OUTPUT_ARCH(powerpc:common64)
SECTIONS {
.unmapped 0: AT (0) {
unmapped_ktext_start = .;
*(K_UNMAPPED_TEXT_START);
unmapped_ktext_end = .;
unmapped_kdata_start = .;
*(K_UNMAPPED_DATA_START);
unmapped_kdata_start = .;
}
.mapped PA2KA(BOOT_OFFSET): AT (BOOT_OFFSET) {
ktext_start = .;
*(K_TEXT_START);
*(.text);
ktext_end = .;
kdata_start = .;
*(K_DATA_START);
*(.rodata);
*(.rodata.*);
*(.data); /* initialized data */
*(.sdata);
*(.sdata2);
*(.sbss);
hardcoded_ktext_size = .;
LONG(ktext_end - ktext_start);
hardcoded_kdata_size = .;
LONG(kdata_end - kdata_start);
hardcoded_load_address = .;
LONG(PA2KA(BOOT_OFFSET));
*(.bss); /* uninitialized static variables */
*(COMMON); /* global variables */
symbol_table = .;
*(symtab.*); /* Symbol table, must be LAST symbol!*/
kdata_end = .;
}
}