| 67,6 → 67,12 |
|---|
| instruction_access_exception_tl0: |
| PREEMPTIBLE_HANDLER instruction_access_exception |
| |
| /* TT = 0x09, TL = 0, instruction_access_mmu_miss */ |
| .org trap_table + TT_INSTRUCTION_ACCESS_MMU_MISS*ENTRY_SIZE |
| .global instruction_access_mmu_miss_handler_tl0 |
| ba fast_instruction_access_mmu_miss_handler_tl0 |
| nop |
| |
| /* TT = 0x0a, TL = 0, instruction_access_error */ |
| .org trap_table + TT_INSTRUCTION_ACCESS_ERROR*ENTRY_SIZE |
| .global instruction_access_error_tl0 |
| 176,6 → 182,13 |
|---|
| data_access_exception_tl0: |
| PREEMPTIBLE_HANDLER data_access_exception |
| |
| /* TT = 0x31, TL = 0, data_access_mmu_miss */ |
| .org trap_table + TT_DATA_ACCESS_MMU_MISS*ENTRY_SIZE |
| .global data_access_mmu_miss_tl0 |
| data_access_mmu_miss_tl0: |
| ba fast_data_access_mmu_miss_handler_tl0 |
| nop |
| |
| /* TT = 0x32, TL = 0, data_access_error */ |
| .org trap_table + TT_DATA_ACCESS_ERROR*ENTRY_SIZE |
| .global data_access_error_tl0 |
| 396,6 → 409,13 |
|---|
| wrpr %g0, 1, %tl |
| PREEMPTIBLE_HANDLER instruction_access_exception |
| |
| /* TT = 0x09, TL > 0, instruction_access_mmu_miss */ |
| .org trap_table + (TT_INSTRUCTION_ACCESS_MMU_MISS+512)*ENTRY_SIZE |
| .global instruction_access_mmu_miss_handler_tl1 |
| wrpr %g0, 1, %tl |
| ba fast_instruction_access_mmu_miss_handler_tl0 |
| nop |
| |
| /* TT = 0x0a, TL > 0, instruction_access_error */ |
| .org trap_table + (TT_INSTRUCTION_ACCESS_ERROR+512)*ENTRY_SIZE |
| .global instruction_access_error_tl1 |
| 473,6 → 493,14 |
|---|
| wrpr %g0, PSTATE_AG_BIT | PSTATE_PRIV_BIT, %pstate |
| PREEMPTIBLE_HANDLER data_access_exception*/ |
| |
| /* TT = 0x31, TL > 0, data_access_mmu_miss */ |
| .org trap_table + (TT_DATA_ACCESS_MMU_MISS+512)*ENTRY_SIZE |
| .global data_access_mmu_miss_tl1 |
| data_access_mmu_miss_tl1: |
| ba fast_data_access_mmu_miss_handler_tl1 |
| nop |
| |
| |
| /* TT = 0x32, TL > 0, data_access_error */ |
| .org trap_table + (TT_DATA_ACCESS_ERROR+512)*ENTRY_SIZE |
| .global data_access_error_tl1 |