| 53,10 → 53,10 |
|---|
| |
| interrupt_register(14, "tick_int", tick_interrupt); |
| compare.int_dis = false; |
| compare.tick_cmpr = CPU->arch.clock_frequency / HZ; |
| compare.tick_cmpr = tick_counter_read() + |
| CPU->arch.clock_frequency / HZ; |
| CPU->arch.next_tick_cmpr = compare.tick_cmpr; |
| tick_compare_write(compare.value); |
| tick_write(0); |
| |
| #if defined (US3) |
| /* disable STICK interrupts and clear any pending ones */ |
| 110,12 → 110,12 |
|---|
| * about 812 years. If there was a 2GHz UltraSPARC computer, it would |
| * overflow only in 146 years. |
| */ |
| drift = tick_read() - CPU->arch.next_tick_cmpr; |
| drift = tick_counter_read() - CPU->arch.next_tick_cmpr; |
| while (drift > CPU->arch.clock_frequency / HZ) { |
| drift -= CPU->arch.clock_frequency / HZ; |
| CPU->missed_clock_ticks++; |
| } |
| CPU->arch.next_tick_cmpr = tick_read() + |
| CPU->arch.next_tick_cmpr = tick_counter_read() + |
| (CPU->arch.clock_frequency / HZ) - drift; |
| tick_compare_write(CPU->arch.next_tick_cmpr); |
| clock(); |