| /branches/sparc/kernel/arch/sparc64/src/smp/ipi.c |
|---|
| 100,6 → 100,8 |
| if (status & INTR_DISPATCH_STATUS_BUSY) |
| panic("Interrupt Dispatch Status busy bit set\n"); |
| ASSERT(!(pstate_read() & PSTATE_IE_BIT)); |
| do { |
| set_intr_w_data(func); |
| asi_u64_write(ASI_INTR_W, |
| /branches/sparc/kernel/arch/sparc64/src/ddi/ddi.c |
|---|
| 41,7 → 41,7 |
| * Interrupts are disabled and task is locked. |
| * |
| * @param task Task. |
| * @param ioaddr Startign I/O space address. |
| * @param ioaddr Starting I/O space address. |
| * @param size Size of the enabled I/O range. |
| * |
| * @return 0 on success or an error code from errno.h. |
| /branches/sparc/kernel/arch/sparc64/src/sparc64.c |
|---|
| 87,9 → 87,12 |
| * But we only create 128 buckets. |
| */ |
| irq_init(1 << 11, 128); |
| #if defined (CONFIG_SIMICS_OUTPUT) |
| simics_output_init(); |
| //standalone_sparc64_console_init(); |
| #else |
| standalone_sparc64_console_init(); |
| #endif |
| } |
| } |
| /branches/sparc/kernel/arch/sparc64/src/trap/interrupt.c |
|---|
| 67,8 → 67,12 |
| */ |
| void interrupt(int n, istate_t *istate) |
| { |
| uint64_t status; |
| uint64_t intrcv; |
| uint64_t data0; |
| status = asi_u64_read(ASI_INTR_DISPATCH_STATUS, 0); |
| if (status & (!INTR_DISPATCH_STATUS_BUSY)) |
| panic("Interrupt Dispatch Status busy bit not set\n"); |
| intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0); |
| #if defined (US) |
| /branches/sparc/kernel/arch/sparc64/src/mm/tlb.c |
|---|
| 103,7 → 103,7 |
| pg.address = page; |
| fr.address = frame; |
| tag.value = ASID_KERNEL; |
| tag.context = ASID_KERNEL; |
| tag.vpn = pg.vpn; |
| dtlb_tag_access_write(tag.value); |
| 467,9 → 467,16 |
| sfsr.value = dtlb_sfsr_read(); |
| sfar = dtlb_sfar_read(); |
| #if defined (US) |
| printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
| "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
| sfsr.ow, sfsr.fv); |
| #elif defined (US3) |
| printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
| "fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
| sfsr.ow, sfsr.fv); |
| #endif |
| printf("DTLB SFAR: address=%p\n", sfar); |
| dtlb_sfsr_write(0); |
| 618,4 → 625,4 |
| } |
| /** @} |
| */ |
| */ |
| /branches/sparc/kernel/arch/sparc64/src/mm/as.c |
|---|
| 164,7 → 164,25 |
| itsb_base_write(tsb_base.value); |
| tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH; |
| dtsb_base_write(tsb_base.value); |
| #if defined (US3) |
| /* |
| * Clear the extension registers. |
| * In HelenOS, primary and secondary context registers contain |
| * equal values and kernel misses (context 0, ie. the nucleus context) |
| * are excluded from the TSB miss handler, so it makes no sense |
| * to have separate TSBs for primary, secondary and nucleus contexts. |
| * Clearing the extension registers will ensure that the value of the |
| * TSB Base register will be used as an address of TSB, making the code |
| * compatible with the US port. |
| */ |
| itsb_primary_extension_write(0); |
| itsb_nucleus_extension_write(0); |
| dtsb_primary_extension_write(0); |
| dtsb_secondary_extension_write(0); |
| dtsb_nucleus_extension_write(0); |
| #endif |
| #endif |
| } |
| /** Perform sparc64-specific tasks when an address space is removed from the |