| /branches/sparc/kernel/arch/sparc64/include/trap/syscall.h |
|---|
| 0,0 → 1,57 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** |
| * @file |
| * @brief This file contains the trap_instruction handler. |
| * |
| * The trap_instruction trap is used to implement syscalls. |
| */ |
| #ifndef KERN_sparc64_SYSCALL_TRAP_H_ |
| #define KERN_sparc64_SYSCALL_TRAP_H_ |
| #define TT_TRAP_INSTRUCTION(n) (0x100 + (n)) |
| #define TT_TRAP_INSTRUCTION_LAST TT_TRAP_INSTRUCTION(127) |
| #ifdef __ASM__ |
| .macro TRAP_INSTRUCTION n |
| ba trap_instruction_handler |
| mov TT_TRAP_INSTRUCTION(\n) - TT_TRAP_INSTRUCTION(0), %g2 |
| .endm |
| #endif /* __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/trap/trap_table.h |
|---|
| 0,0 → 1,112 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_TRAP_TABLE_H_ |
| #define KERN_sparc64_TRAP_TABLE_H_ |
| #include <arch/stack.h> |
| #define TRAP_TABLE_ENTRY_COUNT 1024 |
| #define TRAP_TABLE_ENTRY_SIZE 32 |
| #define TRAP_TABLE_SIZE (TRAP_TABLE_ENTRY_COUNT * TRAP_TABLE_ENTRY_SIZE) |
| #ifndef __ASM__ |
| #include <arch/types.h> |
| struct trap_table_entry { |
| uint8_t octets[TRAP_TABLE_ENTRY_SIZE]; |
| } __attribute__ ((packed)); |
| typedef struct trap_table_entry trap_table_entry_t; |
| extern trap_table_entry_t trap_table[TRAP_TABLE_ENTRY_COUNT]; |
| extern trap_table_entry_t trap_table_save[TRAP_TABLE_ENTRY_COUNT]; |
| #endif /* !__ASM__ */ |
| #ifdef __ASM__ |
| .macro SAVE_GLOBALS |
| mov %g1, %l1 |
| mov %g2, %l2 |
| mov %g3, %l3 |
| mov %g4, %l4 |
| mov %g5, %l5 |
| mov %g6, %l6 |
| mov %g7, %l7 |
| .endm |
| .macro RESTORE_GLOBALS |
| mov %l1, %g1 |
| mov %l2, %g2 |
| mov %l3, %g3 |
| mov %l4, %g4 |
| mov %l5, %g5 |
| mov %l6, %g6 |
| mov %l7, %g7 |
| .endm |
| /* |
| * The following needs to be in sync with the definition of the istate |
| * structure. The one STACK_ITEM_SIZE is counted for space holding the 7th |
| * argument to syscall_handler (i.e. syscall number) and the other |
| * STACK_ITEM_SIZE is counted because of the required alignment. |
| */ |
| #define PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE \ |
| (STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE + \ |
| (2 * STACK_ITEM_SIZE) + (12 * 8)) |
| #define SAVED_TSTATE -(1 * 8) |
| #define SAVED_TPC -(2 * 8) |
| #define SAVED_TNPC -(3 * 8) /* <-- istate_t begins here */ |
| #define SAVED_Y -(4 * 8) |
| #define SAVED_I0 -(5 * 8) |
| #define SAVED_I1 -(6 * 8) |
| #define SAVED_I2 -(7 * 8) |
| #define SAVED_I3 -(8 * 8) |
| #define SAVED_I4 -(9 * 8) |
| #define SAVED_I5 -(10 * 8) |
| #define SAVED_I6 -(11 * 8) |
| #define SAVED_I7 -(12 * 8) |
| .macro PREEMPTIBLE_HANDLER f |
| sethi %hi(\f), %g1 |
| b preemptible_handler |
| or %g1, %lo(\f), %g1 |
| .endm |
| #endif /* __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/trap/mmu.h |
|---|
| 0,0 → 1,182 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** |
| * @file |
| * @brief This file contains fast MMU trap handlers. |
| */ |
| #ifndef KERN_sparc64_MMU_TRAP_H_ |
| #define KERN_sparc64_MMU_TRAP_H_ |
| #include <arch/stack.h> |
| #include <arch/regdef.h> |
| #include <arch/mm/tlb.h> |
| #include <arch/mm/mmu.h> |
| #include <arch/mm/tte.h> |
| #include <arch/trap/regwin.h> |
| #ifdef CONFIG_TSB |
| #include <arch/mm/tsb.h> |
| #endif |
| #define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 |
| #define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 |
| #define TT_FAST_DATA_ACCESS_PROTECTION 0x6c |
| #define FAST_MMU_HANDLER_SIZE 128 |
| #ifdef __ASM__ |
| .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER |
| /* |
| * First, try to refill TLB from TSB. |
| */ |
| #ifdef CONFIG_TSB |
| ldxa [%g0] ASI_IMMU, %g1 ! read TSB Tag Target Register |
| ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2 ! read TSB 8K Pointer |
| ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 |
| cmp %g1, %g4 ! is this the entry we are looking for? |
| bne,pn %xcc, 0f |
| nop |
| stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG ! copy mapping from ITSB to ITLB |
| retry |
| #endif |
| 0: |
| wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
| PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss |
| .endm |
| .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl |
| /* |
| * First, try to refill TLB from TSB. |
| */ |
| #ifdef CONFIG_TSB |
| ldxa [%g0] ASI_DMMU, %g1 ! read TSB Tag Target Register |
| srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss? |
| brz,pn %g2, 0f |
| ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3 ! read TSB 8K Pointer |
| ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 |
| cmp %g1, %g4 ! is this the entry we are looking for? |
| bne,pn %xcc, 0f |
| nop |
| stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG ! copy mapping from DTSB to DTLB |
| retry |
| #endif |
| /* |
| * Second, test if it is the portion of the kernel address space |
| * which is faulting. If that is the case, immediately create |
| * identity mapping for that page in DTLB. VPN 0 is excluded from |
| * this treatment. |
| * |
| * Note that branch-delay slots are used in order to save space. |
| */ |
| 0: |
| mov VA_DMMU_TAG_ACCESS, %g1 |
| ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN |
| set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 |
| andcc %g1, %g2, %g3 ! get Context |
| bnz 0f ! Context is non-zero |
| andncc %g1, %g2, %g3 ! get page address into %g3 |
| bz 0f ! page address is zero |
| sethi %hi(kernel_8k_tlb_data_template), %g2 |
| ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2 |
| or %g3, %g2, %g2 |
| stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page |
| retry |
| /* |
| * Third, catch and handle special cases when the trap is caused by |
| * the userspace register window spill or fill handler. In case |
| * one of these two traps caused this trap, we just lower the trap |
| * level and service the DTLB miss. In the end, we restart |
| * the offending SAVE or RESTORE. |
| */ |
| 0: |
| .if (\tl > 0) |
| wrpr %g0, 1, %tl |
| .endif |
| /* |
| * Switch from the MM globals. |
| */ |
| wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
| /* |
| * Read the Tag Access register for the higher-level handler. |
| * This is necessary to survive nested DTLB misses. |
| */ |
| mov VA_DMMU_TAG_ACCESS, %g2 |
| ldxa [%g2] ASI_DMMU, %g2 |
| /* |
| * g2 will be passed as an argument to fast_data_access_mmu_miss(). |
| */ |
| PREEMPTIBLE_HANDLER fast_data_access_mmu_miss |
| .endm |
| .macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl |
| /* |
| * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. |
| */ |
| .if (\tl > 0) |
| wrpr %g0, 1, %tl |
| .endif |
| /* |
| * Switch from the MM globals. |
| */ |
| wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
| /* |
| * Read the Tag Access register for the higher-level handler. |
| * This is necessary to survive nested DTLB misses. |
| */ |
| mov VA_DMMU_TAG_ACCESS, %g2 |
| ldxa [%g2] ASI_DMMU, %g2 |
| /* |
| * g2 will be passed as an argument to fast_data_access_mmu_miss(). |
| */ |
| PREEMPTIBLE_HANDLER fast_data_access_protection |
| .endm |
| #endif /* __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/trap/interrupt.h |
|---|
| 0,0 → 1,117 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** |
| * @file |
| * @brief This file contains interrupt vector trap handler. |
| */ |
| #ifndef KERN_sparc64_TRAP_INTERRUPT_H_ |
| #define KERN_sparc64_TRAP_INTERRUPT_H_ |
| #include <arch/trap/trap_table.h> |
| #include <arch/stack.h> |
| /* IMAP register bits */ |
| #define IGN_MASK 0x7c0 |
| #define INO_MASK 0x1f |
| #define IMAP_V_MASK (1ULL << 31) |
| #define IGN_SHIFT 6 |
| /* Interrupt ASI registers. */ |
| #define ASI_UDB_INTR_W 0x77 |
| #define ASI_INTR_DISPATCH_STATUS 0x48 |
| #define ASI_UDB_INTR_R 0x7f |
| #define ASI_INTR_RECEIVE 0x49 |
| /* VA's used with ASI_UDB_INTR_W register. */ |
| #define ASI_UDB_INTR_W_DATA_0 0x40 |
| #define ASI_UDB_INTR_W_DATA_1 0x50 |
| #define ASI_UDB_INTR_W_DATA_2 0x60 |
| #define ASI_UDB_INTR_W_DISPATCH 0x70 |
| /* VA's used with ASI_UDB_INTR_R register. */ |
| #define ASI_UDB_INTR_R_DATA_0 0x40 |
| #define ASI_UDB_INTR_R_DATA_1 0x50 |
| #define ASI_UDB_INTR_R_DATA_2 0x60 |
| /* Shifts in the Interrupt Vector Dispatch virtual address. */ |
| #define INTR_VEC_DISPATCH_MID_SHIFT 14 |
| /* Bits in the Interrupt Dispatch Status register. */ |
| #define INTR_DISPATCH_STATUS_NACK 0x2 |
| #define INTR_DISPATCH_STATUS_BUSY 0x1 |
| #define TT_INTERRUPT_LEVEL_1 0x41 |
| #define TT_INTERRUPT_LEVEL_2 0x42 |
| #define TT_INTERRUPT_LEVEL_3 0x43 |
| #define TT_INTERRUPT_LEVEL_4 0x44 |
| #define TT_INTERRUPT_LEVEL_5 0x45 |
| #define TT_INTERRUPT_LEVEL_6 0x46 |
| #define TT_INTERRUPT_LEVEL_7 0x47 |
| #define TT_INTERRUPT_LEVEL_8 0x48 |
| #define TT_INTERRUPT_LEVEL_9 0x49 |
| #define TT_INTERRUPT_LEVEL_10 0x4a |
| #define TT_INTERRUPT_LEVEL_11 0x4b |
| #define TT_INTERRUPT_LEVEL_12 0x4c |
| #define TT_INTERRUPT_LEVEL_13 0x4d |
| #define TT_INTERRUPT_LEVEL_14 0x4e |
| #define TT_INTERRUPT_LEVEL_15 0x4f |
| #define TT_INTERRUPT_VECTOR_TRAP 0x60 |
| #define INTERRUPT_LEVEL_N_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE |
| #define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE |
| #ifdef __ASM__ |
| .macro INTERRUPT_LEVEL_N_HANDLER n |
| mov \n - 1, %g2 |
| PREEMPTIBLE_HANDLER exc_dispatch |
| .endm |
| .macro INTERRUPT_VECTOR_TRAP_HANDLER |
| PREEMPTIBLE_HANDLER interrupt |
| .endm |
| #endif /* __ASM__ */ |
| #ifndef __ASM__ |
| #include <arch/interrupt.h> |
| extern void interrupt(int n, istate_t *istate); |
| #endif /* !def __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/trap/exception.h |
|---|
| 0,0 → 1,90 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** |
| * @file |
| */ |
| #ifndef KERN_sparc64_EXCEPTION_H_ |
| #define KERN_sparc64_EXCEPTION_H_ |
| #define TT_INSTRUCTION_ACCESS_EXCEPTION 0x08 |
| #define TT_INSTRUCTION_ACCESS_ERROR 0x0a |
| #define TT_ILLEGAL_INSTRUCTION 0x10 |
| #define TT_PRIVILEGED_OPCODE 0x11 |
| #define TT_UNIMPLEMENTED_LDD 0x12 |
| #define TT_UNIMPLEMENTED_STD 0x13 |
| #define TT_FP_DISABLED 0x20 |
| #define TT_FP_EXCEPTION_IEEE_754 0x21 |
| #define TT_FP_EXCEPTION_OTHER 0x22 |
| #define TT_TAG_OVERFLOW 0x23 |
| #define TT_DIVISION_BY_ZERO 0x28 |
| #define TT_DATA_ACCESS_EXCEPTION 0x30 |
| #define TT_DATA_ACCESS_ERROR 0x32 |
| #define TT_MEM_ADDRESS_NOT_ALIGNED 0x34 |
| #define TT_LDDF_MEM_ADDRESS_NOT_ALIGNED 0x35 |
| #define TT_STDF_MEM_ADDRESS_NOT_ALIGNED 0x36 |
| #define TT_PRIVILEGED_ACTION 0x37 |
| #define TT_LDQF_MEM_ADDRESS_NOT_ALIGNED 0x38 |
| #define TT_STQF_MEM_ADDRESS_NOT_ALIGNED 0x39 |
| #ifndef __ASM__ |
| #include <arch/interrupt.h> |
| extern void dump_istate(istate_t *istate); |
| extern void instruction_access_exception(int n, istate_t *istate); |
| extern void instruction_access_error(int n, istate_t *istate); |
| extern void illegal_instruction(int n, istate_t *istate); |
| extern void privileged_opcode(int n, istate_t *istate); |
| extern void unimplemented_LDD(int n, istate_t *istate); |
| extern void unimplemented_STD(int n, istate_t *istate); |
| extern void fp_disabled(int n, istate_t *istate); |
| extern void fp_exception_ieee_754(int n, istate_t *istate); |
| extern void fp_exception_other(int n, istate_t *istate); |
| extern void tag_overflow(int n, istate_t *istate); |
| extern void division_by_zero(int n, istate_t *istate); |
| extern void data_access_exception(int n, istate_t *istate); |
| extern void data_access_error(int n, istate_t *istate); |
| extern void mem_address_not_aligned(int n, istate_t *istate); |
| extern void LDDF_mem_address_not_aligned(int n, istate_t *istate); |
| extern void STDF_mem_address_not_aligned(int n, istate_t *istate); |
| extern void privileged_action(int n, istate_t *istate); |
| extern void LDQF_mem_address_not_aligned(int n, istate_t *istate); |
| extern void STQF_mem_address_not_aligned(int n, istate_t *istate); |
| #endif /* !__ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/trap/regwin.h |
|---|
| 0,0 → 1,231 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** |
| * @file |
| * @brief This file contains register window trap handlers. |
| */ |
| #ifndef KERN_sparc64_REGWIN_H_ |
| #define KERN_sparc64_REGWIN_H_ |
| #include <arch/stack.h> |
| #include <arch/arch.h> |
| #define TT_CLEAN_WINDOW 0x24 |
| #define TT_SPILL_0_NORMAL 0x80 /* kernel spills */ |
| #define TT_SPILL_1_NORMAL 0x84 /* userspace spills */ |
| #define TT_SPILL_2_NORMAL 0x88 /* spills to userspace window buffer */ |
| #define TT_SPILL_0_OTHER 0xa0 /* spills to userspace window buffer */ |
| #define TT_FILL_0_NORMAL 0xc0 /* kernel fills */ |
| #define TT_FILL_1_NORMAL 0xc4 /* userspace fills */ |
| #define REGWIN_HANDLER_SIZE 128 |
| #define CLEAN_WINDOW_HANDLER_SIZE REGWIN_HANDLER_SIZE |
| #define SPILL_HANDLER_SIZE REGWIN_HANDLER_SIZE |
| #define FILL_HANDLER_SIZE REGWIN_HANDLER_SIZE |
| /* Window Save Area offsets. */ |
| #define L0_OFFSET 0 |
| #define L1_OFFSET 8 |
| #define L2_OFFSET 16 |
| #define L3_OFFSET 24 |
| #define L4_OFFSET 32 |
| #define L5_OFFSET 40 |
| #define L6_OFFSET 48 |
| #define L7_OFFSET 56 |
| #define I0_OFFSET 64 |
| #define I1_OFFSET 72 |
| #define I2_OFFSET 80 |
| #define I3_OFFSET 88 |
| #define I4_OFFSET 96 |
| #define I5_OFFSET 104 |
| #define I6_OFFSET 112 |
| #define I7_OFFSET 120 |
| #ifdef __ASM__ |
| /* |
| * Macro used by the nucleus and the primary context 0 during normal and other spills. |
| */ |
| .macro SPILL_NORMAL_HANDLER_KERNEL |
| stx %l0, [%sp + STACK_BIAS + L0_OFFSET] |
| stx %l1, [%sp + STACK_BIAS + L1_OFFSET] |
| stx %l2, [%sp + STACK_BIAS + L2_OFFSET] |
| stx %l3, [%sp + STACK_BIAS + L3_OFFSET] |
| stx %l4, [%sp + STACK_BIAS + L4_OFFSET] |
| stx %l5, [%sp + STACK_BIAS + L5_OFFSET] |
| stx %l6, [%sp + STACK_BIAS + L6_OFFSET] |
| stx %l7, [%sp + STACK_BIAS + L7_OFFSET] |
| stx %i0, [%sp + STACK_BIAS + I0_OFFSET] |
| stx %i1, [%sp + STACK_BIAS + I1_OFFSET] |
| stx %i2, [%sp + STACK_BIAS + I2_OFFSET] |
| stx %i3, [%sp + STACK_BIAS + I3_OFFSET] |
| stx %i4, [%sp + STACK_BIAS + I4_OFFSET] |
| stx %i5, [%sp + STACK_BIAS + I5_OFFSET] |
| stx %i6, [%sp + STACK_BIAS + I6_OFFSET] |
| stx %i7, [%sp + STACK_BIAS + I7_OFFSET] |
| saved |
| retry |
| .endm |
| /* |
| * Macro used by the userspace during normal spills. |
| */ |
| .macro SPILL_NORMAL_HANDLER_USERSPACE |
| wr %g0, ASI_AIUP, %asi |
| stxa %l0, [%sp + STACK_BIAS + L0_OFFSET] %asi |
| stxa %l1, [%sp + STACK_BIAS + L1_OFFSET] %asi |
| stxa %l2, [%sp + STACK_BIAS + L2_OFFSET] %asi |
| stxa %l3, [%sp + STACK_BIAS + L3_OFFSET] %asi |
| stxa %l4, [%sp + STACK_BIAS + L4_OFFSET] %asi |
| stxa %l5, [%sp + STACK_BIAS + L5_OFFSET] %asi |
| stxa %l6, [%sp + STACK_BIAS + L6_OFFSET] %asi |
| stxa %l7, [%sp + STACK_BIAS + L7_OFFSET] %asi |
| stxa %i0, [%sp + STACK_BIAS + I0_OFFSET] %asi |
| stxa %i1, [%sp + STACK_BIAS + I1_OFFSET] %asi |
| stxa %i2, [%sp + STACK_BIAS + I2_OFFSET] %asi |
| stxa %i3, [%sp + STACK_BIAS + I3_OFFSET] %asi |
| stxa %i4, [%sp + STACK_BIAS + I4_OFFSET] %asi |
| stxa %i5, [%sp + STACK_BIAS + I5_OFFSET] %asi |
| stxa %i6, [%sp + STACK_BIAS + I6_OFFSET] %asi |
| stxa %i7, [%sp + STACK_BIAS + I7_OFFSET] %asi |
| saved |
| retry |
| .endm |
| /* |
| * Macro used to spill userspace window to userspace window buffer. |
| * It can be either triggered from preemptible_handler doing SAVE |
| * at (TL=1) or from normal kernel code doing SAVE when OTHERWIN>0 |
| * at (TL=0). |
| */ |
| .macro SPILL_TO_USPACE_WINDOW_BUFFER |
| stx %l0, [%g7 + L0_OFFSET] |
| stx %l1, [%g7 + L1_OFFSET] |
| stx %l2, [%g7 + L2_OFFSET] |
| stx %l3, [%g7 + L3_OFFSET] |
| stx %l4, [%g7 + L4_OFFSET] |
| stx %l5, [%g7 + L5_OFFSET] |
| stx %l6, [%g7 + L6_OFFSET] |
| stx %l7, [%g7 + L7_OFFSET] |
| stx %i0, [%g7 + I0_OFFSET] |
| stx %i1, [%g7 + I1_OFFSET] |
| stx %i2, [%g7 + I2_OFFSET] |
| stx %i3, [%g7 + I3_OFFSET] |
| stx %i4, [%g7 + I4_OFFSET] |
| stx %i5, [%g7 + I5_OFFSET] |
| stx %i6, [%g7 + I6_OFFSET] |
| stx %i7, [%g7 + I7_OFFSET] |
| add %g7, STACK_WINDOW_SAVE_AREA_SIZE, %g7 |
| saved |
| retry |
| .endm |
| /* |
| * Macro used by the nucleus and the primary context 0 during normal fills. |
| */ |
| .macro FILL_NORMAL_HANDLER_KERNEL |
| ldx [%sp + STACK_BIAS + L0_OFFSET], %l0 |
| ldx [%sp + STACK_BIAS + L1_OFFSET], %l1 |
| ldx [%sp + STACK_BIAS + L2_OFFSET], %l2 |
| ldx [%sp + STACK_BIAS + L3_OFFSET], %l3 |
| ldx [%sp + STACK_BIAS + L4_OFFSET], %l4 |
| ldx [%sp + STACK_BIAS + L5_OFFSET], %l5 |
| ldx [%sp + STACK_BIAS + L6_OFFSET], %l6 |
| ldx [%sp + STACK_BIAS + L7_OFFSET], %l7 |
| ldx [%sp + STACK_BIAS + I0_OFFSET], %i0 |
| ldx [%sp + STACK_BIAS + I1_OFFSET], %i1 |
| ldx [%sp + STACK_BIAS + I2_OFFSET], %i2 |
| ldx [%sp + STACK_BIAS + I3_OFFSET], %i3 |
| ldx [%sp + STACK_BIAS + I4_OFFSET], %i4 |
| ldx [%sp + STACK_BIAS + I5_OFFSET], %i5 |
| ldx [%sp + STACK_BIAS + I6_OFFSET], %i6 |
| ldx [%sp + STACK_BIAS + I7_OFFSET], %i7 |
| restored |
| retry |
| .endm |
| /* |
| * Macro used by the userspace during normal fills. |
| */ |
| .macro FILL_NORMAL_HANDLER_USERSPACE |
| wr %g0, ASI_AIUP, %asi |
| ldxa [%sp + STACK_BIAS + L0_OFFSET] %asi, %l0 |
| ldxa [%sp + STACK_BIAS + L1_OFFSET] %asi, %l1 |
| ldxa [%sp + STACK_BIAS + L2_OFFSET] %asi, %l2 |
| ldxa [%sp + STACK_BIAS + L3_OFFSET] %asi, %l3 |
| ldxa [%sp + STACK_BIAS + L4_OFFSET] %asi, %l4 |
| ldxa [%sp + STACK_BIAS + L5_OFFSET] %asi, %l5 |
| ldxa [%sp + STACK_BIAS + L6_OFFSET] %asi, %l6 |
| ldxa [%sp + STACK_BIAS + L7_OFFSET] %asi, %l7 |
| ldxa [%sp + STACK_BIAS + I0_OFFSET] %asi, %i0 |
| ldxa [%sp + STACK_BIAS + I1_OFFSET] %asi, %i1 |
| ldxa [%sp + STACK_BIAS + I2_OFFSET] %asi, %i2 |
| ldxa [%sp + STACK_BIAS + I3_OFFSET] %asi, %i3 |
| ldxa [%sp + STACK_BIAS + I4_OFFSET] %asi, %i4 |
| ldxa [%sp + STACK_BIAS + I5_OFFSET] %asi, %i5 |
| ldxa [%sp + STACK_BIAS + I6_OFFSET] %asi, %i6 |
| ldxa [%sp + STACK_BIAS + I7_OFFSET] %asi, %i7 |
| restored |
| retry |
| .endm |
| .macro CLEAN_WINDOW_HANDLER |
| rdpr %cleanwin, %l0 |
| add %l0, 1, %l0 |
| wrpr %l0, 0, %cleanwin |
| mov %r0, %l0 |
| mov %r0, %l1 |
| mov %r0, %l2 |
| mov %r0, %l3 |
| mov %r0, %l4 |
| mov %r0, %l5 |
| mov %r0, %l6 |
| mov %r0, %l7 |
| mov %r0, %o0 |
| mov %r0, %o1 |
| mov %r0, %o2 |
| mov %r0, %o3 |
| mov %r0, %o4 |
| mov %r0, %o5 |
| mov %r0, %o6 |
| mov %r0, %o7 |
| retry |
| .endm |
| #endif /* __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/trap/trap.h |
|---|
| 0,0 → 1,44 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_TRAP_H_ |
| #define KERN_sparc64_TRAP_H_ |
| extern void trap_init(void); |
| #endif |
| /** @} |
| */ |