| /branches/sparc/kernel/arch/sparc64/include/mm/page.h |
|---|
| 0,0 → 1,84 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_PAGE_H_ |
| #define KERN_sparc64_PAGE_H_ |
| #include <arch/mm/frame.h> |
| /* |
| * On the TLB and TSB level, we still use 8K pages, which are supported by the |
| * MMU. |
| */ |
| #define MMU_PAGE_WIDTH MMU_FRAME_WIDTH |
| #define MMU_PAGE_SIZE MMU_FRAME_SIZE |
| /* |
| * On the page table level, we use 16K pages. 16K pages are not supported by |
| * the MMU but we emulate them with pairs of 8K pages. |
| */ |
| #define PAGE_WIDTH FRAME_WIDTH |
| #define PAGE_SIZE FRAME_SIZE |
| #define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) |
| #ifdef KERNEL |
| #ifndef __ASM__ |
| #include <arch/interrupt.h> |
| extern uintptr_t physmem_base; |
| #define KA2PA(x) (((uintptr_t) (x)) + physmem_base) |
| #define PA2KA(x) (((uintptr_t) (x)) - physmem_base) |
| typedef union { |
| uintptr_t address; |
| struct { |
| uint64_t vpn : 51; /**< Virtual Page Number. */ |
| unsigned offset : 13; /**< Offset. */ |
| } __attribute__ ((packed)); |
| } page_address_t; |
| extern void page_arch_init(void); |
| #endif /* !def __ASM__ */ |
| #endif /* KERNEL */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/tlb.h |
|---|
| 0,0 → 1,444 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_TLB_H_ |
| #define KERN_sparc64_TLB_H_ |
| #define ITLB_ENTRY_COUNT 64 |
| #define DTLB_ENTRY_COUNT 64 |
| #define MEM_CONTEXT_KERNEL 0 |
| #define MEM_CONTEXT_TEMP 1 |
| /** Page sizes. */ |
| #define PAGESIZE_8K 0 |
| #define PAGESIZE_64K 1 |
| #define PAGESIZE_512K 2 |
| #define PAGESIZE_4M 3 |
| /** Bit width of the TLB-locked portion of kernel address space. */ |
| #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
| /* TLB Demap Operation types. */ |
| #define TLB_DEMAP_PAGE 0 |
| #define TLB_DEMAP_CONTEXT 1 |
| #define TLB_DEMAP_TYPE_SHIFT 6 |
| /* TLB Demap Operation Context register encodings. */ |
| #define TLB_DEMAP_PRIMARY 0 |
| #define TLB_DEMAP_SECONDARY 1 |
| #define TLB_DEMAP_NUCLEUS 2 |
| #define TLB_DEMAP_CONTEXT_SHIFT 4 |
| /* TLB Tag Access shifts */ |
| #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
| #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) |
| #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
| #ifndef __ASM__ |
| #include <arch/mm/tte.h> |
| #include <arch/mm/mmu.h> |
| #include <arch/mm/page.h> |
| #include <arch/asm.h> |
| #include <arch/barrier.h> |
| #include <arch/types.h> |
| union tlb_context_reg { |
| uint64_t v; |
| struct { |
| unsigned long : 51; |
| unsigned context : 13; /**< Context/ASID. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tlb_context_reg tlb_context_reg_t; |
| /** I-/D-TLB Data In/Access Register type. */ |
| typedef tte_data_t tlb_data_t; |
| /** I-/D-TLB Data Access Address in Alternate Space. */ |
| union tlb_data_access_addr { |
| uint64_t value; |
| struct { |
| uint64_t : 55; |
| unsigned tlb_entry : 6; |
| unsigned : 3; |
| } __attribute__ ((packed)); |
| }; |
| typedef union tlb_data_access_addr tlb_data_access_addr_t; |
| typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
| /** I-/D-TLB Tag Read Register. */ |
| union tlb_tag_read_reg { |
| uint64_t value; |
| struct { |
| uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
| unsigned context : 13; /**< Context identifier. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
| typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
| /** TLB Demap Operation Address. */ |
| union tlb_demap_addr { |
| uint64_t value; |
| struct { |
| uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
| unsigned : 6; /**< Ignored. */ |
| unsigned type : 1; /**< The type of demap operation. */ |
| unsigned context : 2; /**< Context register selection. */ |
| unsigned : 4; /**< Zero. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tlb_demap_addr tlb_demap_addr_t; |
| /** TLB Synchronous Fault Status Register. */ |
| union tlb_sfsr_reg { |
| uint64_t value; |
| struct { |
| unsigned long : 40; /**< Implementation dependent. */ |
| unsigned asi : 8; /**< ASI. */ |
| unsigned : 2; |
| unsigned ft : 7; /**< Fault type. */ |
| unsigned e : 1; /**< Side-effect bit. */ |
| unsigned ct : 2; /**< Context Register selection. */ |
| unsigned pr : 1; /**< Privilege bit. */ |
| unsigned w : 1; /**< Write bit. */ |
| unsigned ow : 1; /**< Overwrite bit. */ |
| unsigned fv : 1; /**< Fault Valid bit. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
| /** Read MMU Primary Context Register. |
| * |
| * @return Current value of Primary Context Register. |
| */ |
| static inline uint64_t mmu_primary_context_read(void) |
| { |
| return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
| } |
| /** Write MMU Primary Context Register. |
| * |
| * @param v New value of Primary Context Register. |
| */ |
| static inline void mmu_primary_context_write(uint64_t v) |
| { |
| asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
| flush_pipeline(); |
| } |
| /** Read MMU Secondary Context Register. |
| * |
| * @return Current value of Secondary Context Register. |
| */ |
| static inline uint64_t mmu_secondary_context_read(void) |
| { |
| return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
| } |
| /** Write MMU Primary Context Register. |
| * |
| * @param v New value of Primary Context Register. |
| */ |
| static inline void mmu_secondary_context_write(uint64_t v) |
| { |
| asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
| flush_pipeline(); |
| } |
| /** Read IMMU TLB Data Access Register. |
| * |
| * @param entry TLB Entry index. |
| * |
| * @return Current value of specified IMMU TLB Data Access Register. |
| */ |
| static inline uint64_t itlb_data_access_read(index_t entry) |
| { |
| tlb_data_access_addr_t reg; |
| reg.value = 0; |
| reg.tlb_entry = entry; |
| return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
| } |
| /** Write IMMU TLB Data Access Register. |
| * |
| * @param entry TLB Entry index. |
| * @param value Value to be written. |
| */ |
| static inline void itlb_data_access_write(index_t entry, uint64_t value) |
| { |
| tlb_data_access_addr_t reg; |
| reg.value = 0; |
| reg.tlb_entry = entry; |
| asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
| flush_pipeline(); |
| } |
| /** Read DMMU TLB Data Access Register. |
| * |
| * @param entry TLB Entry index. |
| * |
| * @return Current value of specified DMMU TLB Data Access Register. |
| */ |
| static inline uint64_t dtlb_data_access_read(index_t entry) |
| { |
| tlb_data_access_addr_t reg; |
| reg.value = 0; |
| reg.tlb_entry = entry; |
| return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
| } |
| /** Write DMMU TLB Data Access Register. |
| * |
| * @param entry TLB Entry index. |
| * @param value Value to be written. |
| */ |
| static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
| { |
| tlb_data_access_addr_t reg; |
| reg.value = 0; |
| reg.tlb_entry = entry; |
| asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
| membar(); |
| } |
| /** Read IMMU TLB Tag Read Register. |
| * |
| * @param entry TLB Entry index. |
| * |
| * @return Current value of specified IMMU TLB Tag Read Register. |
| */ |
| static inline uint64_t itlb_tag_read_read(index_t entry) |
| { |
| tlb_tag_read_addr_t tag; |
| tag.value = 0; |
| tag.tlb_entry = entry; |
| return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
| } |
| /** Read DMMU TLB Tag Read Register. |
| * |
| * @param entry TLB Entry index. |
| * |
| * @return Current value of specified DMMU TLB Tag Read Register. |
| */ |
| static inline uint64_t dtlb_tag_read_read(index_t entry) |
| { |
| tlb_tag_read_addr_t tag; |
| tag.value = 0; |
| tag.tlb_entry = entry; |
| return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
| } |
| /** Write IMMU TLB Tag Access Register. |
| * |
| * @param v Value to be written. |
| */ |
| static inline void itlb_tag_access_write(uint64_t v) |
| { |
| asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
| flush_pipeline(); |
| } |
| /** Read IMMU TLB Tag Access Register. |
| * |
| * @return Current value of IMMU TLB Tag Access Register. |
| */ |
| static inline uint64_t itlb_tag_access_read(void) |
| { |
| return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
| } |
| /** Write DMMU TLB Tag Access Register. |
| * |
| * @param v Value to be written. |
| */ |
| static inline void dtlb_tag_access_write(uint64_t v) |
| { |
| asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
| membar(); |
| } |
| /** Read DMMU TLB Tag Access Register. |
| * |
| * @return Current value of DMMU TLB Tag Access Register. |
| */ |
| static inline uint64_t dtlb_tag_access_read(void) |
| { |
| return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
| } |
| /** Write IMMU TLB Data in Register. |
| * |
| * @param v Value to be written. |
| */ |
| static inline void itlb_data_in_write(uint64_t v) |
| { |
| asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
| flush_pipeline(); |
| } |
| /** Write DMMU TLB Data in Register. |
| * |
| * @param v Value to be written. |
| */ |
| static inline void dtlb_data_in_write(uint64_t v) |
| { |
| asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
| membar(); |
| } |
| /** Read ITLB Synchronous Fault Status Register. |
| * |
| * @return Current content of I-SFSR register. |
| */ |
| static inline uint64_t itlb_sfsr_read(void) |
| { |
| return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
| } |
| /** Write ITLB Synchronous Fault Status Register. |
| * |
| * @param v New value of I-SFSR register. |
| */ |
| static inline void itlb_sfsr_write(uint64_t v) |
| { |
| asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
| flush_pipeline(); |
| } |
| /** Read DTLB Synchronous Fault Status Register. |
| * |
| * @return Current content of D-SFSR register. |
| */ |
| static inline uint64_t dtlb_sfsr_read(void) |
| { |
| return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
| } |
| /** Write DTLB Synchronous Fault Status Register. |
| * |
| * @param v New value of D-SFSR register. |
| */ |
| static inline void dtlb_sfsr_write(uint64_t v) |
| { |
| asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
| membar(); |
| } |
| /** Read DTLB Synchronous Fault Address Register. |
| * |
| * @return Current content of D-SFAR register. |
| */ |
| static inline uint64_t dtlb_sfar_read(void) |
| { |
| return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
| } |
| /** Perform IMMU TLB Demap Operation. |
| * |
| * @param type Selects between context and page demap. |
| * @param context_encoding Specifies which Context register has Context ID for |
| * demap. |
| * @param page Address which is on the page to be demapped. |
| */ |
| static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
| { |
| tlb_demap_addr_t da; |
| page_address_t pg; |
| da.value = 0; |
| pg.address = page; |
| da.type = type; |
| da.context = context_encoding; |
| da.vpn = pg.vpn; |
| asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
| * address within the |
| * ASI */ |
| flush_pipeline(); |
| } |
| /** Perform DMMU TLB Demap Operation. |
| * |
| * @param type Selects between context and page demap. |
| * @param context_encoding Specifies which Context register has Context ID for |
| * demap. |
| * @param page Address which is on the page to be demapped. |
| */ |
| static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
| { |
| tlb_demap_addr_t da; |
| page_address_t pg; |
| da.value = 0; |
| pg.address = page; |
| da.type = type; |
| da.context = context_encoding; |
| da.vpn = pg.vpn; |
| asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
| * address within the |
| * ASI */ |
| membar(); |
| } |
| extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
| extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
| extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
| extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
| extern void dump_sfsr_and_sfar(void); |
| #endif /* !def __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/cache_spec.h |
|---|
| 0,0 → 1,57 |
| /* |
| * Copyright (c) 2008 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_CACHE_SPEC_H_ |
| #define KERN_sparc64_CACHE_SPEC_H_ |
| /* |
| * The following macros are valid for the following processors: |
| * |
| * UltraSPARC, UltraSPARC II, UltraSPARC IIi |
| * |
| * Should we support other UltraSPARC processors, we need to make sure that |
| * the macros are defined correctly for them. |
| */ |
| #define DCACHE_SIZE (16 * 1024) |
| #define DCACHE_LINE_SIZE 32 |
| #define ICACHE_SIZE (16 * 1024) |
| #define ICACHE_WAYS 2 |
| #define ICACHE_LINE_SIZE 32 |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/frame.h |
|---|
| 0,0 → 1,80 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_FRAME_H_ |
| #define KERN_sparc64_FRAME_H_ |
| /* |
| * Page size supported by the MMU. |
| * For 8K there is the nasty illegal virtual aliasing problem. |
| * Therefore, the kernel uses 8K only internally on the TLB and TSB levels. |
| */ |
| #define MMU_FRAME_WIDTH 13 /* 8K */ |
| #define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) |
| /* |
| * Page size exported to the generic memory management subsystems. |
| * This page size is not directly supported by the MMU, but we can emulate |
| * each 16K page with a pair of adjacent 8K pages. |
| */ |
| #define FRAME_WIDTH 14 /* 16K */ |
| #define FRAME_SIZE (1 << FRAME_WIDTH) |
| #ifdef KERNEL |
| #ifndef __ASM__ |
| #include <arch/types.h> |
| union frame_address { |
| uintptr_t address; |
| struct { |
| unsigned : 23; |
| uint64_t pfn : 28; /**< Physical Frame Number. */ |
| unsigned offset : 13; /**< Offset. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union frame_address frame_address_t; |
| extern uintptr_t last_frame; |
| extern void frame_arch_init(void); |
| #define physmem_print() |
| #endif |
| #endif |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/as.h |
|---|
| 0,0 → 1,96 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_AS_H_ |
| #define KERN_sparc64_AS_H_ |
| #include <arch/mm/tte.h> |
| #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1 |
| #define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 |
| #define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff |
| #define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 |
| #define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff |
| #define USTACK_ADDRESS_ARCH (0xffffffffffffffffULL - (PAGE_SIZE - 1)) |
| #ifdef CONFIG_TSB |
| /** TSB Tag Target register. */ |
| typedef union tsb_tag_target { |
| uint64_t value; |
| struct { |
| unsigned invalid : 1; /**< Invalidated by software. */ |
| unsigned : 2; |
| unsigned context : 13; /**< Software ASID. */ |
| unsigned : 6; |
| uint64_t va_tag : 42; /**< Virtual address bits <63:22>. */ |
| } __attribute__ ((packed)); |
| } tsb_tag_target_t; |
| /** TSB entry. */ |
| typedef struct tsb_entry { |
| tsb_tag_target_t tag; |
| tte_data_t data; |
| } __attribute__ ((packed)) tsb_entry_t; |
| typedef struct { |
| tsb_entry_t *itsb; |
| tsb_entry_t *dtsb; |
| } as_arch_t; |
| #else |
| typedef struct { |
| } as_arch_t; |
| #endif /* CONFIG_TSB */ |
| #include <genarch/mm/as_ht.h> |
| #ifdef CONFIG_TSB |
| #include <arch/mm/tsb.h> |
| #define as_invalidate_translation_cache(as, page, cnt) \ |
| tsb_invalidate((as), (page), (cnt)) |
| #else |
| #define as_invalidate_translation_cache(as, page, cnt) |
| #endif |
| extern void as_arch_init(void); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/cache.h |
|---|
| 0,0 → 1,53 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_CACHE_H_ |
| #define KERN_sparc64_CACHE_H_ |
| #include <mm/page.h> |
| #include <mm/frame.h> |
| #define dcache_flush_page(p) \ |
| dcache_flush_color(PAGE_COLOR((p))) |
| #define dcache_flush_frame(p, f) \ |
| dcache_flush_tag(PAGE_COLOR((p)), ADDR2PFN((f))); |
| extern void dcache_flush(void); |
| extern void dcache_flush_color(int c); |
| extern void dcache_flush_tag(int c, pfn_t tag); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/tsb.h |
|---|
| 0,0 → 1,123 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_TSB_H_ |
| #define KERN_sparc64_TSB_H_ |
| /* |
| * ITSB abd DTSB will claim 64K of memory, which |
| * is a nice number considered that it is one of |
| * the page sizes supported by hardware, which, |
| * again, is nice because TSBs need to be locked |
| * in TLBs - only one TLB entry will do. |
| */ |
| #define TSB_SIZE 2 /* when changing this, change |
| * as.c as well */ |
| #define ITSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) |
| #define DTSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) |
| #define TSB_TAG_TARGET_CONTEXT_SHIFT 48 |
| #ifndef __ASM__ |
| #include <arch/mm/tte.h> |
| #include <arch/mm/mmu.h> |
| #include <arch/types.h> |
| /** TSB Base register. */ |
| typedef union tsb_base_reg { |
| uint64_t value; |
| struct { |
| uint64_t base : 51; /**< TSB base address, bits 63:13. */ |
| unsigned split : 1; /**< Split vs. common TSB for 8K and 64K |
| * pages. HelenOS uses only 8K pages |
| * for user mappings, so we always set |
| * this to 0. |
| */ |
| unsigned : 9; |
| unsigned size : 3; /**< TSB size. Number of entries is |
| * 512 * 2^size. */ |
| } __attribute__ ((packed)); |
| } tsb_base_reg_t; |
| /** Read ITSB Base register. |
| * |
| * @return Content of the ITSB Base register. |
| */ |
| static inline uint64_t itsb_base_read(void) |
| { |
| return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE); |
| } |
| /** Read DTSB Base register. |
| * |
| * @return Content of the DTSB Base register. |
| */ |
| static inline uint64_t dtsb_base_read(void) |
| { |
| return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE); |
| } |
| /** Write ITSB Base register. |
| * |
| * @param v New content of the ITSB Base register. |
| */ |
| static inline void itsb_base_write(uint64_t v) |
| { |
| asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v); |
| } |
| /** Write DTSB Base register. |
| * |
| * @param v New content of the DTSB Base register. |
| */ |
| static inline void dtsb_base_write(uint64_t v) |
| { |
| asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v); |
| } |
| /* Forward declarations. */ |
| struct as; |
| struct pte; |
| extern void tsb_invalidate(struct as *as, uintptr_t page, count_t pages); |
| extern void itsb_pte_copy(struct pte *t, index_t index); |
| extern void dtsb_pte_copy(struct pte *t, index_t index, bool ro); |
| #endif /* !def __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/mmu.h |
|---|
| 0,0 → 1,109 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_MMU_H_ |
| #define KERN_sparc64_MMU_H_ |
| /* LSU Control Register ASI. */ |
| #define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ |
| /* I-MMU ASIs. */ |
| #define ASI_IMMU 0x50 |
| #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
| #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
| #define ASI_ITLB_DATA_IN_REG 0x54 |
| #define ASI_ITLB_DATA_ACCESS_REG 0x55 |
| #define ASI_ITLB_TAG_READ_REG 0x56 |
| #define ASI_IMMU_DEMAP 0x57 |
| /* Virtual Addresses within ASI_IMMU. */ |
| #define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ |
| #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
| #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
| #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
| /* D-MMU ASIs. */ |
| #define ASI_DMMU 0x58 |
| #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
| #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
| #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b |
| #define ASI_DTLB_DATA_IN_REG 0x5c |
| #define ASI_DTLB_DATA_ACCESS_REG 0x5d |
| #define ASI_DTLB_TAG_READ_REG 0x5e |
| #define ASI_DMMU_DEMAP 0x5f |
| /* Virtual Addresses within ASI_DMMU. */ |
| #define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */ |
| #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
| #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
| #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ |
| #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
| #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
| #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
| #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
| #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
| #ifndef __ASM__ |
| #include <arch/asm.h> |
| #include <arch/barrier.h> |
| #include <arch/types.h> |
| /** LSU Control Register. */ |
| typedef union { |
| uint64_t value; |
| struct { |
| unsigned : 23; |
| unsigned pm : 8; |
| unsigned vm : 8; |
| unsigned pr : 1; |
| unsigned pw : 1; |
| unsigned vr : 1; |
| unsigned vw : 1; |
| unsigned : 1; |
| unsigned fm : 16; |
| unsigned dm : 1; /**< D-MMU enable. */ |
| unsigned im : 1; /**< I-MMU enable. */ |
| unsigned dc : 1; /**< D-Cache enable. */ |
| unsigned ic : 1; /**< I-Cache enable. */ |
| } __attribute__ ((packed)); |
| } lsu_cr_reg_t; |
| #endif /* !def __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/tte.h |
|---|
| 0,0 → 1,98 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_TTE_H_ |
| #define KERN_sparc64_TTE_H_ |
| #define TTE_G (1 << 0) |
| #define TTE_W (1 << 1) |
| #define TTE_P (1 << 2) |
| #define TTE_E (1 << 3) |
| #define TTE_CV (1 << 4) |
| #define TTE_CP (1 << 5) |
| #define TTE_L (1 << 6) |
| #define TTE_V_SHIFT 63 |
| #define TTE_SIZE_SHIFT 61 |
| #ifndef __ASM__ |
| #include <arch/types.h> |
| #define VA_TAG_PAGE_SHIFT 22 |
| /** Translation Table Entry - Tag. */ |
| union tte_tag { |
| uint64_t value; |
| struct { |
| unsigned g : 1; /**< Global. */ |
| unsigned : 2; /**< Reserved. */ |
| unsigned context : 13; /**< Context identifier. */ |
| unsigned : 6; /**< Reserved. */ |
| uint64_t va_tag : 42; /**< Virtual Address Tag, bits 63:22. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tte_tag tte_tag_t; |
| /** Translation Table Entry - Data. */ |
| union tte_data { |
| uint64_t value; |
| struct { |
| unsigned v : 1; /**< Valid. */ |
| unsigned size : 2; /**< Page size of this entry. */ |
| unsigned nfo : 1; /**< No-Fault-Only. */ |
| unsigned ie : 1; /**< Invert Endianness. */ |
| unsigned soft2 : 9; /**< Software defined field. */ |
| unsigned diag : 9; /**< Diagnostic data. */ |
| unsigned pfn : 28; /**< Physical Address bits, bits 40:13. */ |
| unsigned soft : 6; /**< Software defined field. */ |
| unsigned l : 1; /**< Lock. */ |
| unsigned cp : 1; /**< Cacheable in physically indexed cache. */ |
| unsigned cv : 1; /**< Cacheable in virtually indexed cache. */ |
| unsigned e : 1; /**< Side-effect. */ |
| unsigned p : 1; /**< Privileged. */ |
| unsigned w : 1; /**< Writable. */ |
| unsigned g : 1; /**< Global. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tte_data tte_data_t; |
| #endif /* !def __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/asid.h |
|---|
| 0,0 → 1,50 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_ASID_H_ |
| #define KERN_sparc64_ASID_H_ |
| #include <arch/types.h> |
| /* |
| * On SPARC, Context means the same thing as ASID trough out the kernel. |
| */ |
| typedef uint16_t asid_t; |
| #define ASID_MAX_ARCH 8191 /* 2^13 - 1 */ |
| #endif |
| /** @} |
| */ |