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/branches/sparc/kernel/arch/sparc64/include/regdef.h
File deleted
/branches/sparc/kernel/arch/sparc64/include/sun4v/regdef.h
0,0 → 1,68
/*
* Copyright (c) 2005 Jakub Jermar
* Copyright (c) 2008 Pavel Rimsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup sparc64
* @{
*/
/** @file
*/
 
#ifndef KERN_sparc64_sun4v_REGDEF_H_
#define KERN_sparc64_sun4v_REGDEF_H_
 
#define PSTATE_PRIV_BIT (1 << 2)
 
/*
 
#define PSTATE_IE_BIT (1 << 1)
#define PSTATE_AM_BIT (1 << 3)
 
#define PSTATE_AG_BIT (1 << 0)
#define PSTATE_IG_BIT (1 << 11)
#define PSTATE_MG_BIT (1 << 10)
 
#define PSTATE_PRIV_BIT (1 << 2)
#define PSTATE_PEF_BIT (1 << 4)
 
#define TSTATE_PSTATE_SHIFT 8
#define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT << TSTATE_PSTATE_SHIFT)
#define TSTATE_IE_BIT (PSTATE_IE_BIT << TSTATE_PSTATE_SHIFT)
#define TSTATE_PEF_BIT (PSTATE_PEF_BIT << TSTATE_PSTATE_SHIFT)
 
#define TSTATE_CWP_MASK 0x1f
 
#define WSTATE_NORMAL(n) (n)
#define WSTATE_OTHER(n) ((n) << 3)
 
*/
 
#endif
 
/** @}
*/
/branches/sparc/kernel/arch/sparc64/include/sun4v/hypercall.h
0,0 → 1,184
/*
* Copyright (c) 2008 Pavel Rimsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup sparc64
* @{
*/
/**
* @file
* @brief Macros, constants and functions needed to perform a call to the
* hypervisor API. For details and terminology see this document:
* UltraSPARC Virtual Machine Specification (The Hypervisor API
* specification for Logical Domains).
*
*/
 
#ifndef KERN_sparc64_sun4v_HYPERCALL_H_
#define KERN_sparc64_sun4v_HYPERCALL_H_
 
/* SW trap numbers for hyperfast traps */
#define FAST_TRAP 0x80
#define MMU_MAP_ADDR 0x83
#define MMU_UNMAP_ADDR 0x84
 
/* function codes for fast traps */
#define MACH_DESC 0x01
#define CPU_START 0x10
#define CPU_STOP 0x11
#define CPU_YIELD 0x12
#define CPU_MYID 0x16
#define CPU_STATE 0x17
#define CPU_SET_RTBA 0x18
#define CPU_GET_RTBA 0x19
#define MMU_TSB_CTX0 0x20
#define MMU_TSB_CTXNON0 0x21
#define MMU_DEMAP_PAGE 0x22
#define MMU_DEMAP_CTX 0x23
#define MMU_DEMAP_ALL 0x24
#define MMU_MAP_PERM_ADDR 0x25
#define MMU_FAULT_AREA_CONF 0x26
#define MMU_ENABLE 0x27
#define MMU_UNMAP_PERM_ADDR 0x28
#define MMU_TSB_CTX0_INFO 0x29
#define MMU_TSB_CTXNON0_INFO 0x2a
#define MMU_FAULT_AREA_INFO 0x2b
#define CPU_MONDO_SEND 0x42
#define CONS_GETCHAR 0x60
#define CONS_PUTCHAR 0x61
 
/**
* Performs a hyperfast hypervisor API call from the assembly language code.
* Expects the registers %o1-%o4 are properly filled with the arguments of the
* call.
*
* @param function_number hyperfast call function number
*/
#define __HYPERCALL_FAST(function_number) \
set function_number, %o5; \
ta FAST_TRAP;
/**
* Performs a fast hypervisor API call from the assembly language code.
* Expects the registers %o1-%o4 are properly filled with the arguments of the
* call.
*
* @param sw_trap_number software trap number
*/
#define __HYPERCALL_HYPERFAST(sw_trap_number) \
ta (sw_trap_number);
 
 
#ifndef __ASM__
 
/*
* Macros to be used from the C-language code; __hypercall_fastN performs
* a fast hypervisor API call taking exactly N arguments.
*/
 
#define __hypercall_fast0(function_number) \
__hypercall_fast(0, 0, 0, 0, 0, function_number)
#define __hypercall_fast1(function_number, p1) \
__hypercall_fast(p1, 0, 0, 0, 0, function_number)
#define __hypercall_fast2(function_number, p1, p2) \
__hypercall_fast(p1, p2, 0, 0, 0, function_number)
#define __hypercall_fast3(function_number, p1, p2, p3) \
__hypercall_fast(p1, p2, p3, 0, 0, function_number)
#define __hypercall_fast4(function_number, p1, p2, p3, p4) \
__hypercall_fast(p1, p2, p3, p4, 0, function_number)
#define __hypercall_fast5(function_number, p1, p2, p3, p4, p5) \
__hypercall_fast(p1, p2, p3, p4, p5, function_number)
 
/**
* Performs a fast hypervisor API call.
*
* @param p1 the 1st argument of the hypervisor API call
* @param p2 the 2nd argument of the hypervisor API call
* @param p3 the 3rd argument of the hypervisor API call
* @param p4 the 4th argument of the hypervisor API call
* @param p5 the 5th argument of the hypervisor API call
* @param function_number function number of the call
*/
static inline uint64_t
__hypercall_fast(const uint64_t p1, const uint64_t p2, const uint64_t p3,
const uint64_t p4, const uint64_t p5, const uint64_t function_number)
{
register uint64_t a6 asm("o5") = function_number;
register uint64_t a1 asm("o0") = p1;
register uint64_t a2 asm("o1") = p2;
register uint64_t a3 asm("o2") = p3;
register uint64_t a4 asm("o3") = p4;
register uint64_t a5 asm("o4") = p5;
 
asm volatile (
"ta %7\n"
: "=r" (a1)
: "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6),
"i" (FAST_TRAP)
: "memory"
);
return a1;
}
 
/**
* Performs a hyperfast hypervisor API call.
*
* @param p1 the 1st argument of the hypervisor API call
* @param p2 the 2nd argument of the hypervisor API call
* @param p3 the 3rd argument of the hypervisor API call
* @param p4 the 4th argument of the hypervisor API call
* @param p5 the 5th argument of the hypervisor API call
* @param sw_trap_number software trap number
*/
static inline uint64_t
__hypercall_hyperfast(const uint64_t p1, const uint64_t p2, const uint64_t p3,
const uint64_t p4, const uint64_t p5, const uint64_t sw_trap_number)
{
register uint64_t a1 asm("o0") = p1;
register uint64_t a2 asm("o1") = p2;
register uint64_t a3 asm("o2") = p3;
register uint64_t a4 asm("o3") = p4;
register uint64_t a5 asm("o4") = p5;
 
asm volatile (
"ta %6\n"
: "=r" (a1)
: "r" (a1), "r" (a2), "r" (a3), "r" (a4), "r" (a5),
"i" (sw_trap_number)
: "memory"
);
return a1;
}
 
#endif /* ASM */
 
#endif
 
/** @}
*/
/branches/sparc/kernel/arch/sparc64/include/interrupt.h
37,7 → 37,7
#define KERN_sparc64_INTERRUPT_H_
 
#include <arch/types.h>
#include <arch/regdef.h>
#include <arch/sun4u/regdef.h>
 
#define IVT_ITEMS 15
#define IVT_FIRST 1
/branches/sparc/kernel/arch/sparc64/include/arch.h
39,9 → 39,6
 
#define ASI_AIUP 0x10 /** Access to primary context with user privileges. */
#define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */
#define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */
#define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */
#define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */
 
#define NWINDOWS 8 /** Number of register window sets. */
 
/branches/sparc/kernel/arch/sparc64/include/trap/mmu.h
File deleted
/branches/sparc/kernel/arch/sparc64/include/trap/sun4v/mmu.h
0,0 → 1,85
/*
* Copyright (c) 2006 Jakub Jermar
* Copyright (c) 2008 Pavel Rimsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup sparc64interrupt
* @{
*/
/**
* @file
* @brief This file contains fast MMU trap handlers.
*/
 
#ifndef KERN_sparc64_sun4v_MMU_TRAP_H_
#define KERN_sparc64_sun4v_MMU_TRAP_H_
 
#include <arch/stack.h>
#include <arch/sun4v/regdef.h>
#include <arch/mm/tlb.h>
#include <arch/mm/sun4v/mmu.h>
#include <arch/mm/sun4v/tte.h>
#include <arch/trap/regwin.h>
 
#ifdef CONFIG_TSB
#include <arch/mm/tsb.h>
#endif
 
#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68
#define TT_FAST_DATA_ACCESS_PROTECTION 0x6c
 
#define FAST_MMU_HANDLER_SIZE 128
 
#ifdef __ASM__
 
.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
.endm
 
/*
* So far it is here only to process the trap which occurs when the kernel
* needs to access the bootinfo structure, which is placed in the bootloader
* memory (i.e. before address 0x400000).
*/
.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
set 0x8000, %o0
set 0x0, %o1
setx 0x80000000804087c3, %g1, %o2
set 0x3, %o3
ta 0x83
retry
.endm
 
.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
.endm
 
#endif /* __ASM__ */
 
#endif
 
/** @}
*/
/branches/sparc/kernel/arch/sparc64/include/trap/sun4u/mmu.h
0,0 → 1,184
/*
* Copyright (c) 2006 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup sparc64interrupt
* @{
*/
/**
* @file
* @brief This file contains fast MMU trap handlers.
*/
 
#ifndef KERN_sparc64_sun4u_MMU_TRAP_H_
#define KERN_sparc64_sun4u_MMU_TRAP_H_
 
#include <arch/stack.h>
#include <arch/sun4u/regdef.h>
#include <arch/mm/tlb.h>
#include <arch/mm/sun4u/tlb.h>
#include <arch/mm/sun4u/mmu.h>
#include <arch/mm/sun4u/tte.h>
#include <arch/trap/regwin.h>
#include <arch/sun4u/arch.h>
 
#ifdef CONFIG_TSB
#include <arch/mm/tsb.h>
#endif
 
#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64
#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68
#define TT_FAST_DATA_ACCESS_PROTECTION 0x6c
 
#define FAST_MMU_HANDLER_SIZE 128
 
#ifdef __ASM__
 
.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
/*
* First, try to refill TLB from TSB.
*/
#ifdef CONFIG_TSB
ldxa [%g0] ASI_IMMU, %g1 ! read TSB Tag Target Register
ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2 ! read TSB 8K Pointer
ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5
cmp %g1, %g4 ! is this the entry we are looking for?
bne,pn %xcc, 0f
nop
stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG ! copy mapping from ITSB to ITLB
retry
 
#endif
0:
wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
.endm
 
.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
/*
* First, try to refill TLB from TSB.
*/
 
#ifdef CONFIG_TSB
ldxa [%g0] ASI_DMMU, %g1 ! read TSB Tag Target Register
srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss?
brz,pn %g2, 0f
ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3 ! read TSB 8K Pointer
ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5
cmp %g1, %g4 ! is this the entry we are looking for?
bne,pn %xcc, 0f
nop
stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG ! copy mapping from DTSB to DTLB
retry
#endif
 
/*
* Second, test if it is the portion of the kernel address space
* which is faulting. If that is the case, immediately create
* identity mapping for that page in DTLB. VPN 0 is excluded from
* this treatment.
*
* Note that branch-delay slots are used in order to save space.
*/
0:
mov VA_DMMU_TAG_ACCESS, %g1
ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN
set TLB_TAG_ACCESS_CONTEXT_MASK, %g2
andcc %g1, %g2, %g3 ! get Context
bnz 0f ! Context is non-zero
andncc %g1, %g2, %g3 ! get page address into %g3
bz 0f ! page address is zero
 
sethi %hi(kernel_8k_tlb_data_template), %g2
ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2
or %g3, %g2, %g2
stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page
retry
 
/*
* Third, catch and handle special cases when the trap is caused by
* the userspace register window spill or fill handler. In case
* one of these two traps caused this trap, we just lower the trap
* level and service the DTLB miss. In the end, we restart
* the offending SAVE or RESTORE.
*/
0:
.if (\tl > 0)
wrpr %g0, 1, %tl
.endif
 
/*
* Switch from the MM globals.
*/
wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
 
/*
* Read the Tag Access register for the higher-level handler.
* This is necessary to survive nested DTLB misses.
*/
mov VA_DMMU_TAG_ACCESS, %g2
ldxa [%g2] ASI_DMMU, %g2
 
/*
* g2 will be passed as an argument to fast_data_access_mmu_miss().
*/
PREEMPTIBLE_HANDLER fast_data_access_mmu_miss
.endm
 
.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
/*
* The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER.
*/
 
.if (\tl > 0)
wrpr %g0, 1, %tl
.endif
 
/*
* Switch from the MM globals.
*/
wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate
 
/*
* Read the Tag Access register for the higher-level handler.
* This is necessary to survive nested DTLB misses.
*/
mov VA_DMMU_TAG_ACCESS, %g2
ldxa [%g2] ASI_DMMU, %g2
 
/*
* g2 will be passed as an argument to fast_data_access_mmu_miss().
*/
PREEMPTIBLE_HANDLER fast_data_access_protection
.endm
 
#endif /* __ASM__ */
 
#endif
 
/** @}
*/
/branches/sparc/kernel/arch/sparc64/include/mm/tte.h
File deleted
/branches/sparc/kernel/arch/sparc64/include/mm/mmu.h
File deleted
/branches/sparc/kernel/arch/sparc64/include/mm/sun4v/tte.h
0,0 → 1,53
/*
* Copyright (c) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup sparc64mm
* @{
*/
/** @file
*/
 
#ifndef KERN_sparc64_sun4v_TTE_H_
#define KERN_sparc64_sun4v_TTE_H_
 
#define TTE_V_SHIFT 63 /**< valid */
#define TTE_TADDR_SHIFT 13 /**< target address */
#define TTE_CP_SHIFT 10 /**< cacheable physically */
#define TTE_CV_SHIFT 9 /**< caheable virtually */
#define TTE_P_SHIFT 8 /**< privileged */
#define TTE_EP_SHIFT 7 /**< execute permission */
#define TTE_W_SHIFT 6 /**< writable */
#define TTE_SZ_SHIFT 0 /**< size */
 
#define MMU_FLAG_ITLB 2 /**< operation applies to ITLB */
#define MMU_FLAG_DTLB 1 /**< operation applies to DTLB */
 
#endif
 
/** @}
*/
/branches/sparc/kernel/arch/sparc64/include/mm/sun4v/mmu.h
0,0 → 1,45
/*
* Copyright (c) 2005 Jakub Jermar
* Copyright (c) 2008 Pavel Rimsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup sparc64mm
* @{
*/
/** @file
*/
 
#ifndef KERN_sparc64_sun4v_MMU_H_
#define KERN_sparc64_sun4v_MMU_H_
 
#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context registeri VA. */
#define ASI_PRIMARY_CONTEXT_REG 0x21 /**< DMMU primary context register ASI. */
 
#endif
 
/** @}
*/
/branches/sparc/kernel/arch/sparc64/include/mm/tlb.h
35,17 → 35,6
#ifndef KERN_sparc64_TLB_H_
#define KERN_sparc64_TLB_H_
 
#if defined (US)
#define ITLB_ENTRY_COUNT 64
#define DTLB_ENTRY_COUNT 64
#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT
#endif
 
/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
#if defined (US3)
#define DTLB_MAX_LOCKED_ENTRIES 16
#endif
 
#define MEM_CONTEXT_KERNEL 0
#define MEM_CONTEXT_TEMP 1
 
55,635 → 44,9
#define PAGESIZE_512K 2
#define PAGESIZE_4M 3
 
/** Bit width of the TLB-locked portion of kernel address space. */
#define KERNEL_PAGE_WIDTH 22 /* 4M */
 
/* TLB Demap Operation types. */
#define TLB_DEMAP_PAGE 0
#define TLB_DEMAP_CONTEXT 1
#if defined (US3)
#define TLB_DEMAP_ALL 2
#endif
 
#define TLB_DEMAP_TYPE_SHIFT 6
 
/* TLB Demap Operation Context register encodings. */
#define TLB_DEMAP_PRIMARY 0
#define TLB_DEMAP_SECONDARY 1
#define TLB_DEMAP_NUCLEUS 2
 
/* There are more TLBs in one MMU in US3, their codes are defined here. */
#if defined (US3)
/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
#define TLB_DSMALL 0
#define TLB_DBIG_0 2
#define TLB_DBIG_1 3
/* I-MMU: one small (16-entry) TLB and one big TLB */
#define TLB_ISMALL 0
#define TLB_IBIG 2
#endif
 
#define TLB_DEMAP_CONTEXT_SHIFT 4
 
/* TLB Tag Access shifts */
#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0
#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
#define TLB_TAG_ACCESS_VPN_SHIFT 13
 
#ifndef __ASM__
 
#include <arch/mm/tte.h>
#include <arch/mm/mmu.h>
#include <arch/mm/page.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
#include <arch/register.h>
#include <arch/cpu.h>
 
union tlb_context_reg {
uint64_t v;
struct {
unsigned long : 51;
unsigned context : 13; /**< Context/ASID. */
} __attribute__ ((packed));
};
typedef union tlb_context_reg tlb_context_reg_t;
 
/** I-/D-TLB Data In/Access Register type. */
typedef tte_data_t tlb_data_t;
 
/** I-/D-TLB Data Access Address in Alternate Space. */
 
#if defined (US)
 
union tlb_data_access_addr {
uint64_t value;
struct {
uint64_t : 55;
unsigned tlb_entry : 6;
unsigned : 3;
} __attribute__ ((packed));
};
typedef union tlb_data_access_addr dtlb_data_access_addr_t;
typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
typedef union tlb_data_access_addr itlb_data_access_addr_t;
typedef union tlb_data_access_addr itlb_tag_read_addr_t;
 
#elif defined (US3)
 
/*
* In US3, I-MMU and D-MMU have different formats of the data
* access register virtual address. In the corresponding
* structures the member variable for the entry number is
* called "local_tlb_entry" - it contrasts with the "tlb_entry"
* for the US data access register VA structure. The rationale
* behind this is to prevent careless mistakes in the code
* caused by setting only the entry number and not the TLB
* number in the US3 code (when taking the code from US).
*/
 
union dtlb_data_access_addr {
uint64_t value;
struct {
uint64_t : 45;
unsigned : 1;
unsigned tlb_number : 2;
unsigned : 4;
unsigned local_tlb_entry : 9;
unsigned : 3;
} __attribute__ ((packed));
};
typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
 
union itlb_data_access_addr {
uint64_t value;
struct {
uint64_t : 45;
unsigned : 1;
unsigned tlb_number : 2;
unsigned : 6;
unsigned local_tlb_entry : 7;
unsigned : 3;
} __attribute__ ((packed));
};
typedef union itlb_data_access_addr itlb_data_access_addr_t;
typedef union itlb_data_access_addr itlb_tag_read_addr_t;
 
#endif
 
/** I-/D-TLB Tag Read Register. */
union tlb_tag_read_reg {
uint64_t value;
struct {
uint64_t vpn : 51; /**< Virtual Address bits 63:13. */
unsigned context : 13; /**< Context identifier. */
} __attribute__ ((packed));
};
typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
 
 
/** TLB Demap Operation Address. */
union tlb_demap_addr {
uint64_t value;
struct {
uint64_t vpn: 51; /**< Virtual Address bits 63:13. */
#if defined (US)
unsigned : 6; /**< Ignored. */
unsigned type : 1; /**< The type of demap operation. */
#elif defined (US3)
unsigned : 5; /**< Ignored. */
unsigned type: 2; /**< The type of demap operation. */
#endif
unsigned context : 2; /**< Context register selection. */
unsigned : 4; /**< Zero. */
} __attribute__ ((packed));
};
typedef union tlb_demap_addr tlb_demap_addr_t;
 
/** TLB Synchronous Fault Status Register. */
union tlb_sfsr_reg {
uint64_t value;
struct {
#if defined (US)
unsigned long : 40; /**< Implementation dependent. */
unsigned asi : 8; /**< ASI. */
unsigned : 2;
unsigned ft : 7; /**< Fault type. */
#elif defined (US3)
unsigned long : 39; /**< Implementation dependent. */
unsigned nf : 1; /**< Non-faulting load. */
unsigned asi : 8; /**< ASI. */
unsigned tm : 1; /**< I-TLB miss. */
unsigned : 3; /**< Reserved. */
unsigned ft : 5; /**< Fault type. */
#endif
unsigned e : 1; /**< Side-effect bit. */
unsigned ct : 2; /**< Context Register selection. */
unsigned pr : 1; /**< Privilege bit. */
unsigned w : 1; /**< Write bit. */
unsigned ow : 1; /**< Overwrite bit. */
unsigned fv : 1; /**< Fault Valid bit. */
} __attribute__ ((packed));
};
typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
 
#if defined (US3)
 
/*
* Functions for determining the number of entries in TLBs. They either return
* a constant value or a value based on the CPU autodetection.
*/
 
/**
* Determine the number of entries in the DMMU's small TLB.
*/
static inline uint16_t tlb_dsmall_size(void)
{
return 16;
}
 
/**
* Determine the number of entries in each DMMU's big TLB.
*/
static inline uint16_t tlb_dbig_size(void)
{
return 512;
}
 
/**
* Determine the number of entries in the IMMU's small TLB.
*/
static inline uint16_t tlb_ismall_size(void)
{
return 16;
}
 
/**
* Determine the number of entries in the IMMU's big TLB.
*/
static inline uint16_t tlb_ibig_size(void)
{
if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
return 512;
else
return 128;
}
 
#endif
 
/** Read MMU Primary Context Register.
*
* @return Current value of Primary Context Register.
*/
static inline uint64_t mmu_primary_context_read(void)
{
return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
*
* @param v New value of Primary Context Register.
*/
static inline void mmu_primary_context_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
flush_pipeline();
}
 
/** Read MMU Secondary Context Register.
*
* @return Current value of Secondary Context Register.
*/
static inline uint64_t mmu_secondary_context_read(void)
{
return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
*
* @param v New value of Primary Context Register.
*/
static inline void mmu_secondary_context_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
flush_pipeline();
}
 
#if defined (US)
 
/** Read IMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Data Access
* Register.
*/
static inline uint64_t itlb_data_access_read(index_t entry)
{
itlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void itlb_data_access_write(index_t entry, uint64_t value)
{
itlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Data Access
* Register.
*/
static inline uint64_t dtlb_data_access_read(index_t entry)
{
dtlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
{
dtlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
membar();
}
 
/** Read IMMU TLB Tag Read Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Tag Read Register.
*/
static inline uint64_t itlb_tag_read_read(index_t entry)
{
itlb_tag_read_addr_t tag;
 
tag.value = 0;
tag.tlb_entry = entry;
return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Tag Read Register.
*/
static inline uint64_t dtlb_tag_read_read(index_t entry)
{
dtlb_tag_read_addr_t tag;
 
tag.value = 0;
tag.tlb_entry = entry;
return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
 
#elif defined (US3)
 
 
/** Read IMMU TLB Data Access Register.
*
* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Data Access
* Register.
*/
static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
{
itlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_number = tlb;
reg.local_tlb_entry = entry;
return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void itlb_data_access_write(int tlb, index_t entry,
uint64_t value)
{
itlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_number = tlb;
reg.local_tlb_entry = entry;
asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
*
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Data Access
* Register.
*/
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
{
dtlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_number = tlb;
reg.local_tlb_entry = entry;
return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
*
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void dtlb_data_access_write(int tlb, index_t entry,
uint64_t value)
{
dtlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_number = tlb;
reg.local_tlb_entry = entry;
asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
membar();
}
 
/** Read IMMU TLB Tag Read Register.
*
* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Tag Read Register.
*/
static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
{
itlb_tag_read_addr_t tag;
 
tag.value = 0;
tag.tlb_number = tlb;
tag.local_tlb_entry = entry;
return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
*
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Tag Read Register.
*/
static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
{
dtlb_tag_read_addr_t tag;
 
tag.value = 0;
tag.tlb_number = tlb;
tag.local_tlb_entry = entry;
return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
 
#endif
 
 
/** Write IMMU TLB Tag Access Register.
*
* @param v Value to be written.
*/
static inline void itlb_tag_access_write(uint64_t v)
{
asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
flush_pipeline();
}
 
/** Read IMMU TLB Tag Access Register.
*
* @return Current value of IMMU TLB Tag Access Register.
*/
static inline uint64_t itlb_tag_access_read(void)
{
return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
}
 
/** Write DMMU TLB Tag Access Register.
*
* @param v Value to be written.
*/
static inline void dtlb_tag_access_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
membar();
}
 
/** Read DMMU TLB Tag Access Register.
*
* @return Current value of DMMU TLB Tag Access Register.
*/
static inline uint64_t dtlb_tag_access_read(void)
{
return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
}
 
 
/** Write IMMU TLB Data in Register.
*
* @param v Value to be written.
*/
static inline void itlb_data_in_write(uint64_t v)
{
asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
flush_pipeline();
}
 
/** Write DMMU TLB Data in Register.
*
* @param v Value to be written.
*/
static inline void dtlb_data_in_write(uint64_t v)
{
asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
membar();
}
 
/** Read ITLB Synchronous Fault Status Register.
*
* @return Current content of I-SFSR register.
*/
static inline uint64_t itlb_sfsr_read(void)
{
return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
}
 
/** Write ITLB Synchronous Fault Status Register.
*
* @param v New value of I-SFSR register.
*/
static inline void itlb_sfsr_write(uint64_t v)
{
asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
flush_pipeline();
}
 
/** Read DTLB Synchronous Fault Status Register.
*
* @return Current content of D-SFSR register.
*/
static inline uint64_t dtlb_sfsr_read(void)
{
return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
}
 
/** Write DTLB Synchronous Fault Status Register.
*
* @param v New value of D-SFSR register.
*/
static inline void dtlb_sfsr_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
membar();
}
 
/** Read DTLB Synchronous Fault Address Register.
*
* @return Current content of D-SFAR register.
*/
static inline uint64_t dtlb_sfar_read(void)
{
return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
}
 
/** Perform IMMU TLB Demap Operation.
*
* @param type Selects between context and page demap (and entire MMU
* demap on US3).
* @param context_encoding Specifies which Context register has Context ID for
* demap.
* @param page Address which is on the page to be demapped.
*/
static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
{
tlb_demap_addr_t da;
page_address_t pg;
da.value = 0;
pg.address = page;
da.type = type;
da.context = context_encoding;
da.vpn = pg.vpn;
/* da.value is the address within the ASI */
asi_u64_write(ASI_IMMU_DEMAP, da.value, 0);
 
flush_pipeline();
}
 
/** Perform DMMU TLB Demap Operation.
*
* @param type Selects between context and page demap (and entire MMU
* demap on US3).
* @param context_encoding Specifies which Context register has Context ID for
* demap.
* @param page Address which is on the page to be demapped.
*/
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
{
tlb_demap_addr_t da;
page_address_t pg;
da.value = 0;
pg.address = page;
da.type = type;
da.context = context_encoding;
da.vpn = pg.vpn;
/* da.value is the address within the ASI */
asi_u64_write(ASI_DMMU_DEMAP, da.value, 0);
 
membar();
}
 
extern void fast_instruction_access_mmu_miss(unative_t, istate_t *);
extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t, istate_t *);
extern void fast_data_access_protection(tlb_tag_access_reg_t , istate_t *);
 
extern void dtlb_insert_mapping(uintptr_t, uintptr_t, int, bool, bool);
 
extern void dump_sfsr_and_sfar(void);
 
#endif /* !def __ASM__ */
 
#endif
/branches/sparc/kernel/arch/sparc64/include/mm/as.h
35,7 → 35,7
#ifndef KERN_sparc64_AS_H_
#define KERN_sparc64_AS_H_
 
#include <arch/mm/tte.h>
#include <arch/mm/sun4u/tte.h>
 
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1
 
/branches/sparc/kernel/arch/sparc64/include/mm/tsb.h
51,8 → 51,8
 
#ifndef __ASM__
 
#include <arch/mm/tte.h>
#include <arch/mm/mmu.h>
#include <arch/mm/sun4u/tte.h>
#include <arch/mm/sun4u/mmu.h>
#include <arch/types.h>
 
/** TSB Base register. */
/branches/sparc/kernel/arch/sparc64/include/mm/sun4u/tte.h
0,0 → 1,104
/*
* Copyright (c) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup sparc64mm
* @{
*/
/** @file
*/
 
#ifndef KERN_sparc64_sun4u_TTE_H_
#define KERN_sparc64_sun4u_TTE_H_
 
#define TTE_G (1 << 0)
#define TTE_W (1 << 1)
#define TTE_P (1 << 2)
#define TTE_E (1 << 3)
#define TTE_CV (1 << 4)
#define TTE_CP (1 << 5)
#define TTE_L (1 << 6)
 
#define TTE_V_SHIFT 63
#define TTE_SIZE_SHIFT 61
 
#ifndef __ASM__
 
#include <arch/types.h>
 
/* TTE tag's VA_tag field contains bits <63:VA_TAG_PAGE_SHIFT> of the VA */
#define VA_TAG_PAGE_SHIFT 22
 
/** Translation Table Entry - Tag. */
union tte_tag {
uint64_t value;
struct {
unsigned g : 1; /**< Global. */
unsigned : 2; /**< Reserved. */
unsigned context : 13; /**< Context identifier. */
unsigned : 6; /**< Reserved. */
uint64_t va_tag : 42; /**< Virtual Address Tag, bits 63:22. */
} __attribute__ ((packed));
};
 
typedef union tte_tag tte_tag_t;
 
/** Translation Table Entry - Data. */
union tte_data {
uint64_t value;
struct {
unsigned v : 1; /**< Valid. */
unsigned size : 2; /**< Page size of this entry. */
unsigned nfo : 1; /**< No-Fault-Only. */
unsigned ie : 1; /**< Invert Endianness. */
unsigned soft2 : 9; /**< Software defined field. */
#if defined (US)
unsigned diag : 9; /**< Diagnostic data. */
unsigned pfn : 28; /**< Physical Address bits, bits 40:13. */
#elif defined (US3)
unsigned : 7; /**< Reserved. */
unsigned pfn : 30; /**< Physical Address bits, bits 42:13 */
#endif
unsigned soft : 6; /**< Software defined field. */
unsigned l : 1; /**< Lock. */
unsigned cp : 1; /**< Cacheable in physically indexed cache. */
unsigned cv : 1; /**< Cacheable in virtually indexed cache. */
unsigned e : 1; /**< Side-effect. */
unsigned p : 1; /**< Privileged. */
unsigned w : 1; /**< Writable. */
unsigned g : 1; /**< Global. */
} __attribute__ ((packed));
};
 
typedef union tte_data tte_data_t;
 
#endif /* !def __ASM__ */
 
#endif
 
/** @}
*/
/branches/sparc/kernel/arch/sparc64/include/mm/sun4u/mmu.h
0,0 → 1,123
/*
* Copyright (c) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup sparc64mm
* @{
*/
/** @file
*/
 
#ifndef KERN_sparc64_sun4u_MMU_H_
#define KERN_sparc64_sun4u_MMU_H_
 
#if defined(US)
/* LSU Control Register ASI. */
#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */
#endif
 
/* I-MMU ASIs. */
#define ASI_IMMU 0x50
#define ASI_IMMU_TSB_8KB_PTR_REG 0x51
#define ASI_IMMU_TSB_64KB_PTR_REG 0x52
#define ASI_ITLB_DATA_IN_REG 0x54
#define ASI_ITLB_DATA_ACCESS_REG 0x55
#define ASI_ITLB_TAG_READ_REG 0x56
#define ASI_IMMU_DEMAP 0x57
 
/* Virtual Addresses within ASI_IMMU. */
#define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */
#define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */
#define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */
#define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */
#if defined (US3)
#define VA_IMMU_PRIMARY_EXTENSION 0x48 /**< IMMU TSB primary extension register */
#define VA_IMMU_NUCLEUS_EXTENSION 0x58 /**< IMMU TSB nucleus extension register */
#endif
 
 
/* D-MMU ASIs. */
#define ASI_DMMU 0x58
#define ASI_DMMU_TSB_8KB_PTR_REG 0x59
#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a
#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
#define ASI_DTLB_DATA_IN_REG 0x5c
#define ASI_DTLB_DATA_ACCESS_REG 0x5d
#define ASI_DTLB_TAG_READ_REG 0x5e
#define ASI_DMMU_DEMAP 0x5f
 
/* Virtual Addresses within ASI_DMMU. */
#define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */
#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */
#define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */
#define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */
#define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */
#define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */
#define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */
#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */
#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */
#if defined (US3)
#define VA_DMMU_PRIMARY_EXTENSION 0x48 /**< DMMU TSB primary extension register */
#define VA_DMMU_SECONDARY_EXTENSION 0x50 /**< DMMU TSB secondary extension register */
#define VA_DMMU_NUCLEUS_EXTENSION 0x58 /**< DMMU TSB nucleus extension register */
#endif
 
#ifndef __ASM__
 
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
 
#if defined(US)
/** LSU Control Register. */
typedef union {
uint64_t value;
struct {
unsigned : 23;
unsigned pm : 8;
unsigned vm : 8;
unsigned pr : 1;
unsigned pw : 1;
unsigned vr : 1;
unsigned vw : 1;
unsigned : 1;
unsigned fm : 16;
unsigned dm : 1; /**< D-MMU enable. */
unsigned im : 1; /**< I-MMU enable. */
unsigned dc : 1; /**< D-Cache enable. */
unsigned ic : 1; /**< I-Cache enable. */
} __attribute__ ((packed));
} lsu_cr_reg_t;
#endif /* US */
 
#endif /* !def __ASM__ */
 
#endif
 
/** @}
*/
/branches/sparc/kernel/arch/sparc64/include/mm/sun4u/tlb.h
0,0 → 1,681
/*
* Copyright (c) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup sparc64mm
* @{
*/
/** @file
*/
 
#ifndef KERN_sparc64_sun4u_TLB_H_
#define KERN_sparc64_sun4u_TLB_H_
 
#if defined (US)
#define ITLB_ENTRY_COUNT 64
#define DTLB_ENTRY_COUNT 64
#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT
#endif
 
/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
#if defined (US3)
#define DTLB_MAX_LOCKED_ENTRIES 16
#endif
 
/** Bit width of the TLB-locked portion of kernel address space. */
#define KERNEL_PAGE_WIDTH 22 /* 4M */
 
/* TLB Demap Operation types. */
#define TLB_DEMAP_PAGE 0
#define TLB_DEMAP_CONTEXT 1
#if defined (US3)
#define TLB_DEMAP_ALL 2
#endif
 
#define TLB_DEMAP_TYPE_SHIFT 6
 
/* TLB Demap Operation Context register encodings. */
#define TLB_DEMAP_PRIMARY 0
#define TLB_DEMAP_SECONDARY 1
#define TLB_DEMAP_NUCLEUS 2
 
/* There are more TLBs in one MMU in US3, their codes are defined here. */
#if defined (US3)
/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
#define TLB_DSMALL 0
#define TLB_DBIG_0 2
#define TLB_DBIG_1 3
/* I-MMU: one small (16-entry) TLB and one big TLB */
#define TLB_ISMALL 0
#define TLB_IBIG 2
#endif
 
#define TLB_DEMAP_CONTEXT_SHIFT 4
 
/* TLB Tag Access shifts */
#define TLB_TAG_ACCESS_CONTEXT_SHIFT 0
#define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1)
#define TLB_TAG_ACCESS_VPN_SHIFT 13
 
#ifndef __ASM__
 
#include <arch/mm/sun4u/tte.h>
#include <arch/mm/sun4u/mmu.h>
#include <arch/mm/page.h>
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
#include <arch/register.h>
#include <arch/cpu.h>
 
union tlb_context_reg {
uint64_t v;
struct {
unsigned long : 51;
unsigned context : 13; /**< Context/ASID. */
} __attribute__ ((packed));
};
typedef union tlb_context_reg tlb_context_reg_t;
 
/** I-/D-TLB Data In/Access Register type. */
typedef tte_data_t tlb_data_t;
 
/** I-/D-TLB Data Access Address in Alternate Space. */
 
#if defined (US)
 
union tlb_data_access_addr {
uint64_t value;
struct {
uint64_t : 55;
unsigned tlb_entry : 6;
unsigned : 3;
} __attribute__ ((packed));
};
typedef union tlb_data_access_addr dtlb_data_access_addr_t;
typedef union tlb_data_access_addr dtlb_tag_read_addr_t;
typedef union tlb_data_access_addr itlb_data_access_addr_t;
typedef union tlb_data_access_addr itlb_tag_read_addr_t;
 
#elif defined (US3)
 
/*
* In US3, I-MMU and D-MMU have different formats of the data
* access register virtual address. In the corresponding
* structures the member variable for the entry number is
* called "local_tlb_entry" - it contrast with the "tlb_entry"
* for the US data access register VA structure. The rationale
* behind this is to prevent careless mistakes in the code
* caused by setting only the entry number and not the TLB
* number in the US3 code (when taking the code from US).
*/
 
union dtlb_data_access_addr {
uint64_t value;
struct {
uint64_t : 45;
unsigned : 1;
unsigned tlb_number : 2;
unsigned : 4;
unsigned local_tlb_entry : 9;
unsigned : 3;
} __attribute__ ((packed));
};
typedef union dtlb_data_access_addr dtlb_data_access_addr_t;
typedef union dtlb_data_access_addr dtlb_tag_read_addr_t;
 
union itlb_data_access_addr {
uint64_t value;
struct {
uint64_t : 45;
unsigned : 1;
unsigned tlb_number : 2;
unsigned : 6;
unsigned local_tlb_entry : 7;
unsigned : 3;
} __attribute__ ((packed));
};
typedef union itlb_data_access_addr itlb_data_access_addr_t;
typedef union itlb_data_access_addr itlb_tag_read_addr_t;
 
#endif
 
/** I-/D-TLB Tag Read Register. */
union tlb_tag_read_reg {
uint64_t value;
struct {
uint64_t vpn : 51; /**< Virtual Address bits 63:13. */
unsigned context : 13; /**< Context identifier. */
} __attribute__ ((packed));
};
typedef union tlb_tag_read_reg tlb_tag_read_reg_t;
typedef union tlb_tag_read_reg tlb_tag_access_reg_t;
 
 
/** TLB Demap Operation Address. */
union tlb_demap_addr {
uint64_t value;
struct {
uint64_t vpn: 51; /**< Virtual Address bits 63:13. */
#if defined (US)
unsigned : 6; /**< Ignored. */
unsigned type : 1; /**< The type of demap operation. */
#elif defined (US3)
unsigned : 5; /**< Ignored. */
unsigned type: 2; /**< The type of demap operation. */
#endif
unsigned context : 2; /**< Context register selection. */
unsigned : 4; /**< Zero. */
} __attribute__ ((packed));
};
typedef union tlb_demap_addr tlb_demap_addr_t;
 
/** TLB Synchronous Fault Status Register. */
union tlb_sfsr_reg {
uint64_t value;
struct {
#if defined (US)
unsigned long : 40; /**< Implementation dependent. */
unsigned asi : 8; /**< ASI. */
unsigned : 2;
unsigned ft : 7; /**< Fault type. */
#elif defined (US3)
unsigned long : 39; /**< Implementation dependent. */
unsigned nf : 1; /**< Non-faulting load. */
unsigned asi : 8; /**< ASI. */
unsigned tm : 1; /**< I-TLB miss. */
unsigned : 3; /**< Reserved. */
unsigned ft : 5; /**< Fault type. */
#endif
unsigned e : 1; /**< Side-effect bit. */
unsigned ct : 2; /**< Context Register selection. */
unsigned pr : 1; /**< Privilege bit. */
unsigned w : 1; /**< Write bit. */
unsigned ow : 1; /**< Overwrite bit. */
unsigned fv : 1; /**< Fault Valid bit. */
} __attribute__ ((packed));
};
typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
 
#if defined (US3)
 
/*
* Functions for determining the number of entries in TLBs. They either return
* a constant value or a value based on the CPU autodetection.
*/
 
/**
* Determine the number od entries in the DMMU's small TLB.
*/
static inline uint16_t tlb_dsmall_size(void)
{
return 16;
}
 
/**
* Determine the number od entries in each DMMU's big TLB.
*/
static inline uint16_t tlb_dbig_size(void)
{
return 512;
}
 
/**
* Determine the number od entries in the IMMU's small TLB.
*/
static inline uint16_t tlb_ismall_size(void)
{
return 16;
}
 
/**
* Determine the number od entries in the IMMU's big TLB.
*/
static inline uint16_t tlb_ibig_size(void)
{
if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
return 512;
else
return 128;
}
 
#endif
 
/** Read MMU Primary Context Register.
*
* @return Current value of Primary Context Register.
*/
static inline uint64_t mmu_primary_context_read(void)
{
return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
*
* @param v New value of Primary Context Register.
*/
static inline void mmu_primary_context_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v);
flush_pipeline();
}
 
/** Read MMU Secondary Context Register.
*
* @return Current value of Secondary Context Register.
*/
static inline uint64_t mmu_secondary_context_read(void)
{
return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG);
}
 
/** Write MMU Primary Context Register.
*
* @param v New value of Primary Context Register.
*/
static inline void mmu_secondary_context_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v);
flush_pipeline();
}
 
#if defined (US)
 
/** Read IMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Data Access Register.
*/
static inline uint64_t itlb_data_access_read(index_t entry)
{
itlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void itlb_data_access_write(index_t entry, uint64_t value)
{
itlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Data Access Register.
*/
static inline uint64_t dtlb_data_access_read(index_t entry)
{
dtlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
*
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void dtlb_data_access_write(index_t entry, uint64_t value)
{
dtlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_entry = entry;
asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
membar();
}
 
/** Read IMMU TLB Tag Read Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Tag Read Register.
*/
static inline uint64_t itlb_tag_read_read(index_t entry)
{
itlb_tag_read_addr_t tag;
 
tag.value = 0;
tag.tlb_entry = entry;
return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
*
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Tag Read Register.
*/
static inline uint64_t dtlb_tag_read_read(index_t entry)
{
dtlb_tag_read_addr_t tag;
 
tag.value = 0;
tag.tlb_entry = entry;
return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
 
#elif defined (US3)
 
 
/** Read IMMU TLB Data Access Register.
*
* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Data Access Register.
*/
static inline uint64_t itlb_data_access_read(int tlb, index_t entry)
{
itlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_number = tlb;
reg.local_tlb_entry = entry;
return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write IMMU TLB Data Access Register.
* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void itlb_data_access_write(int tlb, index_t entry,
uint64_t value)
{
itlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_number = tlb;
reg.local_tlb_entry = entry;
asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value);
flush_pipeline();
}
 
/** Read DMMU TLB Data Access Register.
*
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Data Access Register.
*/
static inline uint64_t dtlb_data_access_read(int tlb, index_t entry)
{
dtlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_number = tlb;
reg.local_tlb_entry = entry;
return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value);
}
 
/** Write DMMU TLB Data Access Register.
*
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
* @param entry TLB Entry index.
* @param value Value to be written.
*/
static inline void dtlb_data_access_write(int tlb, index_t entry,
uint64_t value)
{
dtlb_data_access_addr_t reg;
reg.value = 0;
reg.tlb_number = tlb;
reg.local_tlb_entry = entry;
asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value);
membar();
}
 
/** Read IMMU TLB Tag Read Register.
*
* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Tag Read Register.
*/
static inline uint64_t itlb_tag_read_read(int tlb, index_t entry)
{
itlb_tag_read_addr_t tag;
 
tag.value = 0;
tag.tlb_number = tlb;
tag.local_tlb_entry = entry;
return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value);
}
 
/** Read DMMU TLB Tag Read Register.
*
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Tag Read Register.
*/
static inline uint64_t dtlb_tag_read_read(int tlb, index_t entry)
{
dtlb_tag_read_addr_t tag;
 
tag.value = 0;
tag.tlb_number = tlb;
tag.local_tlb_entry = entry;
return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value);
}
 
#endif
 
 
/** Write IMMU TLB Tag Access Register.
*
* @param v Value to be written.
*/
static inline void itlb_tag_access_write(uint64_t v)
{
asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v);
flush_pipeline();
}
 
/** Read IMMU TLB Tag Access Register.
*
* @return Current value of IMMU TLB Tag Access Register.
*/
static inline uint64_t itlb_tag_access_read(void)
{
return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS);
}
 
/** Write DMMU TLB Tag Access Register.
*
* @param v Value to be written.
*/
static inline void dtlb_tag_access_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v);
membar();
}
 
/** Read DMMU TLB Tag Access Register.
*
* @return Current value of DMMU TLB Tag Access Register.
*/
static inline uint64_t dtlb_tag_access_read(void)
{
return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS);
}
 
 
/** Write IMMU TLB Data in Register.
*
* @param v Value to be written.
*/
static inline void itlb_data_in_write(uint64_t v)
{
asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v);
flush_pipeline();
}
 
/** Write DMMU TLB Data in Register.
*
* @param v Value to be written.
*/
static inline void dtlb_data_in_write(uint64_t v)
{
asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v);
membar();
}
 
/** Read ITLB Synchronous Fault Status Register.
*
* @return Current content of I-SFSR register.
*/
static inline uint64_t itlb_sfsr_read(void)
{
return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR);
}
 
/** Write ITLB Synchronous Fault Status Register.
*
* @param v New value of I-SFSR register.
*/
static inline void itlb_sfsr_write(uint64_t v)
{
asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v);
flush_pipeline();
}
 
/** Read DTLB Synchronous Fault Status Register.
*
* @return Current content of D-SFSR register.
*/
static inline uint64_t dtlb_sfsr_read(void)
{
return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR);
}
 
/** Write DTLB Synchronous Fault Status Register.
*
* @param v New value of D-SFSR register.
*/
static inline void dtlb_sfsr_write(uint64_t v)
{
asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v);
membar();
}
 
/** Read DTLB Synchronous Fault Address Register.
*
* @return Current content of D-SFAR register.
*/
static inline uint64_t dtlb_sfar_read(void)
{
return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR);
}
 
/** Perform IMMU TLB Demap Operation.
*
* @param type
* Selects between context and page demap
* (and entire MMU demap on US3).
* @param context_encoding Specifies which Context register has Context ID for
* demap.
* @param page Address which is on the page to be demapped.
*/
static inline void itlb_demap(int type, int context_encoding, uintptr_t page)
{
tlb_demap_addr_t da;
page_address_t pg;
da.value = 0;
pg.address = page;
da.type = type;
da.context = context_encoding;
da.vpn = pg.vpn;
asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the
* address within the
* ASI */
flush_pipeline();
}
 
/** Perform DMMU TLB Demap Operation.
*
* @param type
* Selects between context and page demap
* (and entire MMU demap on US3).
* @param context_encoding Specifies which Context register has Context ID for
* demap.
* @param page Address which is on the page to be demapped.
*/
static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)
{
tlb_demap_addr_t da;
page_address_t pg;
da.value = 0;
pg.address = page;
da.type = type;
da.context = context_encoding;
da.vpn = pg.vpn;
asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the
* address within the
* ASI */
membar();
}
 
extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate);
extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate);
extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate);
 
extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable);
 
extern void dump_sfsr_and_sfar(void);
 
#endif /* !def __ASM__ */
 
#endif
 
/** @}
*/
/branches/sparc/kernel/arch/sparc64/include/register.h
35,7 → 35,7
#ifndef KERN_sparc64_REGISTER_H_
#define KERN_sparc64_REGISTER_H_
 
#include <arch/regdef.h>
#include <arch/sun4u/regdef.h>
#include <arch/types.h>
 
/** Version Register. */
/branches/sparc/kernel/arch/sparc64/include/cpu.h
56,8 → 56,9
#include <arch/types.h>
#include <typedefs.h>
#include <arch/register.h>
#include <arch/regdef.h>
#include <arch/sun4u/regdef.h>
#include <arch/asm.h>
#include <arch/sun4u/arch.h>
 
#ifdef CONFIG_SMP
#include <arch/mm/cache.h>
88,6 → 89,9
return icbus_config & 0x1f;
else
return icbus_config & 0x3ff;
#else
panic("Not implemented for this architecture.");
return 0;
#endif
}
 
/branches/sparc/kernel/arch/sparc64/include/drivers/niagara.h
0,0 → 1,45
/*
* Copyright (c) 2008 Pavel Rimsky
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup sparc64
* @{
*/
/** @file
*/
 
#ifndef KERN_sparc64_NIAGARA_H
#define KERN_sparc64_NIAGARA_H
 
void niagara_grab(void);
void niagara_release(void);
void niagara_init(void);
 
#endif
 
/** @}
*/
/branches/sparc/kernel/arch/sparc64/include/sun4u/regdef.h
0,0 → 1,67
/*
* Copyright (c) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup sparc64
* @{
*/
/** @file
*/
 
#ifndef KERN_sparc64_sun4u_REGDEF_H_
#define KERN_sparc64_sun4u_REGDEF_H_
 
#define PSTATE_IE_BIT (1 << 1)
#define PSTATE_AM_BIT (1 << 3)
 
#define PSTATE_AG_BIT (1 << 0)
#define PSTATE_IG_BIT (1 << 11)
#define PSTATE_MG_BIT (1 << 10)
 
#define PSTATE_PRIV_BIT (1 << 2)
#define PSTATE_PEF_BIT (1 << 4)
 
#define TSTATE_PSTATE_SHIFT 8
#define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT << TSTATE_PSTATE_SHIFT)
#define TSTATE_IE_BIT (PSTATE_IE_BIT << TSTATE_PSTATE_SHIFT)
#define TSTATE_PEF_BIT (PSTATE_PEF_BIT << TSTATE_PSTATE_SHIFT)
 
#define TSTATE_CWP_MASK 0x1f
 
#define WSTATE_NORMAL(n) (n)
#define WSTATE_OTHER(n) ((n) << 3)
 
/*
* The following definitions concern the UPA_CONFIG register on US and the
* FIREPLANE_CONFIG register on US3.
*/
#define ICBUS_CONFIG_MID_SHIFT 17
 
#endif
 
/** @}
*/
/branches/sparc/kernel/arch/sparc64/include/sun4u/arch.h
0,0 → 1,47
/*
* Copyright (c) 2005 Jakub Jermar
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup sparc64
* @{
*/
/**
* @file
* @brief Various sun4u-specific macros.
*/
 
#ifndef KERN_sparc64_sun4u_ARCH_H_
#define KERN_sparc64_sun4u_ARCH_H_
 
#define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */
#define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */
#define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */
 
#endif
 
/** @}
*/