| /branches/sparc/kernel/arch/sparc64/include/regdef.h |
|---|
| 60,11 → 60,6 |
| * FIREPLANE_CONFIG register on US3. |
| */ |
| #define ICBUS_CONFIG_MID_SHIFT 17 |
| #if defined (US) |
| #define ICBUS_CONFIG_MID_MASK 0x1f |
| #elif defined (US3) |
| #define ICBUS_CONFIG_MID_MASK 0x3ff |
| #endif |
| #endif |
| /branches/sparc/kernel/arch/sparc64/include/asm.h |
|---|
| 136,6 → 136,28 |
| asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
| } |
| /** Read STICK_compare Register. |
| * |
| * @return Value of STICK_compare register. |
| */ |
| static inline uint64_t stick_compare_read(void) |
| { |
| uint64_t v; |
| asm volatile ("rd %%asr25, %0\n" : "=r" (v)); |
| return v; |
| } |
| /** Write STICK_compare Register. |
| * |
| * @param v New value of STICK_comapre register. |
| */ |
| static inline void stick_compare_write(uint64_t v) |
| { |
| asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0)); |
| } |
| /** Read TICK Register. |
| * |
| * @return Value of TICK register. |
| 407,17 → 429,6 |
| asm volatile ("wrpr %g0, %g0, %tl\n"); |
| } |
| /** Read UPA_CONFIG/FIREPLANE_CONFIG register. |
| * |
| * @return |
| * Value of the UPA_CONFIG register in US, |
| * value of the FIREPLANE_CONFIG on US3. |
| */ |
| static inline uint64_t icbus_config_read(void) |
| { |
| return asi_u64_read(ASI_ICBUS_CONFIG, 0); |
| } |
| extern void cpu_halt(void); |
| extern void cpu_sleep(void); |
| extern void asm_delay_loop(const uint32_t usec); |
| /branches/sparc/kernel/arch/sparc64/include/register.h |
|---|
| 117,30 → 117,7 |
| }; |
| typedef union fprs_reg fprs_reg_t; |
| /** UPA_CONFIG/FIREPLANE_CONFIG register. |
| * |
| * Note that format of this register differs significantly from |
| * processor version to version. The format defined here |
| * is the common subset for all supported processor versions. |
| */ |
| union icbus_config { |
| uint64_t value; |
| struct { |
| #if defined (US) |
| uint64_t : 34; |
| unsigned pcon : 8; /**< Processor configuration. */ |
| unsigned mid : 5; /**< Module (processor) ID register. */ |
| unsigned pcap : 17; /**< Processor capabilities. */ |
| #elif defined (US3) |
| uint64_t : 37; |
| unsigned mid : 10; /**< Agent ID in US-IV+ manual.*/ |
| uint64_t : 17; |
| #endif |
| } __attribute__ ((packed)); |
| }; |
| typedef union icbus_config icbus_config_t; |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/cpu.h |
|---|
| 35,15 → 35,6 |
| #ifndef KERN_sparc64_CPU_H_ |
| #define KERN_sparc64_CPU_H_ |
| #include <arch/types.h> |
| #include <typedefs.h> |
| #include <arch/register.h> |
| #include <arch/asm.h> |
| #ifdef CONFIG_SMP |
| #include <arch/mm/cache.h> |
| #endif |
| #define MANUF_FUJITSU 0x04 |
| #define MANUF_ULTRASPARC 0x17 /**< UltraSPARC I, UltraSPARC II */ |
| #define MANUF_SUN 0x3e |
| 60,6 → 51,18 |
| #define IMPL_SPARC64V 0x5 |
| #ifndef __ASM__ |
| #include <arch/types.h> |
| #include <typedefs.h> |
| #include <arch/register.h> |
| #include <arch/regdef.h> |
| #include <arch/asm.h> |
| #ifdef CONFIG_SMP |
| #include <arch/mm/cache.h> |
| #endif |
| typedef struct { |
| uint32_t mid; /**< Processor ID as read from |
| UPA_CONFIG/FIREPLANE_CONFIG. */ |
| 69,8 → 72,28 |
| generated when the TICK register |
| matches this value. */ |
| } cpu_arch_t; |
| /** |
| * Reads the module ID (agent ID/CPUID) of the current CPU. |
| */ |
| static inline uint32_t read_mid(void) |
| { |
| uint64_t icbus_config = asi_u64_read(ASI_ICBUS_CONFIG, 0); |
| icbus_config = icbus_config >> ICBUS_CONFIG_MID_SHIFT; |
| #if defined (US) |
| return icbus_config & 0x1f; |
| #elif defined (US3) |
| if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIII_I) |
| return icbus_config & 0x1f; |
| else |
| return icbus_config & 0x3ff; |
| #endif |
| } |
| #endif |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/drivers/scr.h |
|---|
| 42,7 → 42,8 |
| SCR_UNKNOWN, |
| SCR_ATYFB, |
| SCR_FFB, |
| SCR_CGSIX |
| SCR_CGSIX, |
| SCR_XVR |
| } scr_type_t; |
| extern scr_type_t scr_type; |