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Ignore whitespace Rev 3590 → Rev 3591

/branches/sparc/kernel/arch/sparc64/include/mm/cache_spec.h
51,16 → 51,7
#endif
#define DCACHE_LINE_SIZE 32
 
#if defined (US)
#define ICACHE_SIZE (16 * 1024)
#define ICACHE_WAYS 2
#elif defined (US3)
#define ICACHE_SIZE (32 * 1024)
#define ICACHE_WAYS 4
#endif
#define ICACHE_LINE_SIZE 32
 
#endif
 
/** @}
*/
*/
/branches/sparc/kernel/arch/sparc64/include/mm/tlb.h
41,7 → 41,7
#define DTLB_MAX_LOCKED_ENTRIES DTLB_ENTRY_COUNT
#endif
 
/** DT16 is the only of the three DMMUs that can hold locked entries. */
/** TLB_DSMALL is the only of the three DMMUs that can hold locked entries. */
#if defined (US3)
#define DTLB_MAX_LOCKED_ENTRIES 16
#endif
74,14 → 74,14
 
/* There are more TLBs in one MMU in US3, their codes are defined here. */
#if defined (US3)
/* D-MMU: one 16-entry TLB and two 512-entry TLBs */
#define TLB_DT16 0
#define TLB_DT512_0 2
#define TLB_DT512_1 3
/* D-MMU: one small (16-entry) TLB and two big (512-entry) TLBs */
#define TLB_DSMALL 0
#define TLB_DBIG_0 2
#define TLB_DBIG_1 3
/* I-MMU: one 16-entry TLB and one 128-entry TLB */
#define TLB_IT16 0
#define TLB_IT128 2
/* I-MMU: one small (16-entry) TLB and one big TLB */
#define TLB_ISMALL 0
#define TLB_IBIG 2
#endif
 
#define TLB_DEMAP_CONTEXT_SHIFT 4
99,6 → 99,8
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
#include <arch/register.h>
#include <arch/cpu.h>
 
union tlb_context_reg {
uint64_t v;
230,6 → 232,50
};
typedef union tlb_sfsr_reg tlb_sfsr_reg_t;
 
#if defined (US3)
 
/*
* Functions for determining the number of entries in TLBs. They either return
* a constant value or a value based on the CPU autodetection.
*/
 
/**
* Determine the number od entries in the DMMU's small TLB.
*/
static inline uint16_t tlb_dsmall_size(void)
{
return 16;
}
 
/**
* Determine the number od entries in each DMMU's big TLB.
*/
static inline uint16_t tlb_dbig_size(void)
{
return 512;
}
 
/**
* Determine the number od entries in the IMMU's small TLB.
*/
static inline uint16_t tlb_ismall_size(void)
{
return 16;
}
 
/**
* Determine the number od entries in the IMMU's big TLB.
*/
static inline uint16_t tlb_ibig_size(void)
{
if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS)
return 512;
else
return 128;
}
 
#endif
 
/** Read MMU Primary Context Register.
*
* @return Current value of Primary Context Register.
365,7 → 411,7
 
/** Read IMMU TLB Data Access Register.
*
* @param tlb TLB number (one of TLB_IT16 or TLB_IT128)
* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Data Access Register.
381,7 → 427,7
}
 
/** Write IMMU TLB Data Access Register.
* @param tlb TLB number (one of TLB_IT16 or TLB_IT128)
* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
* @param entry TLB Entry index.
* @param value Value to be written.
*/
398,7 → 444,7
 
/** Read DMMU TLB Data Access Register.
*
* @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1)
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG, TLB_DBIG)
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Data Access Register.
415,7 → 461,7
 
/** Write DMMU TLB Data Access Register.
*
* @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1)
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
* @param entry TLB Entry index.
* @param value Value to be written.
*/
432,7 → 478,7
 
/** Read IMMU TLB Tag Read Register.
*
* @param tlb TLB number (one of TLB_IT16 or TLB_IT128)
* @param tlb TLB number (one of TLB_ISMALL or TLB_IBIG)
* @param entry TLB Entry index.
*
* @return Current value of specified IMMU TLB Tag Read Register.
449,7 → 495,7
 
/** Read DMMU TLB Tag Read Register.
*
* @param tlb TLB number (one of TLB_DT16, TLB_DT512_0, TLB_DT512_1)
* @param tlb TLB number (one of TLB_DSMALL, TLB_DBIG_0, TLB_DBIG_1)
* @param entry TLB Entry index.
*
* @return Current value of specified DMMU TLB Tag Read Register.
/branches/sparc/kernel/arch/sparc64/include/mm/cache.h
38,15 → 38,6
#include <mm/page.h>
#include <mm/frame.h>
 
#define dcache_flush_page(p) \
dcache_flush_color(PAGE_COLOR((p)))
#define dcache_flush_frame(p, f) \
dcache_flush_tag(PAGE_COLOR((p)), ADDR2PFN((f)));
 
extern void dcache_flush(void);
extern void dcache_flush_color(int c);
extern void dcache_flush_tag(int c, pfn_t tag);
 
#endif
 
/** @}
/branches/sparc/kernel/arch/sparc64/include/register.h
133,7 → 133,7
unsigned pcap : 17; /**< Processor capabilities. */
#elif defined (US3)
uint64_t : 37;
unsigned mid : 10; /**< Module (processor) ID register. */
unsigned mid : 10; /**< Agent ID in US-IV+ manual.*/
uint64_t : 17;
#endif
} __attribute__ ((packed));