| /branches/sparc/kernel/arch/sparc64/include/regdef.h |
|---|
| 59,8 → 59,8 |
| * The following definitions concern the UPA_CONFIG register on US and the |
| * FIREPLANE_CONFIG register on US3. |
| */ |
| #define UPA_CONFIG_MID_SHIFT 17 |
| #define UPA_CONFIG_MID_MASK 0x1f |
| #define ICBUS_CONFIG_MID_SHIFT 17 |
| #define ICBUS_CONFIG_MID_MASK 0x1f |
| #endif |
| /branches/sparc/kernel/arch/sparc64/include/arch.h |
|---|
| 41,7 → 41,7 |
| #define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ |
| #define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ |
| #define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ |
| #define ASI_UPA_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ |
| #define ASI_ICBUS_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ |
| #define NWINDOWS 8 /** Number of register window sets. */ |
| /branches/sparc/kernel/arch/sparc64/include/asm.h |
|---|
| 364,9 → 364,9 |
| * Value of the UPA_CONFIG register in US, |
| * value of the FIREPLANE_CONFIG on US3. |
| */ |
| static inline uint64_t upa_config_read(void) |
| static inline uint64_t icbus_config_read(void) |
| { |
| return asi_u64_read(ASI_UPA_CONFIG, 0); |
| return asi_u64_read(ASI_ICBUS_CONFIG, 0); |
| } |
| extern void cpu_halt(void); |
| /branches/sparc/kernel/arch/sparc64/include/register.h |
|---|
| 123,7 → 123,7 |
| * processor version to version. The format defined here |
| * is the common subset for all supported processor versions. |
| */ |
| union upa_config { |
| union icbus_config { |
| uint64_t value; |
| struct { |
| uint64_t : 34; |
| 132,7 → 132,7 |
| unsigned pcap : 17; /**< Processor capabilities. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union upa_config upa_config_t; |
| typedef union icbus_config icbus_config_t; |
| #endif |
| /branches/sparc/kernel/arch/sparc64/include/cpu.h |
|---|
| 52,7 → 52,10 |
| #define IMPL_ULTRASPARCII 0x11 |
| #define IMPL_ULTRASPARCII_I 0x12 |
| #define IMPL_ULTRASPARCII_E 0x13 |
| #define IMPL_ULTRASPARCIII 0x15 |
| #define IMPL_ULTRASPARCIII 0x14 |
| #define IMPL_ULTRASPARCIII_PLUS 0x15 |
| #define IMPL_ULTRASPARCIII_I 0x16 |
| #define IMPL_ULTRASPARCIV 0x18 |
| #define IMPL_ULTRASPARCIV_PLUS 0x19 |
| #define IMPL_SPARC64V 0x5 |