| /branches/sparc/kernel/arch/sparc64/include/regdef.h |
|---|
| 55,6 → 55,10 |
| #define WSTATE_NORMAL(n) (n) |
| #define WSTATE_OTHER(n) ((n) << 3) |
| /* |
| * The following definitions concern the UPA_CONFIG register on US and the |
| * FIREPLANE_CONFIG register on US3. |
| */ |
| #define UPA_CONFIG_MID_SHIFT 17 |
| #define UPA_CONFIG_MID_MASK 0x1f |
| /branches/sparc/kernel/arch/sparc64/include/arch.h |
|---|
| 41,7 → 41,7 |
| #define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ |
| #define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ |
| #define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ |
| #define ASI_UPA_CONFIG 0x4a /** ASI of the UPA_CONFIG register. */ |
| #define ASI_UPA_CONFIG 0x4a /** ASI of the UPA_CONFIG/FIREPLANE_CONFIG register. */ |
| #define NWINDOWS 8 /** Number of register window sets. */ |
| /branches/sparc/kernel/arch/sparc64/include/asm.h |
|---|
| 358,9 → 358,11 |
| asm volatile ("wrpr %g0, %g0, %tl\n"); |
| } |
| /** Read UPA_CONFIG register. |
| /** Read UPA_CONFIG/FIREPLANE_CONFIG register. |
| * |
| * @return Value of the UPA_CONFIG register. |
| * @return |
| * Value of the UPA_CONFIG register in US, |
| * value of the FIREPLANE_CONFIG on US3. |
| */ |
| static inline uint64_t upa_config_read(void) |
| { |
| /branches/sparc/kernel/arch/sparc64/include/register.h |
|---|
| 117,7 → 117,7 |
| }; |
| typedef union fprs_reg fprs_reg_t; |
| /** UPA_CONFIG register. |
| /** UPA_CONFIG/FIREPLANE_CONFIG register. |
| * |
| * Note that format of this register differs significantly from |
| * processor version to version. The format defined here |
| /branches/sparc/kernel/arch/sparc64/include/cpu.h |
|---|
| 59,7 → 59,7 |
| typedef struct { |
| uint32_t mid; /**< Processor ID as read from |
| UPA_CONFIG. */ |
| UPA_CONFIG/FIREPLANE_CONFIG. */ |
| ver_reg_t ver; |
| uint32_t clock_frequency; /**< Processor frequency in Hz. */ |
| uint64_t next_tick_cmpr; /**< Next clock interrupt should be |