| /branches/sparc/kernel/arch/sparc64/include/mm/page.h |
|---|
| 0,0 → 1,84 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_PAGE_H_ |
| #define KERN_sparc64_PAGE_H_ |
| #include <arch/mm/frame.h> |
| /* |
| * On the TLB and TSB level, we still use 8K pages, which are supported by the |
| * MMU. |
| */ |
| #define MMU_PAGE_WIDTH MMU_FRAME_WIDTH |
| #define MMU_PAGE_SIZE MMU_FRAME_SIZE |
| /* |
| * On the page table level, we use 16K pages. 16K pages are not supported by |
| * the MMU but we emulate them with pairs of 8K pages. |
| */ |
| #define PAGE_WIDTH FRAME_WIDTH |
| #define PAGE_SIZE FRAME_SIZE |
| #define MMU_PAGES_PER_PAGE (1 << (PAGE_WIDTH - MMU_PAGE_WIDTH)) |
| #ifdef KERNEL |
| #ifndef __ASM__ |
| #include <arch/interrupt.h> |
| extern uintptr_t physmem_base; |
| #define KA2PA(x) (((uintptr_t) (x)) + physmem_base) |
| #define PA2KA(x) (((uintptr_t) (x)) - physmem_base) |
| typedef union { |
| uintptr_t address; |
| struct { |
| uint64_t vpn : 51; /**< Virtual Page Number. */ |
| unsigned offset : 13; /**< Offset. */ |
| } __attribute__ ((packed)); |
| } page_address_t; |
| extern void page_arch_init(void); |
| #endif /* !def __ASM__ */ |
| #endif /* KERNEL */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/tlb.h |
|---|
| 0,0 → 1,444 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_TLB_H_ |
| #define KERN_sparc64_TLB_H_ |
| #define ITLB_ENTRY_COUNT 64 |
| #define DTLB_ENTRY_COUNT 64 |
| #define MEM_CONTEXT_KERNEL 0 |
| #define MEM_CONTEXT_TEMP 1 |
| /** Page sizes. */ |
| #define PAGESIZE_8K 0 |
| #define PAGESIZE_64K 1 |
| #define PAGESIZE_512K 2 |
| #define PAGESIZE_4M 3 |
| /** Bit width of the TLB-locked portion of kernel address space. */ |
| #define KERNEL_PAGE_WIDTH 22 /* 4M */ |
| /* TLB Demap Operation types. */ |
| #define TLB_DEMAP_PAGE 0 |
| #define TLB_DEMAP_CONTEXT 1 |
| #define TLB_DEMAP_TYPE_SHIFT 6 |
| /* TLB Demap Operation Context register encodings. */ |
| #define TLB_DEMAP_PRIMARY 0 |
| #define TLB_DEMAP_SECONDARY 1 |
| #define TLB_DEMAP_NUCLEUS 2 |
| #define TLB_DEMAP_CONTEXT_SHIFT 4 |
| /* TLB Tag Access shifts */ |
| #define TLB_TAG_ACCESS_CONTEXT_SHIFT 0 |
| #define TLB_TAG_ACCESS_CONTEXT_MASK ((1 << 13) - 1) |
| #define TLB_TAG_ACCESS_VPN_SHIFT 13 |
| #ifndef __ASM__ |
| #include <arch/mm/tte.h> |
| #include <arch/mm/mmu.h> |
| #include <arch/mm/page.h> |
| #include <arch/asm.h> |
| #include <arch/barrier.h> |
| #include <arch/types.h> |
| union tlb_context_reg { |
| uint64_t v; |
| struct { |
| unsigned long : 51; |
| unsigned context : 13; /**< Context/ASID. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tlb_context_reg tlb_context_reg_t; |
| /** I-/D-TLB Data In/Access Register type. */ |
| typedef tte_data_t tlb_data_t; |
| /** I-/D-TLB Data Access Address in Alternate Space. */ |
| union tlb_data_access_addr { |
| uint64_t value; |
| struct { |
| uint64_t : 55; |
| unsigned tlb_entry : 6; |
| unsigned : 3; |
| } __attribute__ ((packed)); |
| }; |
| typedef union tlb_data_access_addr tlb_data_access_addr_t; |
| typedef union tlb_data_access_addr tlb_tag_read_addr_t; |
| /** I-/D-TLB Tag Read Register. */ |
| union tlb_tag_read_reg { |
| uint64_t value; |
| struct { |
| uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
| unsigned context : 13; /**< Context identifier. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
| typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
| /** TLB Demap Operation Address. */ |
| union tlb_demap_addr { |
| uint64_t value; |
| struct { |
| uint64_t vpn: 51; /**< Virtual Address bits 63:13. */ |
| unsigned : 6; /**< Ignored. */ |
| unsigned type : 1; /**< The type of demap operation. */ |
| unsigned context : 2; /**< Context register selection. */ |
| unsigned : 4; /**< Zero. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tlb_demap_addr tlb_demap_addr_t; |
| /** TLB Synchronous Fault Status Register. */ |
| union tlb_sfsr_reg { |
| uint64_t value; |
| struct { |
| unsigned long : 40; /**< Implementation dependent. */ |
| unsigned asi : 8; /**< ASI. */ |
| unsigned : 2; |
| unsigned ft : 7; /**< Fault type. */ |
| unsigned e : 1; /**< Side-effect bit. */ |
| unsigned ct : 2; /**< Context Register selection. */ |
| unsigned pr : 1; /**< Privilege bit. */ |
| unsigned w : 1; /**< Write bit. */ |
| unsigned ow : 1; /**< Overwrite bit. */ |
| unsigned fv : 1; /**< Fault Valid bit. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tlb_sfsr_reg tlb_sfsr_reg_t; |
| /** Read MMU Primary Context Register. |
| * |
| * @return Current value of Primary Context Register. |
| */ |
| static inline uint64_t mmu_primary_context_read(void) |
| { |
| return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); |
| } |
| /** Write MMU Primary Context Register. |
| * |
| * @param v New value of Primary Context Register. |
| */ |
| static inline void mmu_primary_context_write(uint64_t v) |
| { |
| asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); |
| flush_pipeline(); |
| } |
| /** Read MMU Secondary Context Register. |
| * |
| * @return Current value of Secondary Context Register. |
| */ |
| static inline uint64_t mmu_secondary_context_read(void) |
| { |
| return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); |
| } |
| /** Write MMU Primary Context Register. |
| * |
| * @param v New value of Primary Context Register. |
| */ |
| static inline void mmu_secondary_context_write(uint64_t v) |
| { |
| asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); |
| flush_pipeline(); |
| } |
| /** Read IMMU TLB Data Access Register. |
| * |
| * @param entry TLB Entry index. |
| * |
| * @return Current value of specified IMMU TLB Data Access Register. |
| */ |
| static inline uint64_t itlb_data_access_read(index_t entry) |
| { |
| tlb_data_access_addr_t reg; |
| reg.value = 0; |
| reg.tlb_entry = entry; |
| return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
| } |
| /** Write IMMU TLB Data Access Register. |
| * |
| * @param entry TLB Entry index. |
| * @param value Value to be written. |
| */ |
| static inline void itlb_data_access_write(index_t entry, uint64_t value) |
| { |
| tlb_data_access_addr_t reg; |
| reg.value = 0; |
| reg.tlb_entry = entry; |
| asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
| flush_pipeline(); |
| } |
| /** Read DMMU TLB Data Access Register. |
| * |
| * @param entry TLB Entry index. |
| * |
| * @return Current value of specified DMMU TLB Data Access Register. |
| */ |
| static inline uint64_t dtlb_data_access_read(index_t entry) |
| { |
| tlb_data_access_addr_t reg; |
| reg.value = 0; |
| reg.tlb_entry = entry; |
| return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
| } |
| /** Write DMMU TLB Data Access Register. |
| * |
| * @param entry TLB Entry index. |
| * @param value Value to be written. |
| */ |
| static inline void dtlb_data_access_write(index_t entry, uint64_t value) |
| { |
| tlb_data_access_addr_t reg; |
| reg.value = 0; |
| reg.tlb_entry = entry; |
| asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
| membar(); |
| } |
| /** Read IMMU TLB Tag Read Register. |
| * |
| * @param entry TLB Entry index. |
| * |
| * @return Current value of specified IMMU TLB Tag Read Register. |
| */ |
| static inline uint64_t itlb_tag_read_read(index_t entry) |
| { |
| tlb_tag_read_addr_t tag; |
| tag.value = 0; |
| tag.tlb_entry = entry; |
| return asi_u64_read(ASI_ITLB_TAG_READ_REG, tag.value); |
| } |
| /** Read DMMU TLB Tag Read Register. |
| * |
| * @param entry TLB Entry index. |
| * |
| * @return Current value of specified DMMU TLB Tag Read Register. |
| */ |
| static inline uint64_t dtlb_tag_read_read(index_t entry) |
| { |
| tlb_tag_read_addr_t tag; |
| tag.value = 0; |
| tag.tlb_entry = entry; |
| return asi_u64_read(ASI_DTLB_TAG_READ_REG, tag.value); |
| } |
| /** Write IMMU TLB Tag Access Register. |
| * |
| * @param v Value to be written. |
| */ |
| static inline void itlb_tag_access_write(uint64_t v) |
| { |
| asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); |
| flush_pipeline(); |
| } |
| /** Read IMMU TLB Tag Access Register. |
| * |
| * @return Current value of IMMU TLB Tag Access Register. |
| */ |
| static inline uint64_t itlb_tag_access_read(void) |
| { |
| return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); |
| } |
| /** Write DMMU TLB Tag Access Register. |
| * |
| * @param v Value to be written. |
| */ |
| static inline void dtlb_tag_access_write(uint64_t v) |
| { |
| asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); |
| membar(); |
| } |
| /** Read DMMU TLB Tag Access Register. |
| * |
| * @return Current value of DMMU TLB Tag Access Register. |
| */ |
| static inline uint64_t dtlb_tag_access_read(void) |
| { |
| return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); |
| } |
| /** Write IMMU TLB Data in Register. |
| * |
| * @param v Value to be written. |
| */ |
| static inline void itlb_data_in_write(uint64_t v) |
| { |
| asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); |
| flush_pipeline(); |
| } |
| /** Write DMMU TLB Data in Register. |
| * |
| * @param v Value to be written. |
| */ |
| static inline void dtlb_data_in_write(uint64_t v) |
| { |
| asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
| membar(); |
| } |
| /** Read ITLB Synchronous Fault Status Register. |
| * |
| * @return Current content of I-SFSR register. |
| */ |
| static inline uint64_t itlb_sfsr_read(void) |
| { |
| return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); |
| } |
| /** Write ITLB Synchronous Fault Status Register. |
| * |
| * @param v New value of I-SFSR register. |
| */ |
| static inline void itlb_sfsr_write(uint64_t v) |
| { |
| asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); |
| flush_pipeline(); |
| } |
| /** Read DTLB Synchronous Fault Status Register. |
| * |
| * @return Current content of D-SFSR register. |
| */ |
| static inline uint64_t dtlb_sfsr_read(void) |
| { |
| return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); |
| } |
| /** Write DTLB Synchronous Fault Status Register. |
| * |
| * @param v New value of D-SFSR register. |
| */ |
| static inline void dtlb_sfsr_write(uint64_t v) |
| { |
| asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); |
| membar(); |
| } |
| /** Read DTLB Synchronous Fault Address Register. |
| * |
| * @return Current content of D-SFAR register. |
| */ |
| static inline uint64_t dtlb_sfar_read(void) |
| { |
| return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); |
| } |
| /** Perform IMMU TLB Demap Operation. |
| * |
| * @param type Selects between context and page demap. |
| * @param context_encoding Specifies which Context register has Context ID for |
| * demap. |
| * @param page Address which is on the page to be demapped. |
| */ |
| static inline void itlb_demap(int type, int context_encoding, uintptr_t page) |
| { |
| tlb_demap_addr_t da; |
| page_address_t pg; |
| da.value = 0; |
| pg.address = page; |
| da.type = type; |
| da.context = context_encoding; |
| da.vpn = pg.vpn; |
| asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); /* da.value is the |
| * address within the |
| * ASI */ |
| flush_pipeline(); |
| } |
| /** Perform DMMU TLB Demap Operation. |
| * |
| * @param type Selects between context and page demap. |
| * @param context_encoding Specifies which Context register has Context ID for |
| * demap. |
| * @param page Address which is on the page to be demapped. |
| */ |
| static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) |
| { |
| tlb_demap_addr_t da; |
| page_address_t pg; |
| da.value = 0; |
| pg.address = page; |
| da.type = type; |
| da.context = context_encoding; |
| da.vpn = pg.vpn; |
| asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); /* da.value is the |
| * address within the |
| * ASI */ |
| membar(); |
| } |
| extern void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate); |
| extern void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate); |
| extern void fast_data_access_protection(tlb_tag_access_reg_t tag , istate_t *istate); |
| extern void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool locked, bool cacheable); |
| extern void dump_sfsr_and_sfar(void); |
| #endif /* !def __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/cache_spec.h |
|---|
| 0,0 → 1,57 |
| /* |
| * Copyright (c) 2008 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_CACHE_SPEC_H_ |
| #define KERN_sparc64_CACHE_SPEC_H_ |
| /* |
| * The following macros are valid for the following processors: |
| * |
| * UltraSPARC, UltraSPARC II, UltraSPARC IIi |
| * |
| * Should we support other UltraSPARC processors, we need to make sure that |
| * the macros are defined correctly for them. |
| */ |
| #define DCACHE_SIZE (16 * 1024) |
| #define DCACHE_LINE_SIZE 32 |
| #define ICACHE_SIZE (16 * 1024) |
| #define ICACHE_WAYS 2 |
| #define ICACHE_LINE_SIZE 32 |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/frame.h |
|---|
| 0,0 → 1,80 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_FRAME_H_ |
| #define KERN_sparc64_FRAME_H_ |
| /* |
| * Page size supported by the MMU. |
| * For 8K there is the nasty illegal virtual aliasing problem. |
| * Therefore, the kernel uses 8K only internally on the TLB and TSB levels. |
| */ |
| #define MMU_FRAME_WIDTH 13 /* 8K */ |
| #define MMU_FRAME_SIZE (1 << MMU_FRAME_WIDTH) |
| /* |
| * Page size exported to the generic memory management subsystems. |
| * This page size is not directly supported by the MMU, but we can emulate |
| * each 16K page with a pair of adjacent 8K pages. |
| */ |
| #define FRAME_WIDTH 14 /* 16K */ |
| #define FRAME_SIZE (1 << FRAME_WIDTH) |
| #ifdef KERNEL |
| #ifndef __ASM__ |
| #include <arch/types.h> |
| union frame_address { |
| uintptr_t address; |
| struct { |
| unsigned : 23; |
| uint64_t pfn : 28; /**< Physical Frame Number. */ |
| unsigned offset : 13; /**< Offset. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union frame_address frame_address_t; |
| extern uintptr_t last_frame; |
| extern void frame_arch_init(void); |
| #define physmem_print() |
| #endif |
| #endif |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/as.h |
|---|
| 0,0 → 1,96 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_AS_H_ |
| #define KERN_sparc64_AS_H_ |
| #include <arch/mm/tte.h> |
| #define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1 |
| #define KERNEL_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 |
| #define KERNEL_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff |
| #define USER_ADDRESS_SPACE_START_ARCH (unsigned long) 0x0000000000000000 |
| #define USER_ADDRESS_SPACE_END_ARCH (unsigned long) 0xffffffffffffffff |
| #define USTACK_ADDRESS_ARCH (0xffffffffffffffffULL - (PAGE_SIZE - 1)) |
| #ifdef CONFIG_TSB |
| /** TSB Tag Target register. */ |
| typedef union tsb_tag_target { |
| uint64_t value; |
| struct { |
| unsigned invalid : 1; /**< Invalidated by software. */ |
| unsigned : 2; |
| unsigned context : 13; /**< Software ASID. */ |
| unsigned : 6; |
| uint64_t va_tag : 42; /**< Virtual address bits <63:22>. */ |
| } __attribute__ ((packed)); |
| } tsb_tag_target_t; |
| /** TSB entry. */ |
| typedef struct tsb_entry { |
| tsb_tag_target_t tag; |
| tte_data_t data; |
| } __attribute__ ((packed)) tsb_entry_t; |
| typedef struct { |
| tsb_entry_t *itsb; |
| tsb_entry_t *dtsb; |
| } as_arch_t; |
| #else |
| typedef struct { |
| } as_arch_t; |
| #endif /* CONFIG_TSB */ |
| #include <genarch/mm/as_ht.h> |
| #ifdef CONFIG_TSB |
| #include <arch/mm/tsb.h> |
| #define as_invalidate_translation_cache(as, page, cnt) \ |
| tsb_invalidate((as), (page), (cnt)) |
| #else |
| #define as_invalidate_translation_cache(as, page, cnt) |
| #endif |
| extern void as_arch_init(void); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/cache.h |
|---|
| 0,0 → 1,53 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_CACHE_H_ |
| #define KERN_sparc64_CACHE_H_ |
| #include <mm/page.h> |
| #include <mm/frame.h> |
| #define dcache_flush_page(p) \ |
| dcache_flush_color(PAGE_COLOR((p))) |
| #define dcache_flush_frame(p, f) \ |
| dcache_flush_tag(PAGE_COLOR((p)), ADDR2PFN((f))); |
| extern void dcache_flush(void); |
| extern void dcache_flush_color(int c); |
| extern void dcache_flush_tag(int c, pfn_t tag); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/tsb.h |
|---|
| 0,0 → 1,123 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_TSB_H_ |
| #define KERN_sparc64_TSB_H_ |
| /* |
| * ITSB abd DTSB will claim 64K of memory, which |
| * is a nice number considered that it is one of |
| * the page sizes supported by hardware, which, |
| * again, is nice because TSBs need to be locked |
| * in TLBs - only one TLB entry will do. |
| */ |
| #define TSB_SIZE 2 /* when changing this, change |
| * as.c as well */ |
| #define ITSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) |
| #define DTSB_ENTRY_COUNT (512 * (1 << TSB_SIZE)) |
| #define TSB_TAG_TARGET_CONTEXT_SHIFT 48 |
| #ifndef __ASM__ |
| #include <arch/mm/tte.h> |
| #include <arch/mm/mmu.h> |
| #include <arch/types.h> |
| /** TSB Base register. */ |
| typedef union tsb_base_reg { |
| uint64_t value; |
| struct { |
| uint64_t base : 51; /**< TSB base address, bits 63:13. */ |
| unsigned split : 1; /**< Split vs. common TSB for 8K and 64K |
| * pages. HelenOS uses only 8K pages |
| * for user mappings, so we always set |
| * this to 0. |
| */ |
| unsigned : 9; |
| unsigned size : 3; /**< TSB size. Number of entries is |
| * 512 * 2^size. */ |
| } __attribute__ ((packed)); |
| } tsb_base_reg_t; |
| /** Read ITSB Base register. |
| * |
| * @return Content of the ITSB Base register. |
| */ |
| static inline uint64_t itsb_base_read(void) |
| { |
| return asi_u64_read(ASI_IMMU, VA_IMMU_TSB_BASE); |
| } |
| /** Read DTSB Base register. |
| * |
| * @return Content of the DTSB Base register. |
| */ |
| static inline uint64_t dtsb_base_read(void) |
| { |
| return asi_u64_read(ASI_DMMU, VA_DMMU_TSB_BASE); |
| } |
| /** Write ITSB Base register. |
| * |
| * @param v New content of the ITSB Base register. |
| */ |
| static inline void itsb_base_write(uint64_t v) |
| { |
| asi_u64_write(ASI_IMMU, VA_IMMU_TSB_BASE, v); |
| } |
| /** Write DTSB Base register. |
| * |
| * @param v New content of the DTSB Base register. |
| */ |
| static inline void dtsb_base_write(uint64_t v) |
| { |
| asi_u64_write(ASI_DMMU, VA_DMMU_TSB_BASE, v); |
| } |
| /* Forward declarations. */ |
| struct as; |
| struct pte; |
| extern void tsb_invalidate(struct as *as, uintptr_t page, count_t pages); |
| extern void itsb_pte_copy(struct pte *t, index_t index); |
| extern void dtsb_pte_copy(struct pte *t, index_t index, bool ro); |
| #endif /* !def __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/mmu.h |
|---|
| 0,0 → 1,109 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_MMU_H_ |
| #define KERN_sparc64_MMU_H_ |
| /* LSU Control Register ASI. */ |
| #define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ |
| /* I-MMU ASIs. */ |
| #define ASI_IMMU 0x50 |
| #define ASI_IMMU_TSB_8KB_PTR_REG 0x51 |
| #define ASI_IMMU_TSB_64KB_PTR_REG 0x52 |
| #define ASI_ITLB_DATA_IN_REG 0x54 |
| #define ASI_ITLB_DATA_ACCESS_REG 0x55 |
| #define ASI_ITLB_TAG_READ_REG 0x56 |
| #define ASI_IMMU_DEMAP 0x57 |
| /* Virtual Addresses within ASI_IMMU. */ |
| #define VA_IMMU_TSB_TAG_TARGET 0x0 /**< IMMU TSB tag target register. */ |
| #define VA_IMMU_SFSR 0x18 /**< IMMU sync fault status register. */ |
| #define VA_IMMU_TSB_BASE 0x28 /**< IMMU TSB base register. */ |
| #define VA_IMMU_TAG_ACCESS 0x30 /**< IMMU TLB tag access register. */ |
| /* D-MMU ASIs. */ |
| #define ASI_DMMU 0x58 |
| #define ASI_DMMU_TSB_8KB_PTR_REG 0x59 |
| #define ASI_DMMU_TSB_64KB_PTR_REG 0x5a |
| #define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b |
| #define ASI_DTLB_DATA_IN_REG 0x5c |
| #define ASI_DTLB_DATA_ACCESS_REG 0x5d |
| #define ASI_DTLB_TAG_READ_REG 0x5e |
| #define ASI_DMMU_DEMAP 0x5f |
| /* Virtual Addresses within ASI_DMMU. */ |
| #define VA_DMMU_TSB_TAG_TARGET 0x0 /**< DMMU TSB tag target register. */ |
| #define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context register. */ |
| #define VA_SECONDARY_CONTEXT_REG 0x10 /**< DMMU secondary context register. */ |
| #define VA_DMMU_SFSR 0x18 /**< DMMU sync fault status register. */ |
| #define VA_DMMU_SFAR 0x20 /**< DMMU sync fault address register. */ |
| #define VA_DMMU_TSB_BASE 0x28 /**< DMMU TSB base register. */ |
| #define VA_DMMU_TAG_ACCESS 0x30 /**< DMMU TLB tag access register. */ |
| #define VA_DMMU_VA_WATCHPOINT_REG 0x38 /**< DMMU VA data watchpoint register. */ |
| #define VA_DMMU_PA_WATCHPOINT_REG 0x40 /**< DMMU PA data watchpoint register. */ |
| #ifndef __ASM__ |
| #include <arch/asm.h> |
| #include <arch/barrier.h> |
| #include <arch/types.h> |
| /** LSU Control Register. */ |
| typedef union { |
| uint64_t value; |
| struct { |
| unsigned : 23; |
| unsigned pm : 8; |
| unsigned vm : 8; |
| unsigned pr : 1; |
| unsigned pw : 1; |
| unsigned vr : 1; |
| unsigned vw : 1; |
| unsigned : 1; |
| unsigned fm : 16; |
| unsigned dm : 1; /**< D-MMU enable. */ |
| unsigned im : 1; /**< I-MMU enable. */ |
| unsigned dc : 1; /**< D-Cache enable. */ |
| unsigned ic : 1; /**< I-Cache enable. */ |
| } __attribute__ ((packed)); |
| } lsu_cr_reg_t; |
| #endif /* !def __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/tte.h |
|---|
| 0,0 → 1,98 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_TTE_H_ |
| #define KERN_sparc64_TTE_H_ |
| #define TTE_G (1 << 0) |
| #define TTE_W (1 << 1) |
| #define TTE_P (1 << 2) |
| #define TTE_E (1 << 3) |
| #define TTE_CV (1 << 4) |
| #define TTE_CP (1 << 5) |
| #define TTE_L (1 << 6) |
| #define TTE_V_SHIFT 63 |
| #define TTE_SIZE_SHIFT 61 |
| #ifndef __ASM__ |
| #include <arch/types.h> |
| #define VA_TAG_PAGE_SHIFT 22 |
| /** Translation Table Entry - Tag. */ |
| union tte_tag { |
| uint64_t value; |
| struct { |
| unsigned g : 1; /**< Global. */ |
| unsigned : 2; /**< Reserved. */ |
| unsigned context : 13; /**< Context identifier. */ |
| unsigned : 6; /**< Reserved. */ |
| uint64_t va_tag : 42; /**< Virtual Address Tag, bits 63:22. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tte_tag tte_tag_t; |
| /** Translation Table Entry - Data. */ |
| union tte_data { |
| uint64_t value; |
| struct { |
| unsigned v : 1; /**< Valid. */ |
| unsigned size : 2; /**< Page size of this entry. */ |
| unsigned nfo : 1; /**< No-Fault-Only. */ |
| unsigned ie : 1; /**< Invert Endianness. */ |
| unsigned soft2 : 9; /**< Software defined field. */ |
| unsigned diag : 9; /**< Diagnostic data. */ |
| unsigned pfn : 28; /**< Physical Address bits, bits 40:13. */ |
| unsigned soft : 6; /**< Software defined field. */ |
| unsigned l : 1; /**< Lock. */ |
| unsigned cp : 1; /**< Cacheable in physically indexed cache. */ |
| unsigned cv : 1; /**< Cacheable in virtually indexed cache. */ |
| unsigned e : 1; /**< Side-effect. */ |
| unsigned p : 1; /**< Privileged. */ |
| unsigned w : 1; /**< Writable. */ |
| unsigned g : 1; /**< Global. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tte_data tte_data_t; |
| #endif /* !def __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/mm/asid.h |
|---|
| 0,0 → 1,50 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64mm |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_ASID_H_ |
| #define KERN_sparc64_ASID_H_ |
| #include <arch/types.h> |
| /* |
| * On SPARC, Context means the same thing as ASID trough out the kernel. |
| */ |
| typedef uint16_t asid_t; |
| #define ASID_MAX_ARCH 8191 /* 2^13 - 1 */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/barrier.h |
|---|
| 0,0 → 1,103 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_BARRIER_H_ |
| #define KERN_sparc64_BARRIER_H_ |
| /* |
| * Our critical section barriers are prepared for the weakest RMO memory model. |
| */ |
| #define CS_ENTER_BARRIER() \ |
| asm volatile ( \ |
| "membar #LoadLoad | #LoadStore\n" \ |
| ::: "memory" \ |
| ) |
| #define CS_LEAVE_BARRIER() \ |
| asm volatile ( \ |
| "membar #StoreStore\n" \ |
| "membar #LoadStore\n" \ |
| ::: "memory" \ |
| ) |
| #define memory_barrier() \ |
| asm volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory") |
| #define read_barrier() \ |
| asm volatile ("membar #LoadLoad\n" ::: "memory") |
| #define write_barrier() \ |
| asm volatile ("membar #StoreStore\n" ::: "memory") |
| #define flush(a) \ |
| asm volatile ("flush %0\n" :: "r" ((a)) : "memory") |
| /** Flush Instruction pipeline. */ |
| static inline void flush_pipeline(void) |
| { |
| /* |
| * The FLUSH instruction takes address parameter. |
| * As such, it may trap if the address is not found in DTLB. |
| * |
| * The entire kernel text is mapped by a locked ITLB and |
| * DTLB entries. Therefore, when this function is called, |
| * the %o7 register will always be in the range mapped by |
| * DTLB. |
| */ |
| asm volatile ("flush %o7\n"); |
| } |
| /** Memory Barrier instruction. */ |
| static inline void membar(void) |
| { |
| asm volatile ("membar #Sync\n"); |
| } |
| #define smc_coherence(a) \ |
| { \ |
| write_barrier(); \ |
| flush((a)); \ |
| } |
| #define FLUSH_INVAL_MIN 4 |
| #define smc_coherence_block(a, l) \ |
| { \ |
| unsigned long i; \ |
| write_barrier(); \ |
| for (i = 0; i < (l); i += FLUSH_INVAL_MIN) \ |
| flush((void *)(a) + i); \ |
| } |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/memstr.h |
|---|
| 0,0 → 1,48 |
| /* |
| * Copyright (c) 2005 Sergey Bondari |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_MEMSTR_H_ |
| #define KERN_sparc64_MEMSTR_H_ |
| #define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) |
| extern void memsetw(void *dst, size_t cnt, uint16_t x); |
| extern void memsetb(void *dst, size_t cnt, uint8_t x); |
| extern int memcmp(const void *a, const void *b, size_t cnt); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/asm.h |
|---|
| 0,0 → 1,384 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_ASM_H_ |
| #define KERN_sparc64_ASM_H_ |
| #include <arch/arch.h> |
| #include <arch/types.h> |
| #include <typedefs.h> |
| #include <align.h> |
| #include <arch/register.h> |
| #include <config.h> |
| #include <arch/stack.h> |
| /** Read Processor State register. |
| * |
| * @return Value of PSTATE register. |
| */ |
| static inline uint64_t pstate_read(void) |
| { |
| uint64_t v; |
| asm volatile ("rdpr %%pstate, %0\n" : "=r" (v)); |
| return v; |
| } |
| /** Write Processor State register. |
| * |
| * @param v New value of PSTATE register. |
| */ |
| static inline void pstate_write(uint64_t v) |
| { |
| asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0)); |
| } |
| /** Read TICK_compare Register. |
| * |
| * @return Value of TICK_comapre register. |
| */ |
| static inline uint64_t tick_compare_read(void) |
| { |
| uint64_t v; |
| asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v)); |
| return v; |
| } |
| /** Write TICK_compare Register. |
| * |
| * @param v New value of TICK_comapre register. |
| */ |
| static inline void tick_compare_write(uint64_t v) |
| { |
| asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0)); |
| } |
| /** Read TICK Register. |
| * |
| * @return Value of TICK register. |
| */ |
| static inline uint64_t tick_read(void) |
| { |
| uint64_t v; |
| asm volatile ("rdpr %%tick, %0\n" : "=r" (v)); |
| return v; |
| } |
| /** Write TICK Register. |
| * |
| * @param v New value of TICK register. |
| */ |
| static inline void tick_write(uint64_t v) |
| { |
| asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0)); |
| } |
| /** Read FPRS Register. |
| * |
| * @return Value of FPRS register. |
| */ |
| static inline uint64_t fprs_read(void) |
| { |
| uint64_t v; |
| asm volatile ("rd %%fprs, %0\n" : "=r" (v)); |
| return v; |
| } |
| /** Write FPRS Register. |
| * |
| * @param v New value of FPRS register. |
| */ |
| static inline void fprs_write(uint64_t v) |
| { |
| asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0)); |
| } |
| /** Read SOFTINT Register. |
| * |
| * @return Value of SOFTINT register. |
| */ |
| static inline uint64_t softint_read(void) |
| { |
| uint64_t v; |
| asm volatile ("rd %%softint, %0\n" : "=r" (v)); |
| return v; |
| } |
| /** Write SOFTINT Register. |
| * |
| * @param v New value of SOFTINT register. |
| */ |
| static inline void softint_write(uint64_t v) |
| { |
| asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0)); |
| } |
| /** Write CLEAR_SOFTINT Register. |
| * |
| * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register. |
| * |
| * @param v New value of CLEAR_SOFTINT register. |
| */ |
| static inline void clear_softint_write(uint64_t v) |
| { |
| asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0)); |
| } |
| /** Write SET_SOFTINT Register. |
| * |
| * Bits set in SET_SOFTINT register will be set in SOFTINT register. |
| * |
| * @param v New value of SET_SOFTINT register. |
| */ |
| static inline void set_softint_write(uint64_t v) |
| { |
| asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0)); |
| } |
| /** Enable interrupts. |
| * |
| * Enable interrupts and return previous |
| * value of IPL. |
| * |
| * @return Old interrupt priority level. |
| */ |
| static inline ipl_t interrupts_enable(void) { |
| pstate_reg_t pstate; |
| uint64_t value; |
| value = pstate_read(); |
| pstate.value = value; |
| pstate.ie = true; |
| pstate_write(pstate.value); |
| return (ipl_t) value; |
| } |
| /** Disable interrupts. |
| * |
| * Disable interrupts and return previous |
| * value of IPL. |
| * |
| * @return Old interrupt priority level. |
| */ |
| static inline ipl_t interrupts_disable(void) { |
| pstate_reg_t pstate; |
| uint64_t value; |
| value = pstate_read(); |
| pstate.value = value; |
| pstate.ie = false; |
| pstate_write(pstate.value); |
| return (ipl_t) value; |
| } |
| /** Restore interrupt priority level. |
| * |
| * Restore IPL. |
| * |
| * @param ipl Saved interrupt priority level. |
| */ |
| static inline void interrupts_restore(ipl_t ipl) { |
| pstate_reg_t pstate; |
| pstate.value = pstate_read(); |
| pstate.ie = ((pstate_reg_t) ipl).ie; |
| pstate_write(pstate.value); |
| } |
| /** Return interrupt priority level. |
| * |
| * Return IPL. |
| * |
| * @return Current interrupt priority level. |
| */ |
| static inline ipl_t interrupts_read(void) { |
| return (ipl_t) pstate_read(); |
| } |
| /** Return base address of current stack. |
| * |
| * Return the base address of the current stack. |
| * The stack is assumed to be STACK_SIZE bytes long. |
| * The stack must start on page boundary. |
| */ |
| static inline uintptr_t get_stack_base(void) |
| { |
| uintptr_t unbiased_sp; |
| asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS)); |
| return ALIGN_DOWN(unbiased_sp, STACK_SIZE); |
| } |
| /** Read Version Register. |
| * |
| * @return Value of VER register. |
| */ |
| static inline uint64_t ver_read(void) |
| { |
| uint64_t v; |
| asm volatile ("rdpr %%ver, %0\n" : "=r" (v)); |
| return v; |
| } |
| /** Read Trap Program Counter register. |
| * |
| * @return Current value in TPC. |
| */ |
| static inline uint64_t tpc_read(void) |
| { |
| uint64_t v; |
| asm volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
| return v; |
| } |
| /** Read Trap Level register. |
| * |
| * @return Current value in TL. |
| */ |
| static inline uint64_t tl_read(void) |
| { |
| uint64_t v; |
| asm volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
| return v; |
| } |
| /** Read Trap Base Address register. |
| * |
| * @return Current value in TBA. |
| */ |
| static inline uint64_t tba_read(void) |
| { |
| uint64_t v; |
| asm volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
| return v; |
| } |
| /** Write Trap Base Address register. |
| * |
| * @param v New value of TBA. |
| */ |
| static inline void tba_write(uint64_t v) |
| { |
| asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0)); |
| } |
| /** Load uint64_t from alternate space. |
| * |
| * @param asi ASI determining the alternate space. |
| * @param va Virtual address within the ASI. |
| * |
| * @return Value read from the virtual address in the specified address space. |
| */ |
| static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va) |
| { |
| uint64_t v; |
| asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi)); |
| return v; |
| } |
| /** Store uint64_t to alternate space. |
| * |
| * @param asi ASI determining the alternate space. |
| * @param va Virtual address within the ASI. |
| * @param v Value to be written. |
| */ |
| static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v) |
| { |
| asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory"); |
| } |
| /** Flush all valid register windows to memory. */ |
| static inline void flushw(void) |
| { |
| asm volatile ("flushw\n"); |
| } |
| /** Switch to nucleus by setting TL to 1. */ |
| static inline void nucleus_enter(void) |
| { |
| asm volatile ("wrpr %g0, 1, %tl\n"); |
| } |
| /** Switch from nucleus by setting TL to 0. */ |
| static inline void nucleus_leave(void) |
| { |
| asm volatile ("wrpr %g0, %g0, %tl\n"); |
| } |
| /** Read UPA_CONFIG register. |
| * |
| * @return Value of the UPA_CONFIG register. |
| */ |
| static inline uint64_t upa_config_read(void) |
| { |
| return asi_u64_read(ASI_UPA_CONFIG, 0); |
| } |
| extern void cpu_halt(void); |
| extern void cpu_sleep(void); |
| extern void asm_delay_loop(const uint32_t usec); |
| extern uint64_t read_from_ag_g7(void); |
| extern void write_to_ag_g6(uint64_t val); |
| extern void write_to_ag_g7(uint64_t val); |
| extern void write_to_ig_g6(uint64_t val); |
| extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/cpu.h |
|---|
| 0,0 → 1,73 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_CPU_H_ |
| #define KERN_sparc64_CPU_H_ |
| #include <arch/types.h> |
| #include <typedefs.h> |
| #include <arch/register.h> |
| #include <arch/asm.h> |
| #ifdef CONFIG_SMP |
| #include <arch/mm/cache.h> |
| #endif |
| #define MANUF_FUJITSU 0x04 |
| #define MANUF_ULTRASPARC 0x17 /**< UltraSPARC I, UltraSPARC II */ |
| #define MANUF_SUN 0x3e |
| #define IMPL_ULTRASPARCI 0x10 |
| #define IMPL_ULTRASPARCII 0x11 |
| #define IMPL_ULTRASPARCII_I 0x12 |
| #define IMPL_ULTRASPARCII_E 0x13 |
| #define IMPL_ULTRASPARCIII 0x15 |
| #define IMPL_ULTRASPARCIV_PLUS 0x19 |
| #define IMPL_SPARC64V 0x5 |
| typedef struct { |
| uint32_t mid; /**< Processor ID as read from |
| UPA_CONFIG. */ |
| ver_reg_t ver; |
| uint32_t clock_frequency; /**< Processor frequency in Hz. */ |
| uint64_t next_tick_cmpr; /**< Next clock interrupt should be |
| generated when the TICK register |
| matches this value. */ |
| } cpu_arch_t; |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/types.h |
|---|
| 0,0 → 1,90 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_TYPES_H_ |
| #define KERN_sparc64_TYPES_H_ |
| typedef signed char int8_t; |
| typedef signed short int16_t; |
| typedef signed int int32_t; |
| typedef signed long int64_t; |
| typedef unsigned char uint8_t; |
| typedef unsigned short uint16_t; |
| typedef unsigned int uint32_t; |
| typedef unsigned long uint64_t; |
| typedef uint64_t size_t; |
| typedef uint64_t count_t; |
| typedef uint64_t index_t; |
| typedef uint64_t uintptr_t; |
| typedef uint64_t pfn_t; |
| typedef uint64_t ipl_t; |
| typedef uint64_t unative_t; |
| typedef int64_t native_t; |
| /**< Formats for uintptr_t, size_t, count_t and index_t */ |
| #define PRIp "llx" |
| #define PRIs "llu" |
| #define PRIc "llu" |
| #define PRIi "llu" |
| /**< Formats for (u)int8_t, (u)int16_t, (u)int32_t, (u)int64_t and (u)native_t */ |
| #define PRId8 "d" |
| #define PRId16 "d" |
| #define PRId32 "d" |
| #define PRId64 "lld" |
| #define PRIdn "lld" |
| #define PRIu8 "u" |
| #define PRIu16 "u" |
| #define PRIu32 "u" |
| #define PRIu64 "llu" |
| #define PRIun "llu" |
| #define PRIx8 "x" |
| #define PRIx16 "x" |
| #define PRIx32 "x" |
| #define PRIx64 "llx" |
| #define PRIxn "llx" |
| typedef uint8_t asi_t; |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/context_offset.h |
|---|
| 0,0 → 1,107 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| #ifndef KERN_sparc64_CONTEXT_OFFSET_H_ |
| #define KERN_sparc64_CONTEXT_OFFSET_H_ |
| #define OFFSET_SP 0x0 |
| #define OFFSET_PC 0x8 |
| #define OFFSET_I0 0x10 |
| #define OFFSET_I1 0x18 |
| #define OFFSET_I2 0x20 |
| #define OFFSET_I3 0x28 |
| #define OFFSET_I4 0x30 |
| #define OFFSET_I5 0x38 |
| #define OFFSET_FP 0x40 |
| #define OFFSET_I7 0x48 |
| #define OFFSET_L0 0x50 |
| #define OFFSET_L1 0x58 |
| #define OFFSET_L2 0x60 |
| #define OFFSET_L3 0x68 |
| #define OFFSET_L4 0x70 |
| #define OFFSET_L5 0x78 |
| #define OFFSET_L6 0x80 |
| #define OFFSET_L7 0x88 |
| #ifndef KERNEL |
| # define OFFSET_TP 0x90 |
| #endif |
| #ifdef __ASM__ |
| .macro CONTEXT_SAVE_ARCH_CORE ctx:req |
| stx %sp, [\ctx + OFFSET_SP] |
| stx %o7, [\ctx + OFFSET_PC] |
| stx %i0, [\ctx + OFFSET_I0] |
| stx %i1, [\ctx + OFFSET_I1] |
| stx %i2, [\ctx + OFFSET_I2] |
| stx %i3, [\ctx + OFFSET_I3] |
| stx %i4, [\ctx + OFFSET_I4] |
| stx %i5, [\ctx + OFFSET_I5] |
| stx %fp, [\ctx + OFFSET_FP] |
| stx %i7, [\ctx + OFFSET_I7] |
| stx %l0, [\ctx + OFFSET_L0] |
| stx %l1, [\ctx + OFFSET_L1] |
| stx %l2, [\ctx + OFFSET_L2] |
| stx %l3, [\ctx + OFFSET_L3] |
| stx %l4, [\ctx + OFFSET_L4] |
| stx %l5, [\ctx + OFFSET_L5] |
| stx %l6, [\ctx + OFFSET_L6] |
| stx %l7, [\ctx + OFFSET_L7] |
| #ifndef KERNEL |
| stx %g7, [\ctx + OFFSET_TP] |
| #endif |
| .endm |
| .macro CONTEXT_RESTORE_ARCH_CORE ctx:req |
| ldx [\ctx + OFFSET_SP], %sp |
| ldx [\ctx + OFFSET_PC], %o7 |
| ldx [\ctx + OFFSET_I0], %i0 |
| ldx [\ctx + OFFSET_I1], %i1 |
| ldx [\ctx + OFFSET_I2], %i2 |
| ldx [\ctx + OFFSET_I3], %i3 |
| ldx [\ctx + OFFSET_I4], %i4 |
| ldx [\ctx + OFFSET_I5], %i5 |
| ldx [\ctx + OFFSET_FP], %fp |
| ldx [\ctx + OFFSET_I7], %i7 |
| ldx [\ctx + OFFSET_L0], %l0 |
| ldx [\ctx + OFFSET_L1], %l1 |
| ldx [\ctx + OFFSET_L2], %l2 |
| ldx [\ctx + OFFSET_L3], %l3 |
| ldx [\ctx + OFFSET_L4], %l4 |
| ldx [\ctx + OFFSET_L5], %l5 |
| ldx [\ctx + OFFSET_L6], %l6 |
| ldx [\ctx + OFFSET_L7], %l7 |
| #ifndef KERNEL |
| ldx [\ctx + OFFSET_TP], %g7 |
| #endif |
| .endm |
| #endif /* __ASM__ */ |
| #endif |
| /branches/sparc/kernel/arch/sparc64/include/byteorder.h |
|---|
| 0,0 → 1,43 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_BYTEORDER_H_ |
| #define KERN_sparc64_BYTEORDER_H_ |
| #define ARCH_IS_BIG_ENDIAN |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/stack.h |
|---|
| 0,0 → 1,72 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_STACK_H_ |
| #define KERN_sparc64_STACK_H_ |
| #define STACK_ITEM_SIZE 8 |
| /** According to SPARC Compliance Definition, every stack frame is 16-byte aligned. */ |
| #define STACK_ALIGNMENT 16 |
| /** |
| * 16-extended-word save area for %i[0-7] and %l[0-7] registers. |
| */ |
| #define STACK_WINDOW_SAVE_AREA_SIZE (16 * STACK_ITEM_SIZE) |
| /** |
| * Six extended words for first six arguments. |
| */ |
| #define STACK_ARG_SAVE_AREA_SIZE (6 * STACK_ITEM_SIZE) |
| /** |
| * By convention, the actual top of the stack is %sp + STACK_BIAS. |
| */ |
| #define STACK_BIAS 2047 |
| /* |
| * Offsets of arguments on stack. |
| */ |
| #define STACK_ARG0 0 |
| #define STACK_ARG1 8 |
| #define STACK_ARG2 16 |
| #define STACK_ARG3 24 |
| #define STACK_ARG4 32 |
| #define STACK_ARG5 40 |
| #define STACK_ARG6 48 |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/trap/syscall.h |
|---|
| 0,0 → 1,57 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** |
| * @file |
| * @brief This file contains the trap_instruction handler. |
| * |
| * The trap_instruction trap is used to implement syscalls. |
| */ |
| #ifndef KERN_sparc64_SYSCALL_TRAP_H_ |
| #define KERN_sparc64_SYSCALL_TRAP_H_ |
| #define TT_TRAP_INSTRUCTION(n) (0x100 + (n)) |
| #define TT_TRAP_INSTRUCTION_LAST TT_TRAP_INSTRUCTION(127) |
| #ifdef __ASM__ |
| .macro TRAP_INSTRUCTION n |
| ba trap_instruction_handler |
| mov TT_TRAP_INSTRUCTION(\n) - TT_TRAP_INSTRUCTION(0), %g2 |
| .endm |
| #endif /* __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/trap/trap_table.h |
|---|
| 0,0 → 1,112 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_TRAP_TABLE_H_ |
| #define KERN_sparc64_TRAP_TABLE_H_ |
| #include <arch/stack.h> |
| #define TRAP_TABLE_ENTRY_COUNT 1024 |
| #define TRAP_TABLE_ENTRY_SIZE 32 |
| #define TRAP_TABLE_SIZE (TRAP_TABLE_ENTRY_COUNT * TRAP_TABLE_ENTRY_SIZE) |
| #ifndef __ASM__ |
| #include <arch/types.h> |
| struct trap_table_entry { |
| uint8_t octets[TRAP_TABLE_ENTRY_SIZE]; |
| } __attribute__ ((packed)); |
| typedef struct trap_table_entry trap_table_entry_t; |
| extern trap_table_entry_t trap_table[TRAP_TABLE_ENTRY_COUNT]; |
| extern trap_table_entry_t trap_table_save[TRAP_TABLE_ENTRY_COUNT]; |
| #endif /* !__ASM__ */ |
| #ifdef __ASM__ |
| .macro SAVE_GLOBALS |
| mov %g1, %l1 |
| mov %g2, %l2 |
| mov %g3, %l3 |
| mov %g4, %l4 |
| mov %g5, %l5 |
| mov %g6, %l6 |
| mov %g7, %l7 |
| .endm |
| .macro RESTORE_GLOBALS |
| mov %l1, %g1 |
| mov %l2, %g2 |
| mov %l3, %g3 |
| mov %l4, %g4 |
| mov %l5, %g5 |
| mov %l6, %g6 |
| mov %l7, %g7 |
| .endm |
| /* |
| * The following needs to be in sync with the definition of the istate |
| * structure. The one STACK_ITEM_SIZE is counted for space holding the 7th |
| * argument to syscall_handler (i.e. syscall number) and the other |
| * STACK_ITEM_SIZE is counted because of the required alignment. |
| */ |
| #define PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE \ |
| (STACK_WINDOW_SAVE_AREA_SIZE + STACK_ARG_SAVE_AREA_SIZE + \ |
| (2 * STACK_ITEM_SIZE) + (12 * 8)) |
| #define SAVED_TSTATE -(1 * 8) |
| #define SAVED_TPC -(2 * 8) |
| #define SAVED_TNPC -(3 * 8) /* <-- istate_t begins here */ |
| #define SAVED_Y -(4 * 8) |
| #define SAVED_I0 -(5 * 8) |
| #define SAVED_I1 -(6 * 8) |
| #define SAVED_I2 -(7 * 8) |
| #define SAVED_I3 -(8 * 8) |
| #define SAVED_I4 -(9 * 8) |
| #define SAVED_I5 -(10 * 8) |
| #define SAVED_I6 -(11 * 8) |
| #define SAVED_I7 -(12 * 8) |
| .macro PREEMPTIBLE_HANDLER f |
| sethi %hi(\f), %g1 |
| b preemptible_handler |
| or %g1, %lo(\f), %g1 |
| .endm |
| #endif /* __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/trap/mmu.h |
|---|
| 0,0 → 1,182 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** |
| * @file |
| * @brief This file contains fast MMU trap handlers. |
| */ |
| #ifndef KERN_sparc64_MMU_TRAP_H_ |
| #define KERN_sparc64_MMU_TRAP_H_ |
| #include <arch/stack.h> |
| #include <arch/regdef.h> |
| #include <arch/mm/tlb.h> |
| #include <arch/mm/mmu.h> |
| #include <arch/mm/tte.h> |
| #include <arch/trap/regwin.h> |
| #ifdef CONFIG_TSB |
| #include <arch/mm/tsb.h> |
| #endif |
| #define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 |
| #define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 |
| #define TT_FAST_DATA_ACCESS_PROTECTION 0x6c |
| #define FAST_MMU_HANDLER_SIZE 128 |
| #ifdef __ASM__ |
| .macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER |
| /* |
| * First, try to refill TLB from TSB. |
| */ |
| #ifdef CONFIG_TSB |
| ldxa [%g0] ASI_IMMU, %g1 ! read TSB Tag Target Register |
| ldxa [%g0] ASI_IMMU_TSB_8KB_PTR_REG, %g2 ! read TSB 8K Pointer |
| ldda [%g2] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 |
| cmp %g1, %g4 ! is this the entry we are looking for? |
| bne,pn %xcc, 0f |
| nop |
| stxa %g5, [%g0] ASI_ITLB_DATA_IN_REG ! copy mapping from ITSB to ITLB |
| retry |
| #endif |
| 0: |
| wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
| PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss |
| .endm |
| .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl |
| /* |
| * First, try to refill TLB from TSB. |
| */ |
| #ifdef CONFIG_TSB |
| ldxa [%g0] ASI_DMMU, %g1 ! read TSB Tag Target Register |
| srlx %g1, TSB_TAG_TARGET_CONTEXT_SHIFT, %g2 ! is this a kernel miss? |
| brz,pn %g2, 0f |
| ldxa [%g0] ASI_DMMU_TSB_8KB_PTR_REG, %g3 ! read TSB 8K Pointer |
| ldda [%g3] ASI_NUCLEUS_QUAD_LDD, %g4 ! 16-byte atomic load into %g4 and %g5 |
| cmp %g1, %g4 ! is this the entry we are looking for? |
| bne,pn %xcc, 0f |
| nop |
| stxa %g5, [%g0] ASI_DTLB_DATA_IN_REG ! copy mapping from DTSB to DTLB |
| retry |
| #endif |
| /* |
| * Second, test if it is the portion of the kernel address space |
| * which is faulting. If that is the case, immediately create |
| * identity mapping for that page in DTLB. VPN 0 is excluded from |
| * this treatment. |
| * |
| * Note that branch-delay slots are used in order to save space. |
| */ |
| 0: |
| mov VA_DMMU_TAG_ACCESS, %g1 |
| ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN |
| set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 |
| andcc %g1, %g2, %g3 ! get Context |
| bnz 0f ! Context is non-zero |
| andncc %g1, %g2, %g3 ! get page address into %g3 |
| bz 0f ! page address is zero |
| sethi %hi(kernel_8k_tlb_data_template), %g2 |
| ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2 |
| or %g3, %g2, %g2 |
| stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page |
| retry |
| /* |
| * Third, catch and handle special cases when the trap is caused by |
| * the userspace register window spill or fill handler. In case |
| * one of these two traps caused this trap, we just lower the trap |
| * level and service the DTLB miss. In the end, we restart |
| * the offending SAVE or RESTORE. |
| */ |
| 0: |
| .if (\tl > 0) |
| wrpr %g0, 1, %tl |
| .endif |
| /* |
| * Switch from the MM globals. |
| */ |
| wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
| /* |
| * Read the Tag Access register for the higher-level handler. |
| * This is necessary to survive nested DTLB misses. |
| */ |
| mov VA_DMMU_TAG_ACCESS, %g2 |
| ldxa [%g2] ASI_DMMU, %g2 |
| /* |
| * g2 will be passed as an argument to fast_data_access_mmu_miss(). |
| */ |
| PREEMPTIBLE_HANDLER fast_data_access_mmu_miss |
| .endm |
| .macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl |
| /* |
| * The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. |
| */ |
| .if (\tl > 0) |
| wrpr %g0, 1, %tl |
| .endif |
| /* |
| * Switch from the MM globals. |
| */ |
| wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
| /* |
| * Read the Tag Access register for the higher-level handler. |
| * This is necessary to survive nested DTLB misses. |
| */ |
| mov VA_DMMU_TAG_ACCESS, %g2 |
| ldxa [%g2] ASI_DMMU, %g2 |
| /* |
| * g2 will be passed as an argument to fast_data_access_mmu_miss(). |
| */ |
| PREEMPTIBLE_HANDLER fast_data_access_protection |
| .endm |
| #endif /* __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/trap/interrupt.h |
|---|
| 0,0 → 1,117 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** |
| * @file |
| * @brief This file contains interrupt vector trap handler. |
| */ |
| #ifndef KERN_sparc64_TRAP_INTERRUPT_H_ |
| #define KERN_sparc64_TRAP_INTERRUPT_H_ |
| #include <arch/trap/trap_table.h> |
| #include <arch/stack.h> |
| /* IMAP register bits */ |
| #define IGN_MASK 0x7c0 |
| #define INO_MASK 0x1f |
| #define IMAP_V_MASK (1ULL << 31) |
| #define IGN_SHIFT 6 |
| /* Interrupt ASI registers. */ |
| #define ASI_UDB_INTR_W 0x77 |
| #define ASI_INTR_DISPATCH_STATUS 0x48 |
| #define ASI_UDB_INTR_R 0x7f |
| #define ASI_INTR_RECEIVE 0x49 |
| /* VA's used with ASI_UDB_INTR_W register. */ |
| #define ASI_UDB_INTR_W_DATA_0 0x40 |
| #define ASI_UDB_INTR_W_DATA_1 0x50 |
| #define ASI_UDB_INTR_W_DATA_2 0x60 |
| #define ASI_UDB_INTR_W_DISPATCH 0x70 |
| /* VA's used with ASI_UDB_INTR_R register. */ |
| #define ASI_UDB_INTR_R_DATA_0 0x40 |
| #define ASI_UDB_INTR_R_DATA_1 0x50 |
| #define ASI_UDB_INTR_R_DATA_2 0x60 |
| /* Shifts in the Interrupt Vector Dispatch virtual address. */ |
| #define INTR_VEC_DISPATCH_MID_SHIFT 14 |
| /* Bits in the Interrupt Dispatch Status register. */ |
| #define INTR_DISPATCH_STATUS_NACK 0x2 |
| #define INTR_DISPATCH_STATUS_BUSY 0x1 |
| #define TT_INTERRUPT_LEVEL_1 0x41 |
| #define TT_INTERRUPT_LEVEL_2 0x42 |
| #define TT_INTERRUPT_LEVEL_3 0x43 |
| #define TT_INTERRUPT_LEVEL_4 0x44 |
| #define TT_INTERRUPT_LEVEL_5 0x45 |
| #define TT_INTERRUPT_LEVEL_6 0x46 |
| #define TT_INTERRUPT_LEVEL_7 0x47 |
| #define TT_INTERRUPT_LEVEL_8 0x48 |
| #define TT_INTERRUPT_LEVEL_9 0x49 |
| #define TT_INTERRUPT_LEVEL_10 0x4a |
| #define TT_INTERRUPT_LEVEL_11 0x4b |
| #define TT_INTERRUPT_LEVEL_12 0x4c |
| #define TT_INTERRUPT_LEVEL_13 0x4d |
| #define TT_INTERRUPT_LEVEL_14 0x4e |
| #define TT_INTERRUPT_LEVEL_15 0x4f |
| #define TT_INTERRUPT_VECTOR_TRAP 0x60 |
| #define INTERRUPT_LEVEL_N_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE |
| #define INTERRUPT_VECTOR_TRAP_HANDLER_SIZE TRAP_TABLE_ENTRY_SIZE |
| #ifdef __ASM__ |
| .macro INTERRUPT_LEVEL_N_HANDLER n |
| mov \n - 1, %g2 |
| PREEMPTIBLE_HANDLER exc_dispatch |
| .endm |
| .macro INTERRUPT_VECTOR_TRAP_HANDLER |
| PREEMPTIBLE_HANDLER interrupt |
| .endm |
| #endif /* __ASM__ */ |
| #ifndef __ASM__ |
| #include <arch/interrupt.h> |
| extern void interrupt(int n, istate_t *istate); |
| #endif /* !def __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/trap/exception.h |
|---|
| 0,0 → 1,90 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** |
| * @file |
| */ |
| #ifndef KERN_sparc64_EXCEPTION_H_ |
| #define KERN_sparc64_EXCEPTION_H_ |
| #define TT_INSTRUCTION_ACCESS_EXCEPTION 0x08 |
| #define TT_INSTRUCTION_ACCESS_ERROR 0x0a |
| #define TT_ILLEGAL_INSTRUCTION 0x10 |
| #define TT_PRIVILEGED_OPCODE 0x11 |
| #define TT_UNIMPLEMENTED_LDD 0x12 |
| #define TT_UNIMPLEMENTED_STD 0x13 |
| #define TT_FP_DISABLED 0x20 |
| #define TT_FP_EXCEPTION_IEEE_754 0x21 |
| #define TT_FP_EXCEPTION_OTHER 0x22 |
| #define TT_TAG_OVERFLOW 0x23 |
| #define TT_DIVISION_BY_ZERO 0x28 |
| #define TT_DATA_ACCESS_EXCEPTION 0x30 |
| #define TT_DATA_ACCESS_ERROR 0x32 |
| #define TT_MEM_ADDRESS_NOT_ALIGNED 0x34 |
| #define TT_LDDF_MEM_ADDRESS_NOT_ALIGNED 0x35 |
| #define TT_STDF_MEM_ADDRESS_NOT_ALIGNED 0x36 |
| #define TT_PRIVILEGED_ACTION 0x37 |
| #define TT_LDQF_MEM_ADDRESS_NOT_ALIGNED 0x38 |
| #define TT_STQF_MEM_ADDRESS_NOT_ALIGNED 0x39 |
| #ifndef __ASM__ |
| #include <arch/interrupt.h> |
| extern void dump_istate(istate_t *istate); |
| extern void instruction_access_exception(int n, istate_t *istate); |
| extern void instruction_access_error(int n, istate_t *istate); |
| extern void illegal_instruction(int n, istate_t *istate); |
| extern void privileged_opcode(int n, istate_t *istate); |
| extern void unimplemented_LDD(int n, istate_t *istate); |
| extern void unimplemented_STD(int n, istate_t *istate); |
| extern void fp_disabled(int n, istate_t *istate); |
| extern void fp_exception_ieee_754(int n, istate_t *istate); |
| extern void fp_exception_other(int n, istate_t *istate); |
| extern void tag_overflow(int n, istate_t *istate); |
| extern void division_by_zero(int n, istate_t *istate); |
| extern void data_access_exception(int n, istate_t *istate); |
| extern void data_access_error(int n, istate_t *istate); |
| extern void mem_address_not_aligned(int n, istate_t *istate); |
| extern void LDDF_mem_address_not_aligned(int n, istate_t *istate); |
| extern void STDF_mem_address_not_aligned(int n, istate_t *istate); |
| extern void privileged_action(int n, istate_t *istate); |
| extern void LDQF_mem_address_not_aligned(int n, istate_t *istate); |
| extern void STQF_mem_address_not_aligned(int n, istate_t *istate); |
| #endif /* !__ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/trap/regwin.h |
|---|
| 0,0 → 1,231 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** |
| * @file |
| * @brief This file contains register window trap handlers. |
| */ |
| #ifndef KERN_sparc64_REGWIN_H_ |
| #define KERN_sparc64_REGWIN_H_ |
| #include <arch/stack.h> |
| #include <arch/arch.h> |
| #define TT_CLEAN_WINDOW 0x24 |
| #define TT_SPILL_0_NORMAL 0x80 /* kernel spills */ |
| #define TT_SPILL_1_NORMAL 0x84 /* userspace spills */ |
| #define TT_SPILL_2_NORMAL 0x88 /* spills to userspace window buffer */ |
| #define TT_SPILL_0_OTHER 0xa0 /* spills to userspace window buffer */ |
| #define TT_FILL_0_NORMAL 0xc0 /* kernel fills */ |
| #define TT_FILL_1_NORMAL 0xc4 /* userspace fills */ |
| #define REGWIN_HANDLER_SIZE 128 |
| #define CLEAN_WINDOW_HANDLER_SIZE REGWIN_HANDLER_SIZE |
| #define SPILL_HANDLER_SIZE REGWIN_HANDLER_SIZE |
| #define FILL_HANDLER_SIZE REGWIN_HANDLER_SIZE |
| /* Window Save Area offsets. */ |
| #define L0_OFFSET 0 |
| #define L1_OFFSET 8 |
| #define L2_OFFSET 16 |
| #define L3_OFFSET 24 |
| #define L4_OFFSET 32 |
| #define L5_OFFSET 40 |
| #define L6_OFFSET 48 |
| #define L7_OFFSET 56 |
| #define I0_OFFSET 64 |
| #define I1_OFFSET 72 |
| #define I2_OFFSET 80 |
| #define I3_OFFSET 88 |
| #define I4_OFFSET 96 |
| #define I5_OFFSET 104 |
| #define I6_OFFSET 112 |
| #define I7_OFFSET 120 |
| #ifdef __ASM__ |
| /* |
| * Macro used by the nucleus and the primary context 0 during normal and other spills. |
| */ |
| .macro SPILL_NORMAL_HANDLER_KERNEL |
| stx %l0, [%sp + STACK_BIAS + L0_OFFSET] |
| stx %l1, [%sp + STACK_BIAS + L1_OFFSET] |
| stx %l2, [%sp + STACK_BIAS + L2_OFFSET] |
| stx %l3, [%sp + STACK_BIAS + L3_OFFSET] |
| stx %l4, [%sp + STACK_BIAS + L4_OFFSET] |
| stx %l5, [%sp + STACK_BIAS + L5_OFFSET] |
| stx %l6, [%sp + STACK_BIAS + L6_OFFSET] |
| stx %l7, [%sp + STACK_BIAS + L7_OFFSET] |
| stx %i0, [%sp + STACK_BIAS + I0_OFFSET] |
| stx %i1, [%sp + STACK_BIAS + I1_OFFSET] |
| stx %i2, [%sp + STACK_BIAS + I2_OFFSET] |
| stx %i3, [%sp + STACK_BIAS + I3_OFFSET] |
| stx %i4, [%sp + STACK_BIAS + I4_OFFSET] |
| stx %i5, [%sp + STACK_BIAS + I5_OFFSET] |
| stx %i6, [%sp + STACK_BIAS + I6_OFFSET] |
| stx %i7, [%sp + STACK_BIAS + I7_OFFSET] |
| saved |
| retry |
| .endm |
| /* |
| * Macro used by the userspace during normal spills. |
| */ |
| .macro SPILL_NORMAL_HANDLER_USERSPACE |
| wr %g0, ASI_AIUP, %asi |
| stxa %l0, [%sp + STACK_BIAS + L0_OFFSET] %asi |
| stxa %l1, [%sp + STACK_BIAS + L1_OFFSET] %asi |
| stxa %l2, [%sp + STACK_BIAS + L2_OFFSET] %asi |
| stxa %l3, [%sp + STACK_BIAS + L3_OFFSET] %asi |
| stxa %l4, [%sp + STACK_BIAS + L4_OFFSET] %asi |
| stxa %l5, [%sp + STACK_BIAS + L5_OFFSET] %asi |
| stxa %l6, [%sp + STACK_BIAS + L6_OFFSET] %asi |
| stxa %l7, [%sp + STACK_BIAS + L7_OFFSET] %asi |
| stxa %i0, [%sp + STACK_BIAS + I0_OFFSET] %asi |
| stxa %i1, [%sp + STACK_BIAS + I1_OFFSET] %asi |
| stxa %i2, [%sp + STACK_BIAS + I2_OFFSET] %asi |
| stxa %i3, [%sp + STACK_BIAS + I3_OFFSET] %asi |
| stxa %i4, [%sp + STACK_BIAS + I4_OFFSET] %asi |
| stxa %i5, [%sp + STACK_BIAS + I5_OFFSET] %asi |
| stxa %i6, [%sp + STACK_BIAS + I6_OFFSET] %asi |
| stxa %i7, [%sp + STACK_BIAS + I7_OFFSET] %asi |
| saved |
| retry |
| .endm |
| /* |
| * Macro used to spill userspace window to userspace window buffer. |
| * It can be either triggered from preemptible_handler doing SAVE |
| * at (TL=1) or from normal kernel code doing SAVE when OTHERWIN>0 |
| * at (TL=0). |
| */ |
| .macro SPILL_TO_USPACE_WINDOW_BUFFER |
| stx %l0, [%g7 + L0_OFFSET] |
| stx %l1, [%g7 + L1_OFFSET] |
| stx %l2, [%g7 + L2_OFFSET] |
| stx %l3, [%g7 + L3_OFFSET] |
| stx %l4, [%g7 + L4_OFFSET] |
| stx %l5, [%g7 + L5_OFFSET] |
| stx %l6, [%g7 + L6_OFFSET] |
| stx %l7, [%g7 + L7_OFFSET] |
| stx %i0, [%g7 + I0_OFFSET] |
| stx %i1, [%g7 + I1_OFFSET] |
| stx %i2, [%g7 + I2_OFFSET] |
| stx %i3, [%g7 + I3_OFFSET] |
| stx %i4, [%g7 + I4_OFFSET] |
| stx %i5, [%g7 + I5_OFFSET] |
| stx %i6, [%g7 + I6_OFFSET] |
| stx %i7, [%g7 + I7_OFFSET] |
| add %g7, STACK_WINDOW_SAVE_AREA_SIZE, %g7 |
| saved |
| retry |
| .endm |
| /* |
| * Macro used by the nucleus and the primary context 0 during normal fills. |
| */ |
| .macro FILL_NORMAL_HANDLER_KERNEL |
| ldx [%sp + STACK_BIAS + L0_OFFSET], %l0 |
| ldx [%sp + STACK_BIAS + L1_OFFSET], %l1 |
| ldx [%sp + STACK_BIAS + L2_OFFSET], %l2 |
| ldx [%sp + STACK_BIAS + L3_OFFSET], %l3 |
| ldx [%sp + STACK_BIAS + L4_OFFSET], %l4 |
| ldx [%sp + STACK_BIAS + L5_OFFSET], %l5 |
| ldx [%sp + STACK_BIAS + L6_OFFSET], %l6 |
| ldx [%sp + STACK_BIAS + L7_OFFSET], %l7 |
| ldx [%sp + STACK_BIAS + I0_OFFSET], %i0 |
| ldx [%sp + STACK_BIAS + I1_OFFSET], %i1 |
| ldx [%sp + STACK_BIAS + I2_OFFSET], %i2 |
| ldx [%sp + STACK_BIAS + I3_OFFSET], %i3 |
| ldx [%sp + STACK_BIAS + I4_OFFSET], %i4 |
| ldx [%sp + STACK_BIAS + I5_OFFSET], %i5 |
| ldx [%sp + STACK_BIAS + I6_OFFSET], %i6 |
| ldx [%sp + STACK_BIAS + I7_OFFSET], %i7 |
| restored |
| retry |
| .endm |
| /* |
| * Macro used by the userspace during normal fills. |
| */ |
| .macro FILL_NORMAL_HANDLER_USERSPACE |
| wr %g0, ASI_AIUP, %asi |
| ldxa [%sp + STACK_BIAS + L0_OFFSET] %asi, %l0 |
| ldxa [%sp + STACK_BIAS + L1_OFFSET] %asi, %l1 |
| ldxa [%sp + STACK_BIAS + L2_OFFSET] %asi, %l2 |
| ldxa [%sp + STACK_BIAS + L3_OFFSET] %asi, %l3 |
| ldxa [%sp + STACK_BIAS + L4_OFFSET] %asi, %l4 |
| ldxa [%sp + STACK_BIAS + L5_OFFSET] %asi, %l5 |
| ldxa [%sp + STACK_BIAS + L6_OFFSET] %asi, %l6 |
| ldxa [%sp + STACK_BIAS + L7_OFFSET] %asi, %l7 |
| ldxa [%sp + STACK_BIAS + I0_OFFSET] %asi, %i0 |
| ldxa [%sp + STACK_BIAS + I1_OFFSET] %asi, %i1 |
| ldxa [%sp + STACK_BIAS + I2_OFFSET] %asi, %i2 |
| ldxa [%sp + STACK_BIAS + I3_OFFSET] %asi, %i3 |
| ldxa [%sp + STACK_BIAS + I4_OFFSET] %asi, %i4 |
| ldxa [%sp + STACK_BIAS + I5_OFFSET] %asi, %i5 |
| ldxa [%sp + STACK_BIAS + I6_OFFSET] %asi, %i6 |
| ldxa [%sp + STACK_BIAS + I7_OFFSET] %asi, %i7 |
| restored |
| retry |
| .endm |
| .macro CLEAN_WINDOW_HANDLER |
| rdpr %cleanwin, %l0 |
| add %l0, 1, %l0 |
| wrpr %l0, 0, %cleanwin |
| mov %r0, %l0 |
| mov %r0, %l1 |
| mov %r0, %l2 |
| mov %r0, %l3 |
| mov %r0, %l4 |
| mov %r0, %l5 |
| mov %r0, %l6 |
| mov %r0, %l7 |
| mov %r0, %o0 |
| mov %r0, %o1 |
| mov %r0, %o2 |
| mov %r0, %o3 |
| mov %r0, %o4 |
| mov %r0, %o5 |
| mov %r0, %o6 |
| mov %r0, %o7 |
| retry |
| .endm |
| #endif /* __ASM__ */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/trap/trap.h |
|---|
| 0,0 → 1,44 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_TRAP_H_ |
| #define KERN_sparc64_TRAP_H_ |
| extern void trap_init(void); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/drivers/scr.h |
|---|
| 0,0 → 1,55 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_SCR_H_ |
| #define KERN_sparc64_SCR_H_ |
| #include <arch/types.h> |
| #include <genarch/ofw/ofw_tree.h> |
| typedef enum { |
| SCR_UNKNOWN, |
| SCR_ATYFB, |
| SCR_FFB, |
| SCR_CGSIX |
| } scr_type_t; |
| extern scr_type_t scr_type; |
| extern void scr_init(ofw_tree_node_t *node); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/drivers/z8530.h |
|---|
| 0,0 → 1,140 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_Z8530_H_ |
| #define KERN_sparc64_Z8530_H_ |
| #include <arch/types.h> |
| #include <arch/drivers/kbd.h> |
| #define Z8530_CHAN_A 4 |
| #define Z8530_CHAN_B 0 |
| #define WR0 0 |
| #define WR1 1 |
| #define WR2 2 |
| #define WR3 3 |
| #define WR4 4 |
| #define WR5 5 |
| #define WR6 6 |
| #define WR7 7 |
| #define WR8 8 |
| #define WR9 9 |
| #define WR10 10 |
| #define WR11 11 |
| #define WR12 12 |
| #define WR13 13 |
| #define WR14 14 |
| #define WR15 15 |
| #define RR0 0 |
| #define RR1 1 |
| #define RR2 2 |
| #define RR3 3 |
| #define RR8 8 |
| #define RR10 10 |
| #define RR12 12 |
| #define RR13 13 |
| #define RR14 14 |
| #define RR15 15 |
| /* Write Register 0 */ |
| #define WR0_TX_IP_RST (0x5<<3) /** Reset pending TX interrupt. */ |
| #define WR0_ERR_RST (0x6<<3) |
| /* Write Register 1 */ |
| #define WR1_RID (0x0<<3) /** Receive Interrupts Disabled. */ |
| #define WR1_RIFCSC (0x1<<3) /** Receive Interrupt on First Character or Special Condition. */ |
| #define WR1_IARCSC (0x2<<3) /** Interrupt on All Receive Characters or Special Conditions. */ |
| #define WR1_RISC (0x3<<3) /** Receive Interrupt on Special Condition. */ |
| #define WR1_PISC (0x1<<2) /** Parity Is Special Condition. */ |
| /* Write Register 3 */ |
| #define WR3_RX_ENABLE (0x1<<0) /** Rx Enable. */ |
| #define WR3_RX8BITSCH (0x3<<6) /** 8-bits per character. */ |
| /* Write Register 9 */ |
| #define WR9_MIE (0x1<<3) /** Master Interrupt Enable. */ |
| /* Read Register 0 */ |
| #define RR0_RCA (0x1<<0) /** Receive Character Available. */ |
| /** Structure representing the z8530 device. */ |
| typedef struct { |
| devno_t devno; |
| volatile uint8_t *reg; /** Memory mapped registers of the z8530. */ |
| } z8530_t; |
| static inline void z8530_write(z8530_t *dev, index_t chan, uint8_t reg, uint8_t val) |
| { |
| /* |
| * Registers 8-15 will automatically issue the Point High |
| * command as their bit 3 is 1. |
| */ |
| dev->reg[WR0+chan] = reg; /* select register */ |
| dev->reg[WR0+chan] = val; /* write value */ |
| } |
| static inline void z8530_write_a(z8530_t *dev, uint8_t reg, uint8_t val) |
| { |
| z8530_write(dev, Z8530_CHAN_A, reg, val); |
| } |
| static inline void z8530_write_b(z8530_t *dev, uint8_t reg, uint8_t val) |
| { |
| z8530_write(dev, Z8530_CHAN_B, reg, val); |
| } |
| static inline uint8_t z8530_read(z8530_t *dev, index_t chan, uint8_t reg) |
| { |
| /* |
| * Registers 8-15 will automatically issue the Point High |
| * command as their bit 3 is 1. |
| */ |
| dev->reg[WR0+chan] = reg; /* select register */ |
| return dev->reg[WR0+chan]; |
| } |
| static inline uint8_t z8530_read_a(z8530_t *dev, uint8_t reg) |
| { |
| return z8530_read(dev, Z8530_CHAN_A, reg); |
| } |
| static inline uint8_t z8530_read_b(z8530_t *dev, uint8_t reg) |
| { |
| return z8530_read(dev, Z8530_CHAN_B, reg); |
| } |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/drivers/tick.h |
|---|
| 0,0 → 1,46 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_TICK_H_ |
| #define KERN_sparc64_TICK_H_ |
| #include <arch/interrupt.h> |
| extern void tick_init(void); |
| extern void tick_interrupt(int n, istate_t *istate); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/drivers/pci.h |
|---|
| 0,0 → 1,71 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_PCI_H_ |
| #define KERN_sparc64_PCI_H_ |
| #include <arch/types.h> |
| #include <genarch/ofw/ofw_tree.h> |
| #include <arch/arch.h> |
| #include <arch/asm.h> |
| typedef enum pci_model pci_model_t; |
| typedef struct pci pci_t; |
| typedef struct pci_operations pci_operations_t; |
| enum pci_model { |
| PCI_UNKNOWN, |
| PCI_SABRE, |
| PCI_PSYCHO |
| }; |
| struct pci_operations { |
| void (* enable_interrupt)(pci_t *pci, int inr); |
| void (* clear_interrupt)(pci_t *pci, int inr); |
| }; |
| struct pci { |
| pci_model_t model; |
| pci_operations_t *op; |
| volatile uint64_t *reg; /**< Registers including interrupt registers. */ |
| }; |
| extern pci_t *pci_init(ofw_tree_node_t *node); |
| extern void pci_enable_interrupt(pci_t *pci, int inr); |
| extern void pci_clear_interrupt(pci_t *pci, int inr); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/drivers/fhc.h |
|---|
| 0,0 → 1,54 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_FHC_H_ |
| #define KERN_sparc64_FHC_H_ |
| #include <arch/types.h> |
| #include <genarch/ofw/ofw_tree.h> |
| typedef struct { |
| volatile uint32_t *uart_imap; |
| } fhc_t; |
| extern fhc_t *central_fhc; |
| extern fhc_t *fhc_init(ofw_tree_node_t *node); |
| extern void fhc_enable_interrupt(fhc_t *fhc, int inr); |
| extern void fhc_clear_interrupt(fhc_t *fhc, int inr); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/drivers/kbd.h |
|---|
| 0,0 → 1,54 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_KBD_H_ |
| #define KERN_sparc64_KBD_H_ |
| #include <arch/types.h> |
| #include <genarch/ofw/ofw_tree.h> |
| typedef enum { |
| KBD_UNKNOWN, |
| KBD_Z8530, |
| KBD_NS16550 |
| } kbd_type_t; |
| extern kbd_type_t kbd_type; |
| extern void kbd_init(ofw_tree_node_t *node); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/drivers/ns16550.h |
|---|
| 0,0 → 1,102 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_NS16550_H_ |
| #define KERN_sparc64_NS16550_H_ |
| #include <arch/types.h> |
| #include <arch/drivers/kbd.h> |
| /* NS16550 registers */ |
| #define RBR_REG 0 /** Receiver Buffer Register. */ |
| #define IER_REG 1 /** Interrupt Enable Register. */ |
| #define IIR_REG 2 /** Interrupt Ident Register (read). */ |
| #define FCR_REG 2 /** FIFO control register (write). */ |
| #define LCR_REG 3 /** Line Control register. */ |
| #define LSR_REG 5 /** Line Status Register. */ |
| #define IER_ERBFI 0x01 /** Enable Receive Buffer Full Interrupt. */ |
| #define LCR_DLAB 0x80 /** Divisor Latch Access bit. */ |
| /** Structure representing the ns16550 device. */ |
| typedef struct { |
| devno_t devno; |
| volatile uint8_t *reg; /** Memory mapped registers of the ns16550. */ |
| } ns16550_t; |
| static inline uint8_t ns16550_rbr_read(ns16550_t *dev) |
| { |
| return dev->reg[RBR_REG]; |
| } |
| static inline uint8_t ns16550_ier_read(ns16550_t *dev) |
| { |
| return dev->reg[IER_REG]; |
| } |
| static inline void ns16550_ier_write(ns16550_t *dev, uint8_t v) |
| { |
| dev->reg[IER_REG] = v; |
| } |
| static inline uint8_t ns16550_iir_read(ns16550_t *dev) |
| { |
| return dev->reg[IIR_REG]; |
| } |
| static inline void ns16550_fcr_write(ns16550_t *dev, uint8_t v) |
| { |
| dev->reg[FCR_REG] = v; |
| } |
| static inline uint8_t ns16550_lcr_read(ns16550_t *dev) |
| { |
| return dev->reg[LCR_REG]; |
| } |
| static inline void ns16550_lcr_write(ns16550_t *dev, uint8_t v) |
| { |
| dev->reg[LCR_REG] = v; |
| } |
| static inline uint8_t ns16550_lsr_read(ns16550_t *dev) |
| { |
| return dev->reg[LSR_REG]; |
| } |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/drivers/fb.h |
|---|
| 0,0 → 1,41 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_FB_H_ |
| #define KERN_sparc64_FB_H_ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/interrupt.h |
|---|
| 0,0 → 1,76 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64interrupt sparc64 |
| * @ingroup interrupt |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_INTERRUPT_H_ |
| #define KERN_sparc64_INTERRUPT_H_ |
| #include <arch/types.h> |
| #include <arch/regdef.h> |
| #define IVT_ITEMS 15 |
| #define IVT_FIRST 1 |
| /* This needs to be defined for inter-architecture API portability. */ |
| #define VECTOR_TLB_SHOOTDOWN_IPI 0 |
| enum { |
| IPI_TLB_SHOOTDOWN = VECTOR_TLB_SHOOTDOWN_IPI |
| }; |
| typedef struct { |
| uint64_t tnpc; |
| uint64_t tpc; |
| uint64_t tstate; |
| } istate_t; |
| static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) |
| { |
| istate->tpc = retaddr; |
| } |
| static inline int istate_from_uspace(istate_t *istate) |
| { |
| return !(istate->tstate & TSTATE_PRIV_BIT); |
| } |
| static inline unative_t istate_get_pc(istate_t *istate) |
| { |
| return istate->tpc; |
| } |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/atomic.h |
|---|
| 0,0 → 1,136 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_ATOMIC_H_ |
| #define KERN_sparc64_ATOMIC_H_ |
| #include <arch/barrier.h> |
| #include <arch/types.h> |
| /** Atomic add operation. |
| * |
| * Use atomic compare and swap operation to atomically add signed value. |
| * |
| * @param val Atomic variable. |
| * @param i Signed value to be added. |
| * |
| * @return Value of the atomic variable as it existed before addition. |
| */ |
| static inline long atomic_add(atomic_t *val, int i) |
| { |
| uint64_t a, b; |
| do { |
| volatile uintptr_t x = (uint64_t) &val->count; |
| a = *((uint64_t *) x); |
| b = a + i; |
| asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)), "+r" (b) : "r" (a)); |
| } while (a != b); |
| return a; |
| } |
| static inline long atomic_preinc(atomic_t *val) |
| { |
| return atomic_add(val, 1) + 1; |
| } |
| static inline long atomic_postinc(atomic_t *val) |
| { |
| return atomic_add(val, 1); |
| } |
| static inline long atomic_predec(atomic_t *val) |
| { |
| return atomic_add(val, -1) - 1; |
| } |
| static inline long atomic_postdec(atomic_t *val) |
| { |
| return atomic_add(val, -1); |
| } |
| static inline void atomic_inc(atomic_t *val) |
| { |
| (void) atomic_add(val, 1); |
| } |
| static inline void atomic_dec(atomic_t *val) |
| { |
| (void) atomic_add(val, -1); |
| } |
| static inline long test_and_set(atomic_t *val) |
| { |
| uint64_t v = 1; |
| volatile uintptr_t x = (uint64_t) &val->count; |
| asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), "+r" (v) : "r" (0)); |
| return v; |
| } |
| static inline void atomic_lock_arch(atomic_t *val) |
| { |
| uint64_t tmp1 = 1; |
| uint64_t tmp2 = 0; |
| volatile uintptr_t x = (uint64_t) &val->count; |
| asm volatile ( |
| "0:\n" |
| "casx %0, %3, %1\n" |
| "brz %1, 2f\n" |
| "nop\n" |
| "1:\n" |
| "ldx %0, %2\n" |
| "brz %2, 0b\n" |
| "nop\n" |
| "ba 1b\n" |
| "nop\n" |
| "2:\n" |
| : "+m" (*((uint64_t *) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0) |
| ); |
| /* |
| * Prevent critical section code from bleeding out this way up. |
| */ |
| CS_ENTER_BARRIER(); |
| } |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/boot/boot.h |
|---|
| 0,0 → 1,92 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_BOOT_H_ |
| #define KERN_sparc64_BOOT_H_ |
| #define VMA 0x400000 |
| #define LMA VMA |
| #ifndef __ASM__ |
| #ifndef __LINKER__ |
| #include <config.h> |
| #include <arch/types.h> |
| #include <genarch/ofw/ofw_tree.h> |
| #define TASKMAP_MAX_RECORDS 32 |
| #define MEMMAP_MAX_RECORDS 32 |
| typedef struct { |
| void * addr; |
| uint32_t size; |
| } utask_t; |
| typedef struct { |
| uint32_t count; |
| utask_t tasks[TASKMAP_MAX_RECORDS]; |
| } taskmap_t; |
| typedef struct { |
| uintptr_t start; |
| uint32_t size; |
| } memzone_t; |
| typedef struct { |
| uint32_t total; |
| uint32_t count; |
| memzone_t zones[MEMMAP_MAX_RECORDS]; |
| } memmap_t; |
| /** Bootinfo structure. |
| * |
| * Must be in sync with bootinfo structure used by the boot loader. |
| */ |
| typedef struct { |
| uintptr_t physmem_start; |
| taskmap_t taskmap; |
| memmap_t memmap; |
| ballocs_t ballocs; |
| ofw_tree_node_t *ofw_root; |
| } bootinfo_t; |
| extern bootinfo_t bootinfo; |
| #endif |
| #endif |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/sparc64.h |
|---|
| 0,0 → 1,45 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_SPARC64_H_ |
| #define KERN_sparc64_SPARC64_H_ |
| #include <interrupt.h> |
| extern void interrupt_register(int n, const char *name, iroutine f); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/fpu_context.h |
|---|
| 0,0 → 1,51 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_FPU_CONTEXT_H_ |
| #define KERN_sparc64_FPU_CONTEXT_H_ |
| #include <arch/types.h> |
| #define ARCH_HAS_FPU |
| #define FPU_CONTEXT_ALIGN 8 |
| typedef struct { |
| uint64_t d[32]; |
| uint64_t fsr; |
| } fpu_context_t; |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/context.h |
|---|
| 0,0 → 1,84 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_CONTEXT_H_ |
| #define KERN_sparc64_CONTEXT_H_ |
| #include <arch/stack.h> |
| #include <arch/types.h> |
| #include <align.h> |
| #define SP_DELTA STACK_WINDOW_SAVE_AREA_SIZE |
| #ifdef context_set |
| #undef context_set |
| #endif |
| #define context_set(c, _pc, stack, size) \ |
| (c)->pc = ((uintptr_t) _pc) - 8; \ |
| (c)->sp = ((uintptr_t) stack) + ALIGN_UP((size), \ |
| STACK_ALIGNMENT) - (STACK_BIAS + SP_DELTA); \ |
| (c)->fp = -STACK_BIAS |
| /* |
| * Save only registers that must be preserved across |
| * function calls. |
| */ |
| typedef struct { |
| uintptr_t sp; /* %o6 */ |
| uintptr_t pc; /* %o7 */ |
| uint64_t i0; |
| uint64_t i1; |
| uint64_t i2; |
| uint64_t i3; |
| uint64_t i4; |
| uint64_t i5; |
| uintptr_t fp; /* %i6 */ |
| uintptr_t i7; |
| uint64_t l0; |
| uint64_t l1; |
| uint64_t l2; |
| uint64_t l3; |
| uint64_t l4; |
| uint64_t l5; |
| uint64_t l6; |
| uint64_t l7; |
| ipl_t ipl; |
| } context_t; |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/regdef.h |
|---|
| 0,0 → 1,64 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_REGDEF_H_ |
| #define KERN_sparc64_REGDEF_H_ |
| #define PSTATE_IE_BIT (1 << 1) |
| #define PSTATE_AM_BIT (1 << 3) |
| #define PSTATE_AG_BIT (1 << 0) |
| #define PSTATE_IG_BIT (1 << 11) |
| #define PSTATE_MG_BIT (1 << 10) |
| #define PSTATE_PRIV_BIT (1 << 2) |
| #define PSTATE_PEF_BIT (1 << 4) |
| #define TSTATE_PSTATE_SHIFT 8 |
| #define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT << TSTATE_PSTATE_SHIFT) |
| #define TSTATE_IE_BIT (PSTATE_IE_BIT << TSTATE_PSTATE_SHIFT) |
| #define TSTATE_PEF_BIT (PSTATE_PEF_BIT << TSTATE_PSTATE_SHIFT) |
| #define TSTATE_CWP_MASK 0x1f |
| #define WSTATE_NORMAL(n) (n) |
| #define WSTATE_OTHER(n) ((n) << 3) |
| #define UPA_CONFIG_MID_SHIFT 17 |
| #define UPA_CONFIG_MID_MASK 0x1f |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/cycle.h |
|---|
| 0,0 → 1,48 |
| /* |
| * Copyright (c) 2006 Martin Decky |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_CYCLE_H_ |
| #define KERN_sparc64_CYCLE_H_ |
| #include <arch/asm.h> |
| static inline uint64_t get_cycle(void) |
| { |
| return tick_read(); |
| } |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/console.h |
|---|
| 0,0 → 1,44 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_CONSOLE_H_ |
| #define KERN_sparc64_CONSOLE_H_ |
| extern void kkbdpoll(void *arg); |
| extern void standalone_sparc64_console_init(void); |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/elf.h |
|---|
| 0,0 → 1,45 |
| /* |
| * Copyright (c) 2006 Sergey Bondari |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_ELF_H_ |
| #define KERN_sparc64_ELF_H_ |
| #define ELF_MACHINE EM_SPARCV9 |
| #define ELF_DATA_ENCODING ELFDATA2MSB |
| #define ELF_CLASS ELFCLASS64 |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/arg.h |
|---|
| 0,0 → 1,43 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_ARG_H_ |
| #define KERN_sparc64_ARG_H_ |
| #include <stdarg.h> |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/arch.h |
|---|
| 0,0 → 1,51 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** |
| * @file |
| * @brief Various sparc64-specific macros. |
| */ |
| #ifndef KERN_sparc64_ARCH_H_ |
| #define KERN_sparc64_ARCH_H_ |
| #define ASI_AIUP 0x10 /** Access to primary context with user privileges. */ |
| #define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ |
| #define ASI_NUCLEUS_QUAD_LDD 0x24 /** ASI for 16-byte atomic loads. */ |
| #define ASI_DCACHE_TAG 0x47 /** ASI D-Cache Tag. */ |
| #define ASI_UPA_CONFIG 0x4a /** ASI of the UPA_CONFIG register. */ |
| #define NWINDOWS 8 /** Number of register window sets. */ |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/proc/task.h |
|---|
| 0,0 → 1,47 |
| /* |
| * Copyright (c) 2006 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64proc |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_TASK_H_ |
| #define KERN_sparc64_TASK_H_ |
| typedef struct { |
| } task_arch_t; |
| #define task_create_arch(t) |
| #define task_destroy_arch(t) |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/proc/thread.h |
|---|
| 0,0 → 1,49 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64proc |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_THREAD_H_ |
| #define KERN_sparc64_THREAD_H_ |
| #include <arch/types.h> |
| #include <arch/arch.h> |
| typedef struct { |
| /** Buffer for register windows with userspace content. */ |
| uint8_t *uspace_window_buffer; |
| } thread_arch_t; |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/faddr.h |
|---|
| 0,0 → 1,45 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_FADDR_H_ |
| #define KERN_sparc64_FADDR_H_ |
| #include <arch/types.h> |
| #define FADDR(fptr) ((uintptr_t) (fptr)) |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/register.h |
|---|
| 0,0 → 1,140 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_REGISTER_H_ |
| #define KERN_sparc64_REGISTER_H_ |
| #include <arch/regdef.h> |
| #include <arch/types.h> |
| /** Version Register. */ |
| union ver_reg { |
| uint64_t value; |
| struct { |
| uint16_t manuf; /**< Manufacturer code. */ |
| uint16_t impl; /**< Implementation code. */ |
| uint8_t mask; /**< Mask set revision. */ |
| unsigned : 8; |
| uint8_t maxtl; |
| unsigned : 3; |
| unsigned maxwin : 5; |
| } __attribute__ ((packed)); |
| }; |
| typedef union ver_reg ver_reg_t; |
| /** Processor State Register. */ |
| union pstate_reg { |
| uint64_t value; |
| struct { |
| uint64_t : 52; |
| unsigned ig : 1; /**< Interrupt Globals. */ |
| unsigned mg : 1; /**< MMU Globals. */ |
| unsigned cle : 1; /**< Current Little Endian. */ |
| unsigned tle : 1; /**< Trap Little Endian. */ |
| unsigned mm : 2; /**< Memory Model. */ |
| unsigned red : 1; /**< RED state. */ |
| unsigned pef : 1; /**< Enable floating-point. */ |
| unsigned am : 1; /**< 32-bit Address Mask. */ |
| unsigned priv : 1; /**< Privileged Mode. */ |
| unsigned ie : 1; /**< Interrupt Enable. */ |
| unsigned ag : 1; /**< Alternate Globals*/ |
| } __attribute__ ((packed)); |
| }; |
| typedef union pstate_reg pstate_reg_t; |
| /** TICK Register. */ |
| union tick_reg { |
| uint64_t value; |
| struct { |
| unsigned npt : 1; /**< Non-privileged Trap enable. */ |
| uint64_t counter : 63; /**< Elapsed CPU clck cycle counter. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tick_reg tick_reg_t; |
| /** TICK_compare Register. */ |
| union tick_compare_reg { |
| uint64_t value; |
| struct { |
| unsigned int_dis : 1; /**< TICK_INT interrupt disabled flag. */ |
| uint64_t tick_cmpr : 63; /**< Compare value for TICK interrupts. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union tick_compare_reg tick_compare_reg_t; |
| /** SOFTINT Register. */ |
| union softint_reg { |
| uint64_t value; |
| struct { |
| uint64_t : 47; |
| unsigned stick_int : 1; |
| unsigned int_level : 15; |
| unsigned tick_int : 1; |
| } __attribute__ ((packed)); |
| }; |
| typedef union softint_reg softint_reg_t; |
| /** Floating-point Registers State Register. */ |
| union fprs_reg { |
| uint64_t value; |
| struct { |
| uint64_t : 61; |
| unsigned fef : 1; |
| unsigned du : 1; |
| unsigned dl : 1; |
| } __attribute__ ((packed)); |
| }; |
| typedef union fprs_reg fprs_reg_t; |
| /** UPA_CONFIG register. |
| * |
| * Note that format of this register differs significantly from |
| * processor version to version. The format defined here |
| * is the common subset for all supported processor versions. |
| */ |
| union upa_config { |
| uint64_t value; |
| struct { |
| uint64_t : 34; |
| unsigned pcon : 8; /**< Processor configuration. */ |
| unsigned mid : 5; /**< Module (processor) ID register. */ |
| unsigned pcap : 17; /**< Processor capabilities. */ |
| } __attribute__ ((packed)); |
| }; |
| typedef union upa_config upa_config_t; |
| #endif |
| /** @} |
| */ |
| /branches/sparc/kernel/arch/sparc64/include/debug.h |
|---|
| 0,0 → 1,41 |
| /* |
| * Copyright (c) 2005 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup sparc64debug |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef KERN_sparc64_DEBUG_H_ |
| #define KERN_sparc64_DEBUG_H_ |
| #endif |
| /** @} |
| */ |