| /branches/sparc/kernel/arch/sparc64/include/mm/cache_spec.h |
|---|
| 38,7 → 38,8 |
| /* |
| * The following macros are valid for the following processors: |
| * |
| * UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III Cu |
| * UltraSPARC, UltraSPARC II, UltraSPARC IIi, UltraSPARC III, |
| * UltraSPARC III+, UltraSPARC IV, UltraSPARC IV+ |
| * |
| * Should we support other UltraSPARC processors, we need to make sure that |
| * the macros are defined correctly for them. |
| /branches/sparc/kernel/arch/sparc64/include/mm/tlb.h |
|---|
| 176,7 → 176,6 |
| /** I-/D-TLB Tag Read Register. */ |
| union tlb_tag_read_reg { |
| // TODO have a look at how non-8kB pages will be treated |
| uint64_t value; |
| struct { |
| uint64_t vpn : 51; /**< Virtual Address bits 63:13. */ |
| 431,7 → 430,8 |
| * @param entry TLB Entry index. |
| * @param value Value to be written. |
| */ |
| static inline void itlb_data_access_write(int tlb, index_t entry, uint64_t value) |
| static inline void itlb_data_access_write(int tlb, index_t entry, |
| uint64_t value) |
| { |
| itlb_data_access_addr_t reg; |
| 465,7 → 465,8 |
| * @param entry TLB Entry index. |
| * @param value Value to be written. |
| */ |
| static inline void dtlb_data_access_write(int tlb, index_t entry, uint64_t value) |
| static inline void dtlb_data_access_write(int tlb, index_t entry, |
| uint64_t value) |
| { |
| dtlb_data_access_addr_t reg; |
| /branches/sparc/kernel/arch/sparc64/src/smp/smp.c |
|---|
| 119,7 → 119,8 |
| if (is_us() || is_us_iii()) { |
| node = ofw_tree_find_child_by_device_type(cpus_parent(), "cpu"); |
| for (i = 0; node; node = ofw_tree_find_peer_by_device_type(node, "cpu"), i++) |
| for (i = 0; node; |
| node = ofw_tree_find_peer_by_device_type(node, "cpu"), i++) |
| wakeup_cpu(node); |
| } else if (is_us_iv()) { |
| node = ofw_tree_find_child(cpus_parent(), "cmp"); |
| /branches/sparc/kernel/arch/sparc64/src/console.c |
|---|
| 201,6 → 201,11 |
| ns16550_release(); |
| break; |
| #endif |
| #ifdef CONFIG_SGCN |
| case KBD_SGCN: |
| sgcn_release(); |
| break; |
| #endif |
| default: |
| break; |
| } |
| /branches/sparc/kernel/arch/sparc64/src/cpu/cpu.c |
|---|
| 99,10 → 99,12 |
| node = ofw_tree_find_child(cpus_parent(), "cmp"); |
| while (node) { |
| int f; |
| f = find_cpu_frequency(ofw_tree_find_child(node, "cpu@0")); |
| f = find_cpu_frequency( |
| ofw_tree_find_child(node, "cpu@0")); |
| if (f != -1) |
| clock_frequency = (uint32_t) f; |
| f = find_cpu_frequency(ofw_tree_find_child(node, "cpu@1")); |
| f = find_cpu_frequency( |
| ofw_tree_find_child(node, "cpu@1")); |
| if (f != -1) |
| clock_frequency = (uint32_t) f; |
| node = ofw_tree_find_peer_by_name(node, "cmp"); |
| /branches/sparc/kernel/arch/sparc64/src/mm/tlb.c |
|---|
| 472,9 → 472,9 |
| "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
| sfsr.ow, sfsr.fv); |
| #elif defined (US3) |
| printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, " |
| "fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, |
| sfsr.ow, sfsr.fv); |
| printf("DTLB SFSR: nf=%d, asi=%#x, tm=%d, ft=%#x, e=%d, ct=%d, pr=%d, " |
| "w=%d, ow=%d, fv=%d\n", sfsr.nf, sfsr.asi, sfsr.tm, sfsr.ft, |
| sfsr.e, sfsr.ct, sfsr.pr, sfsr.w, sfsr.ow, sfsr.fv); |
| #endif |
| printf("DTLB SFAR: address=%p\n", sfar); |
| /branches/sparc/kernel/arch/sparc64/src/drivers/scr.c |
|---|
| 175,7 → 175,14 |
| panic("Unexpected type.\n"); |
| } |
| fb_init(fb_addr, fb_width, fb_height, fb_scanline, visual); |
| fb_properties_t props; |
| props.addr = fb_addr; |
| props.fb_start = 0; |
| props.x = fb_width; |
| props.y = fb_height; |
| props.scan = fb_scanline; |
| props.visual = visual; |
| fb_init(&props); |
| } |
| /** @} |
| /branches/sparc/kernel/arch/sparc64/src/drivers/sgcn.c |
|---|
| 175,7 → 175,8 |
| ddi_parea_register(&sram_parea); |
| sysinfo_set_item_val("sram.area.size", NULL, MAPPED_AREA_SIZE); |
| sysinfo_set_item_val("sram.address.physical", NULL, sram_begin_physical); |
| sysinfo_set_item_val("sram.address.physical", NULL, |
| sram_begin_physical); |
| } |
| /** |
| /branches/sparc/kernel/arch/sparc64/src/start.S |
|---|
| 96,7 → 96,7 |
| wrpr %g0, NWINDOWS - 1, %cleanwin ! prevent needless clean_window |
| ! traps for kernel |
| wrpr %g0, 0, %wstate ! use the default spill/fill trap |
| wrpr %g0, 0, %wstate ! use default spill/fill trap |
| wrpr %g0, 0, %tl ! TL = 0, primary context |
| ! register is used |