| /branches/sparc/boot/arch/sparc64/Makefile.inc |
|---|
| 28,13 → 28,11 |
| TMP=distroot |
| ifeq ($(OFW_IMPLEMENTATION),smart_firmware) |
| DEFS += -DSMART_FIRMWARE |
| ifeq ($(CONFIG_AOUT_ISOFS_B),n) |
| SILO_PACKAGE=silo.patched.tar.gz |
| endif |
| ifeq ($(OFW_IMPLEMENTATION),open_boot) |
| DEFS += -DOPEN_BOOT |
| ifeq ($(CONFIG_AOUT_ISOFS_B),y) |
| SILO_PACKAGE=silo.tar.gz |
| endif |
| /branches/sparc/boot/arch/sparc64/loader/asm.S |
|---|
| 108,15 → 108,36 |
| */ |
| /* |
| * US-III processors have a write-invalidate cache, so flushing it is |
| * not required. We only use the FLUSH instruction to flush the |
| * pipeline. |
| */ |
| #ifdef US |
| call icache_flush |
| #endif |
| * US3 processors have a write-invalidate cache, so explicitly |
| * invalidating it is not required. Whether to invalidate I-cache |
| * or not is decided according to the value of the ver.impl bits |
| * in the Version register. |
| */ |
| sethi 0x40000, %g0 |
| ! the lowest/greatest value of ver.impl for US3 |
| #define FIRST_US3_CPU 0x14 |
| #define LAST_US3_CPU 0x19 |
| rdpr %ver, %g2 ! autodetect CPU using the Version register |
| sllx %g2, 16, %g2 ! extract ver.impl bits |
| srlx %g2, 48, %g2 |
| addcc %g2, -FIRST_US3_CPU, %g0 ! flush if ver.impl < FISRT_US3_CPU |
| bl 0f |
| nop |
| addcc %g2, -LAST_US3_CPU, %g0 ! flush if ver.impl > LAST_US3_CPU |
| bg 0f |
| nop |
| ba 1f |
| nop |
| 0: |
| call icache_flush |
| nop |
| 1: |
| membar #StoreStore |
| membar #StoreStore |
| /* |
| * Flush the instruction pipeline. |
| */ |
| flush %i7 |
| mov %o0, %l1 |
| 143,7 → 164,6 |
| retl |
| ! SF Erratum #51 |
| nop |
| .global ofw |
| ofw: |
| save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
| /branches/sparc/boot/arch/sparc64/loader/ofwarch.c |
|---|
| 56,23 → 56,19 |
| return flag != -1; |
| } |
| /* |
| * Node among whose children the CPU nodes are located. |
| */ |
| #if defined (OPEN_BOOT) |
| #define CPUS_PARENT_NODE ofw_root |
| #elif defined (SMART_FIRMWARE) |
| #define CPUS_PARENT_NODE ofw_find_device("/ssm@0,0") |
| #endif |
| int ofw_cpu(void) |
| { |
| char type_name[BUF_SIZE]; |
| phandle node; |
| node = ofw_get_child_node(CPUS_PARENT_NODE); |
| phandle ssm; |
| ssm = ofw_find_device("/ssm@0,0"); |
| if (ssm == -1) { |
| node = ofw_get_child_node(ofw_root); |
| } else { |
| node = ofw_get_child_node(ssm); |
| } |
| if (node == 0 || node == -1) { |
| printf("Could not find any child nodes of the root node.\n"); |
| return 0; |
| 82,9 → 78,9 |
| asm volatile ("ldxa [%1] %2, %0\n" |
| : "=r" (current_mid) |
| : "r" (0), "i" (ASI_UPA_CONFIG)); |
| current_mid >>= UPA_CONFIG_MID_SHIFT; |
| current_mid &= UPA_CONFIG_MID_MASK; |
| : "r" (0), "i" (ASI_ICBUS_CONFIG)); |
| current_mid >>= ICBUS_CONFIG_MID_SHIFT; |
| current_mid &= ICBUS_CONFIG_MID_MASK; |
| int cpus; |
| /branches/sparc/boot/arch/sparc64/loader/register.h |
|---|
| 33,8 → 33,8 |
| #define PSTATE_PRIV_BIT 4 |
| #define PSTATE_AM_BIT 8 |
| #define ASI_UPA_CONFIG 0x4a |
| #define UPA_CONFIG_MID_SHIFT 17 |
| #define UPA_CONFIG_MID_MASK 0x1f |
| #define ASI_ICBUS_CONFIG 0x4a |
| #define ICBUS_CONFIG_MID_SHIFT 17 |
| #define ICBUS_CONFIG_MID_MASK 0x1f |
| #endif |
| /branches/sparc/boot/arch/ppc32/Makefile.inc |
|---|
| 26,8 → 26,6 |
| # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| # |
| DEFS += -DSMART_FIRMWARE |
| build: $(BASE)/image.boot |
| $(BASE)/image.boot: depend arch/$(ARCH)/loader/image.boot |