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Ignore whitespace Rev 3581 → Rev 3582

/branches/sparc/boot/genarch/ofw_tree.c
121,7 → 121,6
memcpy(current_node->da_name, &path[i], len);
current_node->da_name[len] = '\0';
/*
* Recursively process the potential child node.
*/
/branches/sparc/boot/arch/sparc64/loader/asm.S
110,28 → 110,18
/*
* US3 processors have a write-invalidate cache, so explicitly
* invalidating it is not required. Whether to invalidate I-cache
* or not is decided according to the value of the ver.impl bits
* in the Version register.
* or not is decided according to the value of the global
* "subarchitecture" variable (set in the bootstrap).
*/
! the lowest/greatest value of ver.impl for US3
#define FIRST_US3_CPU 0x14
#define LAST_US3_CPU 0x19
rdpr %ver, %g2 ! autodetect CPU using the Version register
sllx %g2, 16, %g2 ! extract ver.impl bits
srlx %g2, 48, %g2
addcc %g2, -FIRST_US3_CPU, %g0 ! flush if ver.impl < FISRT_US3_CPU
bl 0f
set subarchitecture, %g2
ldub [%g2], %g2
cmp %g2, 3
be 1f
nop
addcc %g2, -LAST_US3_CPU, %g0 ! flush if ver.impl > LAST_US3_CPU
bg 0f
nop
ba 1f
nop
0:
call icache_flush
nop
1:
membar #StoreStore
/*
/branches/sparc/boot/arch/sparc64/loader/main.c
39,6 → 39,10
#include <string.h>
 
bootinfo_t bootinfo;
 
/** UltraSPARC subarchitecture - 1 for US, 3 for US3 */
uint8_t subarchitecture;
 
component_t components[COMPONENTS];
 
char *release = RELEASE;
63,6 → 67,21
release, revision, timestamp);
}
 
#define FIRST_US3_CPU 0x14
#define LAST_US3_CPU 0x19
static void detect_subarchitecture(void)
{
uint64_t v;
asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
v = (v << 16) >> 48;
if ((v >= FIRST_US3_CPU) && (v <= LAST_US3_CPU)) {
subarchitecture = SUBARCH_US3;
} else if (v < FIRST_US3_CPU) {
subarchitecture = SUBARCH_US;
}
}
 
void bootstrap(void)
{
void *base = (void *) KERNEL_VIRTUAL_ADDRESS;
72,6 → 91,7
 
version_print();
detect_subarchitecture();
init_components(components);
 
if (!ofw_get_physmem_start(&bootinfo.physmem_start)) {
/branches/sparc/boot/arch/sparc64/loader/main.h
41,6 → 41,9
#define BSP_PROCESSOR 1
#define AP_PROCESSOR 0
 
#define SUBARCH_US 1
#define SUBARCH_US3 3
 
typedef struct {
void *addr;
uint32_t size;
/branches/sparc/boot/arch/sparc64/loader/ofwarch.c
40,6 → 40,8
#include "main.h"
#include "asm.h"
 
extern uint8_t subarchitecture;
 
void write(const char *str, const int len)
{
int i;
56,46 → 58,28
return flag != -1;
}
 
int ofw_cpu(void)
static int wake_cpus_in_node(phandle child, uint64_t current_mid)
{
int cpus;
char type_name[BUF_SIZE];
phandle node;
phandle ssm;
 
ssm = ofw_find_device("/ssm@0,0");
if (ssm == -1) {
node = ofw_get_child_node(ofw_root);
} else {
node = ofw_get_child_node(ssm);
}
 
if (node == 0 || node == -1) {
printf("Could not find any child nodes of the root node.\n");
return 0;
}
uint64_t current_mid;
asm volatile ("ldxa [%1] %2, %0\n"
: "=r" (current_mid)
: "r" (0), "i" (ASI_ICBUS_CONFIG));
current_mid >>= ICBUS_CONFIG_MID_SHIFT;
current_mid &= ICBUS_CONFIG_MID_MASK;
 
int cpus;
for (cpus = 0; node != 0 && node != -1; node = ofw_get_peer_node(node),
cpus++) {
if (ofw_get_property(node, "device_type", type_name,
for (cpus = 0; child != 0 && child != -1;
child = ofw_get_peer_node(child), cpus++) {
if (ofw_get_property(child, "device_type", type_name,
sizeof(type_name)) > 0) {
if (strcmp(type_name, "cpu") == 0) {
uint32_t mid;
/* "upa-portid" for US, "portid" for US-III */
/*
* "upa-portid" for US, "portid" for US-III,
* "cpuid" for US-IV*
*/
if (ofw_get_property(
node, "upa-portid",
child, "upa-portid",
&mid, sizeof(mid)) <= 0
&& ofw_get_property(node, "portid",
&& ofw_get_property(child, "portid",
&mid, sizeof(mid)) <= 0
&& ofw_get_property(child, "cpuid",
&mid, sizeof(mid)) <= 0)
continue;
103,8 → 87,9
/*
* Start secondary processor.
*/
printf("Starting CPU: %d.\n", mid);
(void) ofw_call("SUNW,start-cpu", 3, 1,
NULL, node, KERNEL_VIRTUAL_ADDRESS,
NULL, child, KERNEL_VIRTUAL_ADDRESS,
bootinfo.physmem_start |
AP_PROCESSOR);
}
115,6 → 100,58
return cpus;
}
 
int ofw_cpu(void)
{
int cpus;
phandle node;
phandle subnode;
phandle ssm;
phandle cmp;
char name[BUF_SIZE];
 
/* get the current CPU MID */
uint64_t current_mid;
asm volatile ("ldxa [%1] %2, %0\n"
: "=r" (current_mid)
: "r" (0), "i" (ASI_ICBUS_CONFIG));
current_mid >>= ICBUS_CONFIG_MID_SHIFT;
 
if (subarchitecture == SUBARCH_US) {
current_mid &= ICBUS_CONFIG_MID_MASK_US;
} else if (subarchitecture == SUBARCH_US3) {
current_mid &= ICBUS_CONFIG_MID_MASK_US3;
} else {
printf("MID format unknown for this subarchitecture.");
return 0;
}
 
/* wake up CPUs */
ssm = ofw_find_device("/ssm@0,0");
if (ssm == -1) {
node = ofw_get_child_node(ofw_root);
cpus = wake_cpus_in_node(node, current_mid);
} else {
node = ofw_get_child_node(ssm);
cpus = wake_cpus_in_node(node, current_mid);
while (node != 0 && node != -1) {
if (ofw_get_property(node, "name", name,
sizeof(name)) > 0) {
if (strcmp(name, "cmp") == 0) {
printf("nasel jsem dalsi CPU");
subnode = ofw_get_child_node(node);
cpus += wake_cpus_in_node(subnode,
current_mid);
}
}
node = ofw_get_peer_node(node);
}
}
return cpus;
}
 
/** Get physical memory starting address.
*
* @param start Pointer to variable where the physical memory starting
/branches/sparc/boot/arch/sparc64/loader/register.h
33,8 → 33,9
#define PSTATE_PRIV_BIT 4
#define PSTATE_AM_BIT 8
 
#define ASI_ICBUS_CONFIG 0x4a
#define ICBUS_CONFIG_MID_SHIFT 17
#define ICBUS_CONFIG_MID_MASK 0x1f
#define ASI_ICBUS_CONFIG 0x4a
#define ICBUS_CONFIG_MID_SHIFT 17
#define ICBUS_CONFIG_MID_MASK_US 0x1f
#define ICBUS_CONFIG_MID_MASK_US3 0x3ff
 
#endif