| /branches/dynload/kernel/arch/ia32/include/barrier.h |
|---|
| 95,6 → 95,15 |
| # endif |
| #endif |
| /* |
| * On ia32, the hardware takes care about instruction and data cache coherence, |
| * even on SMP systems. We issue a write barrier to be sure that writes |
| * queueing in the store buffer drain to the memory (even though it would be |
| * sufficient for them to drain to the D-cache). |
| */ |
| #define smc_coherence(a) write_barrier() |
| #define smc_coherence_block(a, l) write_barrier() |
| #endif |
| /** @} |