| 0,0 → 1,216 |
|---|
| #include <unistd.h> |
| #include <ddi.h> |
| #include <libarch/ddi.h> |
| #include <stdio.h> |
| |
| #include "internal.h" |
| |
| /* physical addresses and offsets */ |
| //#define U2P_BASE 0x1FE00000000 |
| #define U2P_BASE 0x1c800000000 |
| #define PCI_CONF_OFFSET 0x001000000 |
| #define PCI_CONF_SIZE 0x001000000 |
| #define PCI_CONF_BASE (U2P_BASE + PCI_CONF_OFFSET) |
| |
| /* virtual address of PCI configuration space */ |
| static void *conf_addr = 0; |
| |
| /* |
| * virtual address of specified PCI configuration register: |
| * bus ... bus number (0 for top level PCI bus B, 1 for top level PCI bus A) |
| * dev ... device number (0 - 15) |
| * fn ... function number (0 - 7) |
| * reg ... register number (register's position within PCI configuration header) |
| **/ |
| #define CONF_ADDR(bus, dev, fn, reg) ((void *)(conf_addr + ((bus << 16) | (dev << 11) | (fn << 8) | (reg << 0)))) |
| |
| |
| |
| static void us2i_init(struct pci_access *a) |
| { |
| } |
| |
| static void us2i_cleanup(struct pci_access *a UNUSED) |
| { |
| } |
| |
| static inline uint64_t pio_read_64(uint64_t *port) |
| { |
| uint64_t rv; |
| |
| rv = *port; |
| memory_barrier(); |
| |
| return rv; |
| } |
| |
| static int us2i_detect(struct pci_access *a) |
| { |
| /* |
| * Gain control over PCI configuration ports. |
| */ |
| if (pio_enable((void *)PCI_CONF_BASE, PCI_CONF_SIZE, &conf_addr)) { |
| return 0; |
| } |
| |
| int vendor_id = le16_to_cpu(pio_read_16(CONF_ADDR(0, 0, 0, PCI_VENDOR_ID))); |
| int device_id = le16_to_cpu(pio_read_16(CONF_ADDR(0, 0, 0, PCI_DEVICE_ID))); |
| |
| printf("PCI: vendor id = %x\n", vendor_id); |
| printf("PCI: device id = %x\n", device_id); |
| |
| return vendor_id == 0x108E && device_id == 0x8000; // should be Psycho from Sun Microsystems |
| } |
| |
| /** Compute new starting position of the operation if byte twisting is used. |
| * |
| * See chapter 10.2 of the UPA to PCI Interface User's Manual. |
| * Note: byte twisting is used only for devices beyond the UPA |
| * to PCI bridge, not for the device of the bridge itself. |
| * Configuration registers of the bridge must be read in a different way. |
| * |
| * @param pos The original starting position of the read/write operation. |
| * @param len The length of the read/write operation (<= 4). |
| * @return New starting position of the operation. |
| */ |
| static int byte_twist(int pos, int len) |
| { |
| int end = (pos + len) % 4; |
| if (end == 0) { |
| end = 4; |
| } |
| int begin = 4 - end; |
| pos = pos - pos % 4 + begin; |
| return pos; |
| } |
| |
| /* |
| static int byte_twist(pos) |
| { |
| return pos - pos % 4 + (3 - pos % 4); |
| }*/ |
| |
| static int us2i_read(struct pci_dev *d, int pos, byte * buf, int len) |
| { |
| /*void * addr = CONF_ADDR(d->bus, d->dev, d->func, pos); |
| |
| if (pos >= 256) |
| return 0; |
| |
| switch (len) { |
| case 1: |
| us2i_read_aligned(d->bus, d->dev, d->func, pos, buf, len); |
| break; |
| case 2: |
| us2i_read_aligned(d->bus, d->dev, d->func, pos, buf, len); |
| ((u16 *) buf)[0] = cpu_to_le16(*((u16 *) buf)); |
| break; |
| case 4: |
| us2i_read_aligned(d->bus, d->dev, d->func, pos, buf, len); |
| ((u32 *) buf)[0] = cpu_to_le32(*((u32 *) buf)); |
| break; |
| default: |
| return pci_generic_block_read(d, pos, buf, len); |
| } |
| return 1; */ |
| |
| |
| if (len <= 4) { |
| int twist = d->dev != 0 || d->func != 0; |
| if (twist) { |
| pos = byte_twist(pos, len); |
| } |
| int i; |
| for (i = 0; i < len; i++) { |
| void * addr = CONF_ADDR(d->bus, d->dev, d->func, pos + i); |
| if (byte_twist) { |
| buf[i] = pio_read_8(addr); |
| } |
| else { |
| buf[len-i-1] = pio_read_8(addr); |
| } |
| } |
| } else { |
| return pci_generic_block_read(d, pos, buf, len); |
| } |
| return 1; |
| |
| /*void * addr = CONF_ADDR(d->bus, d->dev, d->func, pos); |
| |
| if (pos >= 256) |
| return 0; |
| |
| switch (len) { |
| case 1: |
| buf[0] = pio_read_8(addr); |
| break; |
| case 2: |
| ((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr)); |
| break; |
| case 4: |
| ((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr)); |
| break; |
| default: |
| return pci_generic_block_read(d, pos, buf, len); |
| } |
| return 1; */ |
| |
| /* |
| switch (len) { |
| case 1: |
| buf[0] = pio_read_8(CONF_ADDR(d->bus, d->dev, d->func, pos)); |
| break; |
| case 2: |
| us2i_read(d, pos + 1, buf, 1); // unlike PCI, sparc uses big endian |
| us2i_read(d, pos, buf + 1, 1); |
| break; |
| case 4: |
| us2i_read(d, pos + 3, buf, 1); // endians in an ugly way ... FIX ME |
| us2i_read(d, pos + 2, buf + 1, 1); |
| us2i_read(d, pos + 1, buf + 2, 1); |
| us2i_read(d, pos, buf + 3, 1); |
| break; |
| default: |
| return pci_generic_block_read(d, pos, buf, len); |
| } |
| return 1; |
| */ |
| } |
| |
| static int us2i_write(struct pci_dev *d, int pos, byte * buf, int len) |
| { |
| void * addr = CONF_ADDR(d->bus, d->dev, d->func, pos); |
| |
| if (pos >= 256) |
| return 0; |
| |
| switch (len) { |
| case 1: |
| pio_write_8(CONF_ADDR(d->bus, d->dev, d->func, pos), buf[0]); |
| break; |
| case 2: |
| pio_write_16(addr, le16_to_cpu(((u16 *) buf)[0])); |
| break; |
| case 4: |
| pio_write_32(addr, le32_to_cpu(((u32 *) buf)[0])); |
| break; |
| default: |
| return pci_generic_block_write(d, pos, buf, len); |
| } |
| return 1; |
| } |
| |
| |
| struct pci_methods pm_us2i = { |
| "Ultra Sparc IIi", |
| NULL, /* config */ |
| us2i_detect, |
| us2i_init, |
| us2i_cleanup, |
| pci_generic_scan, |
| pci_generic_fill_info, |
| us2i_read, |
| us2i_write, |
| NULL, /* init_dev */ |
| NULL /* cleanup_dev */ |
| }; |