| 39,13 → 39,15 |
|---|
| #include <arch/types.h> |
| #include <arch/mm/page.h> |
| |
| /** Invalidate all entries in TLB. */ |
| /** Invalidate all entries in TLB. |
| * |
| * @note See ARM Architecture reference section 3.7.7 for details. |
| */ |
| void tlb_invalidate_all(void) |
| { |
| asm volatile ( |
| "eor r1, r1\n" |
| "MCR p15, 0, r1, c8, c7, 0\n" // see ARM Architecture reference relE 3.7.7 p.528 |
| |
| "mcr p15, 0, r1, c8, c7, 0\n" |
| ::: "r1" |
| ); |
| } |
| 53,7 → 55,7 |
|---|
| |
| /** Invalidate all entries in TLB that belong to specified address space. |
| * |
| * @param asid This parameter is ignored as the ARM architecture doesn't support it. |
| * @param asid Ignored as the ARM architecture doesn't support ASIDs. |
| */ |
| void tlb_invalidate_asid(asid_t asid) |
| { |
| 68,10 → 70,10 |
|---|
| static inline void invalidate_page(uintptr_t page) |
| { |
| asm volatile ( |
| "MCR p15, 0, %0, c8, c7, 1" |
| "mcr p15, 0, %0, c8, c7, 1" |
| |
| : /* no output */ |
| : "r"(page) /* input */ |
| : |
| : "r"(page) |
| ); |
| } |
| |
| 78,7 → 80,7 |
|---|
| |
| /** Invalidate TLB entries for specified page range belonging to specified address space. |
| * |
| * @param asid This parameter is ignored as the ARM architecture doesn't support it. |
| * @param asid Ignored as the ARM architecture doesn't support it. |
| * @param page Address of the first page whose entry is to be invalidated. |
| * @param cnt Number of entries to invalidate. |
| */ |