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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /branches/arm/kernel/arch/arm32/src/mm/page_fault.c @ 2414

  → /branches/arm/kernel/arch/arm32/src/mm/page_fault.c @ 2415

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 2414 → Rev 2415

/branches/arm/kernel/arch/arm32/src/mm/page_fault.c
43,7 → 43,6
/** Returns value stored in fault status register.
* FSR contain reason of page fault
*
* @return Value stored in CP15 fault status register (FSR).
*/
51,7 → 50,7
{
fault_status_union_t fsu;
// fault adress is stored in CP15 register 5
// fault status is stored in CP15 register 5
asm volatile (
"mrc p15, 0, %0, c5, c0, 0"
: "=r"(fsu.dummy)
77,7 → 76,7
}
/** Decides whether the instructions is load/store or not.
/** Decides whether the instruction is load/store or not.
*
* @param instr Instruction
*
130,11 → 129,10
/** Decides whether read or write into memory is requested.
*
* @param instr_addr Address of instruction which tries to access memory
* @param badvaddr Virtual address the instruction tries to access
* @param instr_addr Address of instruction which tries to access memory.
* @param badvaddr Virtual address the instruction tries to access.
*
* @return Type of access into memmory
* Note: Returns #PF_ACCESS_EXEC if no memory access is requested
* @return Type of access into memmory, #PF_ACCESS_EXEC if no memory access is requested.
*/
static pf_access_t get_memory_access_type(uint32_t instr_addr, uintptr_t badvaddr)
{
145,7 → 143,7
// undefined instructions
if (instr.condition == 0xf) {
panic("page_fault - instruction not access memmory (instr_code: %x, badvaddr:%x)",
panic("page_fault - instruction doesn't access memory (instr_code: %x, badvaddr:%x)",
instr, badvaddr);
return PF_ACCESS_EXEC;
}
161,34 → 159,10
// swap, swpb instruction
if (is_swap_instruction(instr)) {
/* Swap instructions make read and write in one step.
* Type of access that caused exception have to page tables
* and access rights.
*/
pte_level1_t* pte = (pte_level1_t*)
pt_mapping_operations.mapping_find(AS, badvaddr);
if ( pte == NULL ) {
return PF_ACCESS_READ;
}
/* check if read possible
* Note: Don't check PTE_READABLE because it returns 1 everytimes */
if ( !PTE_PRESENT(pte) ) {
return PF_ACCESS_READ;
}
if ( !PTE_WRITABLE(pte) ) {
return PF_ACCESS_WRITE;
} else {
// badvaddr is present readable and writeable but error occured ... why?
panic("page_fault - swap instruction, but address readable and writeable"
"(instr_code:%X, badvaddr:%X)", instr, badvaddr);
}
return PF_ACCESS_WRITE;
}
panic("page_fault - instruction not access memory (instr_code: %x, badvaddr:%x)",
panic("page_fault - instruction doesn't access memory (instr_code: %x, badvaddr:%x)",
instr, badvaddr);
return PF_ACCESS_EXEC;
196,8 → 170,8
/** Handles "data abort" exception (load or store at invalid address).
*
* @param exc_no exception number
* @param istate CPU state when exception occured
* @param exc_no Exception number.
* @param istate CPU state when exception occured.
*/
void data_abort(int exc_no, istate_t *istate)
{
220,8 → 194,8
/** Handles "prefetch abort" exception (instruction couldn't be executed).
*
* @param exc_no exception number
* @param istate CPU state when exception occured
* @param exc_no Exception number.
* @param istate CPU state when exception occured.
*/
void prefetch_abort(int exc_no, istate_t *istate)
{