| 59,6 → 59,7 |
|---|
| #define PTL0_ENTRIES_ARCH (2<<12) // 4096 |
| #define PTL1_ENTRIES_ARCH 0 |
| #define PTL2_ENTRIES_ARCH 0 |
| |
| /* coarse page tables used (256*4 = 1KB per page) */ |
| #define PTL3_ENTRIES_ARCH (2<<8) // 256 |
| |
| 98,8 → 99,10 |
|---|
| |
| /* pte should point into ptl3 */ |
| #define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) |
| |
| /* pte should point into ptl3 */ |
| #define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW ) |
| |
| #define PTE_EXECUTABLE_ARCH(pte) 1 |
| |
| |
| 120,7 → 123,7 |
|---|
| * with 1KB per the coarse table) |
| */ |
| unsigned coarse_table_addr : 22; |
| } __attribute__ ((packed)) pte_level0_t; |
| } ATTRIBUTE_PACKED pte_level0_t; |
| |
| |
| /** Level 1 page table entry (small (4KB) pages used). */ |
| 138,7 → 141,7 |
|---|
| unsigned access_permission_2 : 2; |
| unsigned access_permission_3 : 2; |
| unsigned frame_base_addr : 20; |
| } __attribute__ ((packed)) pte_level1_t; |
| } ATTRIBUTE_PACKED pte_level1_t; |
| |
| |
| /* Level 1 page tables access permissions */ |