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Ignore whitespace Rev 2255 → Rev 2256

/branches/arm/kernel/arch/arm32/include/mm/page.h
69,8 → 69,7
#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)
#define PTL1_INDEX_ARCH(vaddr) 0
#define PTL2_INDEX_ARCH(vaddr) 0
/* TODO: ?? 0xfff or 0x0ff */
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0xfff)
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)
 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
100,7 → 99,7
/* pte should point into ptl3 */
#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
/* pte should point into ptl3 */
#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw )
#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW )
 
#define PTE_EXECUTABLE_ARCH(pte) 1
 
130,14 → 129,14
{
pte_level0_t *p = &pt[i];
 
return (
( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT |
return
( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT ) |
( 1 << PAGE_USER_SHIFT ) |
( 1 << PAGE_READ_SHIFT ) |
( 1 << PAGE_WRITE_SHIFT ) |
( 1 << PAGE_EXEC_SHIFT ) |
( 1 << PAGE_CACHEABLE_SHIFT )
);
;
}
 
/**
150,15 → 149,15
{
pte_level1_t *p = &pt[i];
 
return (
( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT |
( (p->access_permission_0 == pte_ap_user_ro_kernel_rw) << PAGE_READ_SHIFT ) |
( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_READ_SHIFT ) |
( (p->access_permission_0 == pte_ap_user_rw_kernel_rw) << PAGE_WRITE_SHIFT ) |
( (p->access_permission_0 != pte_ap_user_no_kernel_rw) << PAGE_USER_SHIFT ) |
return
( (p->descriptor_type == PTE_DESCRIPTOR_NOT_PRESENT) << PAGE_PRESENT_SHIFT) |
( (p->access_permission_0 == PTE_AP_USER_RO_KERNEL_RW) << PAGE_READ_SHIFT ) |
( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_READ_SHIFT ) |
( (p->access_permission_0 == PTE_AP_USER_RW_KERNEL_RW) << PAGE_WRITE_SHIFT ) |
( (p->access_permission_0 != PTE_AP_USER_NO_KERNEL_RW) << PAGE_USER_SHIFT ) |
( 1 << PAGE_EXEC_SHIFT ) |
( p->bufferable << PAGE_CACHEABLE )
);
;
}
 
/**
173,13 → 172,13
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
{
pte_level0_t *p = &pt[i];
 
if (flags & PAGE_NOT_PRESENT) {
p->descriptor_type = pte_descriptor_not_preset;
p->should_be_zero = 1;
p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
// p->should_be_zero = 1;
} else {
p->descriptor_type = pte_descriptor_coarse_table;
p->should_be_zero = 0;
p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
// p->should_be_zero = 0;
}
}
 
199,11 → 198,11
pte_level1_t *p = &pt[i];
if (flags & PAGE_NOT_PRESENT) {
p->descriptor_type = pte_descriptor_not_preset;
p->access_permission_3 = 1;
p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT;
// p->access_permission_3 = 1;
} else {
p->descriptor_type = pte_descriptor_small_page;
p->access_permission_3 = p->access_permission_0;
p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
// p->access_permission_3 = p->access_permission_0;
}
p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
210,18 → 209,18
 
/* default access permission */
p->access_permission_0 = p->access_permission_1 =
p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw;
p->access_permission_2 = p->access_permission_3 = PTE_AP_USER_NO_KERNEL_RW;
 
if (flags & PAGE_USER) {
if (flags & PAGE_READ) {
p->access_permission_0 = p->access_permission_1 =
p->access_permission_2 = p->access_permission_3 =
pte_ap_user_ro_kernel_rw;
PTE_AP_USER_RO_KERNEL_RW;
}
if (flags & PAGE_WRITE) {
p->access_permission_0 = p->access_permission_1 =
p->access_permission_2 = p->access_permission_3 =
pte_ap_user_rw_kernel_rw;
PTE_AP_USER_RW_KERNEL_RW;
}
}
}