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Ignore whitespace Rev 2237 → Rev 2238

/branches/arm/kernel/arch/arm32/include/mm/page.h
1,5 → 1,5
/*
* Copyright (c) 2003-2007 Jakub Jermar
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
54,63 → 54,65
#endif
 
#ifdef KERNEL
// Using small pages <==> 4kb
#define PTL0_ENTRIES_ARCH (2<<12) // 4096
#define PTL1_ENTRIES_ARCH 0
#define PTL2_ENTRIES_ARCH 0
#define PTL3_ENTRIES_ARCH (2<<8) // 256
 
#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)
#define PTL1_INDEX_ARCH(vaddr) 0
#define PTL2_INDEX_ARCH(vaddr) 0
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)
// "small" pages (4KB) used
#define PTL0_ENTRIES_ARCH (2<<12) // 4096
#define PTL1_ENTRIES_ARCH 0
#define PTL2_ENTRIES_ARCH 0
#define PTL3_ENTRIES_ARCH (2<<8) // 256
 
#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 20) & 0xfff)
#define PTL1_INDEX_ARCH(vaddr) 0
#define PTL2_INDEX_ARCH(vaddr) 0
#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x0ff)
 
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ( (uintptr_t)(((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) ((pte_t *)( (((pte_level0_t*)(ptl0))[(i)]).coarse_table_addr << 10 ))
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) ((uintptr_t)( (((pte_level1_t*)(ptl3))[(i)]).frame_base_addr << 12 ))
 
#define SET_PTL0_ADDRESS_ARCH(ptl0) ( set_ptl0_addr((pte_level0_t *)(ptl0)) )
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
#define SET_PTL0_ADDRESS_ARCH(ptl0) (set_ptl0_addr((pte_level0_t *)(ptl0)))
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) (((pte_level0_t *)(ptl0))[(i)].coarse_table_addr = (a)>>10)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) (((pte_level1_t *)(ptl3))[(i)].frame_base_addr = (a)>>12)
 
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
#define GET_PTL1_FLAGS_ARCH(ptl0, i) get_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) get_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i))
 
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) set_pt_level0_flags((pte_level0_t *)(ptl0), (index_t)(i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) set_pt_level1_flags((pte_level1_t *)(ptl3), (index_t)(i), (x))
 
#define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte) ( ((pte_level0_t *)(pte))->descriptor_type )
#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH) // pte should point into ptl3
#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw ) // pte should point into ptl3
#define PTE_EXECUTABLE_ARCH(pte) 1
// pte should point into ptl3
#define PTE_GET_FRAME_ARCH(pte) ( ((pte_level1_t *)(pte))->frame_base_addr << FRAME_WIDTH)
// pte should point into ptl3
#define PTE_WRITABLE_ARCH(pte) ( ((pte_level1_t *)(pte))->access_permission_0 == pte_ap_user_rw_kernel_rw )
#define PTE_EXECUTABLE_ARCH(pte) 1
 
#ifndef __ASM__
 
/** Set adress of paging level 0 table
* \param pt pointer to page table to set
/** Sets the address of level 0 page table.
* \param pt pointer to the page table to set
*/
static inline void set_ptl0_addr( pte_level0_t* pt){
static inline void set_ptl0_addr( pte_level0_t* pt)
{
asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
:
: "r"(pt)
:
: "r"(pt)
);
}
 
//TODO Comment: Page table structure as in other architectures
static inline int get_pt_level0_flags(pte_level0_t *pt, index_t i)
{
pte_level0_t *p = &pt[i];
pte_level0_t *p = &pt[i];
 
return (
( p->descriptor_type != pte_descriptor_not_preset ) << PAGE_PRESENT_SHIFT |
118,8 → 120,8
( 1 << PAGE_EXEC_SHIFT ) |
( 1 << PAGE_CACHEABLE )
);
}
 
}
static inline int get_pt_level1_flags(pte_level1_t *pt, index_t i)
{
pte_level1_t *p = &pt[i];
138,23 → 140,20
 
}
 
 
static inline void set_pt_level0_flags(pte_level0_t *pt, index_t i, int flags)
{
pte_level0_t *p = &pt[i];
if ( flags & PAGE_NOT_PRESENT ) {
p->descriptor_type = pte_descriptor_not_preset;
p->should_be_zero = 1;
} else
{
p->descriptor_type = pte_descriptor_coarse_table;
p->should_be_zero = 0;
p->descriptor_type = pte_descriptor_not_preset;
p->should_be_zero = 1;
} else {
p->descriptor_type = pte_descriptor_coarse_table;
p->should_be_zero = 0;
}
return;
}
 
/* We use same acess rights for whole page, so if page is set as not preset then
/* TODO: rewrite comment: We use same acess rights for whole page, so if page is set as not preset then
* in acess_rigts_3 set value 1
*/
static inline void set_pt_level1_flags(pte_level1_t *pt, index_t i, int flags)
162,24 → 161,31
pte_level1_t *p = &pt[i];
if ( flags & PAGE_NOT_PRESENT ) {
p->descriptor_type = pte_descriptor_not_preset;
p->access_permission_3 = 1;
} else
{
p->descriptor_type = pte_descriptor_coarse_table;
p->access_permission_3 = p->access_permission_0;
}
p->descriptor_type = pte_descriptor_not_preset;
p->access_permission_3 = 1;
} else {
p->descriptor_type = pte_descriptor_coarse_table;
p->access_permission_3 = p->access_permission_0;
}
p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
// default kernel rw, user none
p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw;
if ( flags & PAGE_USER ) {
if ( flags & PAGE_READ )
p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_ro_kernel_rw;
if ( flags & PAGE_WRITE )
p->access_permission_0 = p->access_permission_1 = p->access_permission_2 = p->access_permission_3 = pte_ap_user_rw_kernel_rw;
}
return; return;
p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0;
 
// default kernel rw, user none
p->access_permission_0 = p->access_permission_1 =
p->access_permission_2 = p->access_permission_3 = pte_ap_user_no_kernel_rw;
 
if ( flags & PAGE_USER ) {
if ( flags & PAGE_READ ) {
p->access_permission_0 = p->access_permission_1 =
p->access_permission_2 = p->access_permission_3 =
pte_ap_user_ro_kernel_rw;
}
if ( flags & PAGE_WRITE ) {
p->access_permission_0 = p->access_permission_1 =
p->access_permission_2 = p->access_permission_3 =
pte_ap_user_rw_kernel_rw;
}
}
}
 
extern void page_arch_init(void);