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Ignore whitespace Rev 2322 → Rev 2323

/branches/arm/boot/arch/arm32/loader/mm.h
26,6 → 26,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
 
/** @addtogroup arm32boot
* @{
*/
33,49 → 34,58
*/
 
 
#ifndef __MM_H__
#define __MM_H__
#ifndef BOOT_arm32__MM_H
#define BOOT_arm32__MM_H
 
 
#ifndef __ASM__
#include "types.h"
#endif
 
 
#define FRAME_WIDTH 12 /* 4KB frames */
#define FRAME_SIZE (1 << FRAME_WIDTH)
/** Frame width. */
#define FRAME_WIDTH 12 /* 4KB frames */
 
#define PAGE_WIDTH FRAME_WIDTH
#define PAGE_SIZE FRAME_SIZE
/** Frame size. */
#define FRAME_SIZE (1 << FRAME_WIDTH)
 
/** Page size in 2-level paging which is switched on later in the kernel initialization. */
#define PAGE_SIZE FRAME_SIZE
 
 
#ifndef __ASM__
# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
#else
# define KA2PA(x) ((x) - 0x80000000)
# define PA2KA(x) ((x) + 0x80000000)
# define KA2PA(x) ((x) - 0x80000000)
# define PA2KA(x) ((x) + 0x80000000)
#endif
 
/** Number of entries in PTL0 */
#define PTL0_ENTRIES_ARCH (1<<12) /* 4096 */
 
/** Frames per 1MB section */
#define FRAMES_PER_SECTION ( ( 1 << 20 ) / FRAME_SIZE )
/** Number of entries in PTL0. */
#define PTL0_ENTRIES (1<<12) /* 4096 */
 
/** Converts adress to frame number */
#define ADDR2PFN( addr ) ( ((uintptr_t)(addr))>>FRAME_WIDTH )
/** Size of an entry in PTL0. */
#define PTL0_ENTRY_SIZE 4
 
/** Descriptor type that signs "section" page table entry
* (one-level paging with 1MB sized pages) */
#define PTE_DESCRIPTOR_SECTION 2
/** Number of frames per 1MB section. */
#define FRAMES_PER_SECTION ( ( 1 << 20 ) / FRAME_SIZE )
 
/** Access rights to page table: user-no access, kernel-read/write */
#define PTE_AP_USER_NO_KERNEL_RW 1
/** Returns number of frame the address belongs to. */
#define ADDR2PFN( addr ) ( ((uintptr_t)(addr)) >> FRAME_WIDTH )
 
/** Describes "section" page table entry (one-level paging with 1MB sized pages). */
#define PTE_DESCRIPTOR_SECTION 0x2
 
/** Page table access rights: user - no access, kernel - read/write. */
#define PTE_AP_USER_NO_KERNEL_RW 0x1
 
 
#ifndef __ASM__
 
 
/** Page table level 0 entry - "section" format (one-level paging, 1MB sized
* pages). Used only for booting the kernel. */
/** Page table level 0 entry - "section" format is used (one-level paging, 1MB sized
* pages). Used only while booting the kernel. */
typedef struct {
unsigned descriptor_type : 2;
unsigned bufferable : 1;
89,14 → 99,12
} __attribute__ ((packed)) pte_level0_section_t;
 
 
/** Page table that holds 1:1 mapping for booting the kernel. */
extern pte_level0_section_t page_table[PTL0_ENTRIES_ARCH];
/** Page table that holds 1:1 virtual to physical mapping used while booting the kernel. */
extern pte_level0_section_t page_table[PTL0_ENTRIES];
 
extern void mmu_start(void);
 
/** Starts the MMU - initializes page table and enables paging. */
void mmu_start(void);
 
 
/** Enables paging. */
static inline void enable_paging()
{
107,17 → 115,14
// behave as a client of domains
"ldr r0, =0x55555555 \n"
"mcr p15, 0, r0, c3, c0, 0 \n"
 
// current settings
"mrc p15, 0, r0, c1, c0, 0 \n"
/* TODO: talk to Alf why needed
// mask to disable aligment checks; system & rom bit set to 0 (has no
// special effect)
"ldr r1, =0xfffffe8f \n"
"and r0, r0, r1 \n"
*/
 
// mask to enable paging
"ldr r1, =0x00000001 \n"
"orr r0, r0, r1 \n"
 
// store settings
"mcr p15, 0, r0, c1, c0, 0 \n"
:
127,17 → 132,20
}
 
 
/** Sets the address of level 0 page table.
* \param pt pointer to the page table to set
/** Sets the address of level 0 page table to CP15 register 2.
*
* @param pt Address of a page table to set.
*/
static inline void set_ptl0_address(pte_level0_section_t* pt)
{
asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
asm volatile (
"mcr p15, 0, %0, c2, c0, 0 \n"
:
: "r"(pt)
);
}
 
 
#endif
#endif