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Ignore whitespace Rev 2253 → Rev 2254

/branches/arm/boot/arch/arm32/loader/mm.h
73,10 → 73,11
 
#ifndef __ASM__
 
 
/** Page table level 0 entry - "section" format (one-level paging, 1MB sized
* pages). Used only for booting the kernel. */
typedef struct {
unsigned descriptor_type : 2; // PTE_DESCRIPTOR_SECTION (0b10)
unsigned descriptor_type : 2;
unsigned bufferable : 1;
unsigned cacheable : 1;
unsigned impl_specific : 1;
88,23 → 89,55
} __attribute__ ((packed)) pte_level0_section;
 
 
/** Page table that holds 1:1 mapping for booting the kernel. */
extern pte_level0_section page_table[PTL0_ENTRIES_ARCH];
 
 
/** Starts the MMU - initializes page table and enables paging. */
void mmu_start(void);
 
 
/** Enables paging. */
static inline void enable_paging()
{
/* c3 - each two bits controls access to the one of domains (16)
* 0b01 - behave as a client (user) of a domain
*/
asm volatile (
// behave as a client of domains
"ldr r0, =0x55555555 \n"
"mcr p15, 0, r0, c3, c0, 0 \n"
// current settings
"mrc p15, 0, r0, c1, c0, 0 \n"
/* TODO: talk to Alf why needed
// mask to disable aligment checks; system & rom bit set to 0 (has no
// special effect)
"ldr r1, =0xfffffe8f \n"
"and r0, r0, r1 \n"
*/
// mask to enable paging
"ldr r1, =0x00000001 \n"
"orr r0, r0, r1 \n"
// store settings
"mcr p15, 0, r0, c1, c0, 0 \n"
:
:
: "r0", "r1"
);
}
 
 
/** Sets the address of level 0 page table.
* \param pt pointer to the page table to set
*/
static inline void set_ptl0_address( pte_level0_section* pt) {
static inline void set_ptl0_address(pte_level0_section* pt)
{
asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
:
: "r"(pt)
:
: "r"(pt)
);
}
 
/** Page table that holds 1:1 mapping for booting the kernel. */
extern pte_level0_section page_table[PTL0_ENTRIES_ARCH];
 
/** Sets memory mapping for kernel */
void mm_kernel_mapping(void);
 
#endif
#endif