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Ignore whitespace Rev 2235 → Rev 2236

/branches/arm/boot/arch/arm32/loader/mm.h
1,5 → 1,5
/*
* Copyright (c) 2003-2004 Jakub Jermar
* Copyright (c) 2007 Pavel Jancik, Michal Kebrt
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
26,7 → 26,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup arm32mm
/** @addtogroup arm32boot
* @{
*/
/** @file
36,7 → 36,9
#ifndef __MM_H__
#define __MM_H__
 
#ifndef __ASM__
#include "types.h"
#endif
 
 
#define FRAME_WIDTH 12 /* 4KB frames */
53,27 → 55,28
# define PA2KA(x) ((x) + 0x80000000)
#endif
 
#define PTL0_ENTRIES_ARCH (2<<12) /* 4096 */
#define SET_PTL0_ADDRESS_ARCH(ptl0) ( set_ptl0_addr((pte_level0_section *)(ptl0)) )
/** Number of entries in PTL0 */
#define PTL0_ENTRIES_ARCH (2<<12) /* 4096 */
 
/** Frames per 1MB section */
#define FRAMES_PER_SECTION ( ( 1 << 20 ) / FRAME_SIZE )
 
/** Converts adress to frame */
/** Converts adress to frame number */
#define ADDR2PFN( addr ) ( ((uintptr_t)(addr))>>FRAME_WIDTH )
 
/** Value of descriptor_type in page table entry that signals
* that this entry describe section
*/
/** Descriptor type that signs "section" page table entry
* (one-level paging with 1MB sized pages) */
#define PTE_DESCRIPTOR_SECTION 2
 
/** Rights: user-no acess, kernel-read/write */
/** Access rights to page table: user-no access, kernel-read/write */
#define PTE_AP_USER_NO_KERNEL_RW 1
 
#ifndef __ASM__
 
/** Page table level 0 entry - section format */
/** Page table level 0 entry - "section" format (one-level paging, 1MB sized
* pages). Used only for booting the kernel. */
typedef struct {
unsigned descriptor_type : 2; // should be 2
unsigned descriptor_type : 2; // PTE_DESCRIPTOR_SECTION
unsigned bufferable : 1;
unsigned cacheable : 1;
unsigned machine_depend : 1;
85,10 → 88,10
} __attribute__ ((packed)) pte_level0_section;
 
 
/** Set adress of paging level 0 table
* \param pt pointer to page table to set
/** Sets the address of level 0 page table.
* \param pt pointer to the page table to set
*/
static inline void set_ptl0_addr( pte_level0_section* pt) {
static inline void set_ptl0_address( pte_level0_section* pt) {
asm volatile ( "mcr p15, 0, %0, c2, c0, 0 \n"
:
: "r"(pt)
96,11 → 99,13
}
 
/** Page table that holds 1:1 mapping for kernel starting */
/** Page table that holds 1:1 mapping for booting the kernel. */
extern pte_level0_section page_table[PTL0_ENTRIES_ARCH];
 
/** Sets memory mapping for kernel */
void mm_kernel_mapping(void);
 
#endif
#endif