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Ignore whitespace Rev 2322 → Rev 2323

/branches/arm/boot/arch/arm32/loader/mm.c
26,6 → 26,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
 
/** @addtogroup arm32boot
* @{
*/
32,17 → 33,19
/** @file
*/
 
 
#include "mm.h"
 
 
/** Initializes section page table entry.
/** Initializes "section" page table entry.
*
* Will be readable/writable by kernel with no access from user mode.
* Will belong to domain 0. No cache or buffering is enabled.
*
* \param pte page table entry to set
* \param frame first frame in the section (frame number)
* \note If frame is not 1MB aligned, first lower 1MB aligned frame will be used.
* @param pte Section entry to initialize.
* @param frame First frame in the section (frame number).
*
* @note If #frame is not 1MB aligned, first lower 1MB aligned frame will be used.
*/
static void init_pte_level0_section(pte_level0_section_t* pte, unsigned frame)
{
58,23 → 61,27
}
 
 
/** Initializes page table used while booting the kernel. */
static void init_page_table(void)
{
int i;
const unsigned int first_kernel_section = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION;
 
const unsigned int first_kernel_section = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION;
// create 1:1 mapping virtual-physical (in lower 2GB)
for(i = 0; i < first_kernel_section; i++) {
// create 1:1 virtual-physical mapping (in lower 2GB)
for (i = 0; i < first_kernel_section; i++) {
init_pte_level0_section(&page_table[i], i * FRAMES_PER_SECTION);
}
 
// create kernel mapping (in upper 2GB), physical addresses starting from 0
for(i = first_kernel_section; i < PTL0_ENTRIES_ARCH; i++) {
// create 1:1 virtual-physical mapping in kernel space (upper 2GB),
// physical addresses start from 0
for (i = first_kernel_section; i < PTL0_ENTRIES; i++) {
init_pte_level0_section(&page_table[i], (i - first_kernel_section) * FRAMES_PER_SECTION);
}
}
 
 
/** Starts the MMU - initializes page table and enables paging.
*/
void mmu_start() {
init_page_table();
set_ptl0_address(page_table);
81,6 → 88,7
enable_paging();
}
 
 
/** @}
*/