| 1,5 → 1,5 |
|---|
| /* |
| * Copyright (c) 2003-2004 Jakub Jermar |
| * Copyright (c) 2007 Pavel Jancik, Michal Kebrt |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| 26,20 → 26,24 |
|---|
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| /** @addtogroup arm32mm |
| /** @addtogroup arm32boot |
| * @{ |
| */ |
| /** @file |
| */ |
| |
| #include "mm.h" |
| |
| /** Set page table entry to point no frame, be read/write by kernel, |
| * no access by user, become to domain 0, no cache or buffer |
| * \param pte page table entry to set |
| * \param frame frame number of first frame 1MB section |
| * Note: If frame not aligned it's used first lower 1MB aligned frame |
| /** Initializes section page table entry. |
| * |
| * Will be readable/writable by kernel with no access from user mode. |
| * Will belong to domain 0. No cache or buffering is enabled. |
| * |
| * \param pte page table entry to set |
| * \param frame first frame in the section (frame number) |
| * \note If frame is not 1MB aligned, first lower 1MB aligned frame will be used. |
| */ |
| static void init_pte_level0_section_entry( pte_level0_section* pte, unsigned frame){ |
| static void init_pte_level0_section(pte_level0_section* pte, unsigned frame){ |
| pte->descriptor_type = PTE_DESCRIPTOR_SECTION; |
| pte->bufferable = 0; // disable |
| pte->cacheable = 0; |
| 54,32 → 58,33 |
|---|
| |
| void mm_kernel_mapping(void) { |
| int i; |
| // Create 1:1 mapping |
| for( i=0; i < PTL0_ENTRIES_ARCH; i++) { |
| init_pte_level0_section_entry(&page_table[i], i * FRAMES_PER_SECTION); |
| |
| const unsigned int first_kernel_section = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION; |
| // create 1:1 mapping (in lower 2GB) |
| for(i = 0; i < first_kernel_section; i++) { |
| init_pte_level0_section(&page_table[i], i * FRAMES_PER_SECTION); |
| } |
| |
| // Create kernel mapping |
| const unsigned int offset = ADDR2PFN(PA2KA(0)) / FRAMES_PER_SECTION; |
| for( i = offset; i < PTL0_ENTRIES_ARCH; i++) { |
| init_pte_level0_section_entry(&page_table[i], (i - offset) * FRAMES_PER_SECTION); |
| // create kernel mapping (in upper 2GB), physical addresses starting from 0 |
| for(i = first_kernel_section; i < PTL0_ENTRIES_ARCH; i++) { |
| init_pte_level0_section(&page_table[i], (i - first_kernel_section) * FRAMES_PER_SECTION); |
| } |
| |
| SET_PTL0_ADDRESS_ARCH( page_table); |
| set_ptl0_address(page_table); |
| |
| // Enable paging |
| // enable paging |
| asm volatile ( |
| "ldr r0, =0x55555555 \n" |
| "mcr p15, 0, r0, c3, c0, 0 \n" // Set domain acces rights to client <==> take rights from page tables |
| "mrc p15, 0, r0, c1, c0, 0 \n" // Get current setting of system ... register 1 isn't only for memmory management |
| "ldr r1, =0xFFFFFE8D \n" // Mask to disable aligment checks; system & rom bit disable |
| "and r0, r0, r1 \n" |
| "ldr r1, =0x00000001 \n" // Mask to enable paging |
| "orr r0, r0, r1 \n" |
| "mcr p15, 0, r0, c1, c0, 0 \n" // Store setting |
| : |
| : |
| : "r0", "r1" |
| "ldr r0, =0x55555555 \n" |
| "mcr p15, 0, r0, c3, c0, 0 \n" // TODO: comment: set domain access rights to client <==> take rights from page tables |
| "mrc p15, 0, r0, c1, c0, 0 \n" // get current settings of system |
| "ldr r1, =0xFFFFFE8D \n" // mask to disable aligment checks; system & rom bit disabled |
| "and r0, r0, r1 \n" |
| "ldr r1, =0x00000001 \n" // mask to enable paging |
| "orr r0, r0, r1 \n" |
| "mcr p15, 0, r0, c1, c0, 0 \n" // store settings |
| : |
| : |
| : "r0", "r1" |
| ); |
| }; |
| |