| 275,6 → 275,7 |
|---|
| */ |
| void qemu_icp_console_init(devno_t devno) |
| { |
| qemu_icp_irqc_mask(QEMU_ICP_KBD_IRQ); |
| chardev_initialize("qemu_icp_console", &console, &qemu_icp_ops); |
| stdin = &console; |
| stdout = &console; |
| 300,9 → 301,9 |
|---|
| */ |
| static void qemu_icp_timer_start(uint32_t frequency) |
| { |
| qemu_icp_irqc_mask(QEMU_ICP_TIMER_IRQ); |
| *((uint32_t*) qemu_icp_hw_map.rtc1_load) = frequency; |
| *((uint32_t*) qemu_icp_hw_map.rtc1_bgload) = frequency; |
| qemu_icp_irqc_mask(QEMU_ICP_TIMER_IRQ); |
| *((uint32_t*) qemu_icp_hw_map.rtc1_ctl) = QEMU_ICP_RTC_CTL_VALUE; |
| qemu_icp_irqc_unmask(QEMU_ICP_TIMER_IRQ); |
| } |
| 309,6 → 310,7 |
|---|
| |
| static irq_ownership_t qemu_icp_timer_claim(void) |
| { |
| *((uint32_t*) qemu_icp_hw_map.rtc1_intrclr) = 1; |
| return IRQ_ACCEPT; |
| } |
| |
| 327,8 → 329,6 |
|---|
| clock(); |
| spinlock_lock(&irq->lock); |
| |
| /* acknowledge tick */ |
| *((uint32_t*) qemu_icp_hw_map.rtc1_intrclr) = 0; |
| } |
| |
| /** Initializes and registers timer interrupt handler. */ |