Subversion Repositories HelenOS

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Ignore whitespace Rev 4611 → Rev 4612

/branches/arm/kernel/arch/arm32/include/drivers/qemu.h
46,7 → 46,7
#define QEMU_ICP_IRQC_MAX_IRQ 8
 
/** Timer frequency */
#define QEMU_ICP_TIMER_FREQ 100
#define QEMU_ICP_TIMER_FREQ 1000
 
/** Struct containing mappings of qemu_icp HW devices into kernel part
* of virtual address space.
55,8 → 55,11
uintptr_t videoram;
uintptr_t kbd;
uintptr_t rtc;
uintptr_t rtc_freq;
uintptr_t rtc_ack;
uintptr_t rtc1_load;
uintptr_t rtc1_read;
uintptr_t rtc1_ctl;
uintptr_t rtc1_intrclr;
uintptr_t rtc1_bgload;
uintptr_t irqc;
uintptr_t irqc_mask;
uintptr_t irqc_unmask;
/branches/arm/kernel/arch/arm32/src/drivers/qemu.c
52,8 → 52,12
#define QEMU_ICP_KBD 0x18000000
#define QEMU_ICP_HALT_OFFSET 0x10
#define QEMU_ICP_RTC 0x13000000
#define QEMU_ICP_RTC_FREQ_OFFSET 0x100
#define QEMU_ICP_RTC_ACK_OFFSET 0x110
#define QEMU_ICP_RTC1_LOAD_OFFSET 0x100
#define QEMU_ICP_RTC1_READ_OFFSET 0x104
#define QEMU_ICP_RTC1_CTL_OFFSET 0x108
#define QEMU_ICP_RTC1_INTRCLR_OFFSET 0x10C
#define QEMU_ICP_RTC1_BGLOAD_OFFSET 0x118
#define QEMU_ICP_RTC_CTL_VALUE 0x00E2
#define QEMU_ICP_IRQC 0x14000000
#define QEMU_ICP_IRQC_MASK_OFFSET 0xC
#define QEMU_ICP_IRQC_UNMASK_OFFSET 0x8
65,8 → 69,8
#define ICP_CMCR 0x10000000
 
/* IRQs */
#define QEMU_ICP_KBD_IRQ 0x03
#define QEMU_ICP_TIMER_IRQ 0x05
#define QEMU_ICP_KBD_IRQ 3
#define QEMU_ICP_TIMER_IRQ 6
 
static qemu_icp_hw_map_t qemu_icp_hw_map;
static chardev_t console;
118,7 → 122,7
*/
static inline void qemu_icp_irqc_mask(uint32_t irq)
{
*((uint32_t *) qemu_icp_hw_map.irqc_mask) = irq;
*((uint32_t *) qemu_icp_hw_map.irqc_mask) = (1 << irq);
}
 
 
128,7 → 132,7
*/
static inline void qemu_icp_irqc_unmask(uint32_t irq)
{
*((uint32_t *) qemu_icp_hw_map.irqc_unmask) |= irq;
*((uint32_t *) qemu_icp_hw_map.irqc_unmask) |= (1 << irq);
}
 
/** Initializes the icp frame buffer */
143,10 → 147,13
qemu_icp_hw_map.videoram = hw_map(QEMU_ICP_VIDEORAM, PAGE_SIZE);
qemu_icp_hw_map.kbd = hw_map(QEMU_ICP_KBD, PAGE_SIZE);
qemu_icp_hw_map.rtc = hw_map(QEMU_ICP_RTC, PAGE_SIZE);
qemu_icp_hw_map.rtc1_load = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_LOAD_OFFSET;
qemu_icp_hw_map.rtc1_read = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_READ_OFFSET;
qemu_icp_hw_map.rtc1_ctl = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_CTL_OFFSET;
qemu_icp_hw_map.rtc1_intrclr = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_INTRCLR_OFFSET;
qemu_icp_hw_map.rtc1_bgload = qemu_icp_hw_map.rtc + QEMU_ICP_RTC1_BGLOAD_OFFSET;
 
qemu_icp_hw_map.irqc = hw_map(QEMU_ICP_IRQC, PAGE_SIZE);
 
qemu_icp_hw_map.rtc_freq = qemu_icp_hw_map.rtc + QEMU_ICP_RTC_FREQ_OFFSET;
qemu_icp_hw_map.rtc_ack = qemu_icp_hw_map.rtc + QEMU_ICP_RTC_ACK_OFFSET;
qemu_icp_hw_map.irqc_mask = qemu_icp_hw_map.irqc + QEMU_ICP_IRQC_MASK_OFFSET;
qemu_icp_hw_map.irqc_unmask = qemu_icp_hw_map.irqc +
QEMU_ICP_IRQC_UNMASK_OFFSET;
293,7 → 300,11
*/
static void qemu_icp_timer_start(uint32_t frequency)
{
*((uint32_t*) qemu_icp_hw_map.rtc_freq) = frequency;
*((uint32_t*) qemu_icp_hw_map.rtc1_load) = frequency;
*((uint32_t*) qemu_icp_hw_map.rtc1_bgload) = frequency;
qemu_icp_irqc_mask(QEMU_ICP_TIMER_IRQ);
*((uint32_t*) qemu_icp_hw_map.rtc1_ctl) = QEMU_ICP_RTC_CTL_VALUE;
qemu_icp_irqc_unmask(QEMU_ICP_TIMER_IRQ);
}
 
static irq_ownership_t qemu_icp_timer_claim(void)
317,7 → 328,7
spinlock_lock(&irq->lock);
 
/* acknowledge tick */
*((uint32_t*) qemu_icp_hw_map.rtc_ack) = 0;
*((uint32_t*) qemu_icp_hw_map.rtc1_intrclr) = 0;
}
 
/** Initializes and registers timer interrupt handler. */