| /branches/arm/kernel/arch/arm32/include/exception.h |
|---|
| 125,6 → 125,7 |
| return (istate->spsr & STATUS_REG_MODE_MASK) == USER_MODE; |
| } |
| /** Returns Program Counter member of given istate structure. */ |
| static inline unative_t istate_get_pc(istate_t *istate) |
| { |
| /branches/arm/kernel/arch/arm32/include/boot.h |
|---|
| 46,8 → 46,10 |
| /** Struct holding information about single loaded uspace task. */ |
| typedef struct { |
| /** Address where the task was placed. */ |
| uintptr_t addr; |
| /** Size of the task's binary. */ |
| uint32_t size; |
| } utask_t; |
| 55,8 → 57,10 |
| /** Struct holding information about loaded uspace tasks. */ |
| typedef struct { |
| /** Number of loaded tasks. */ |
| uint32_t cnt; |
| /** Array of loaded tasks. */ |
| utask_t tasks[TASKMAP_MAX_RECORDS]; |
| } bootinfo_t; |
| /branches/arm/kernel/arch/arm32/include/atomic.h |
|---|
| 72,6 → 72,7 |
| */ |
| static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); } |
| /** Atomic decrement. |
| * |
| * @param val Variable to be decremented. |
| 78,6 → 79,7 |
| */ |
| static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); } |
| /** Atomic pre-increment. |
| * |
| * @param val Variable to be incremented. |
| 85,6 → 87,7 |
| */ |
| static inline long atomic_preinc(atomic_t *val) { return atomic_add(val, 1); } |
| /** Atomic pre-decrement. |
| * |
| * @param val Variable to be decremented. |
| 92,6 → 95,7 |
| */ |
| static inline long atomic_predec(atomic_t *val) { return atomic_add(val, -1); } |
| /** Atomic post-increment. |
| * |
| * @param val Variable to be incremented. |
| 99,6 → 103,7 |
| */ |
| static inline long atomic_postinc(atomic_t *val) { return atomic_add(val, 1) - 1; } |
| /** Atomic post-decrement. |
| * |
| * @param val Variable to be decremented. |
| /branches/arm/kernel/arch/arm32/include/asm.h |
|---|
| 47,7 → 47,7 |
| } |
| /** Return base address of current stack |
| /** Return base address of current stack. |
| * |
| * Return the base address of the current stack. |
| * The stack is assumed to be STACK_SIZE bytes long. |
| /branches/arm/kernel/arch/arm32/include/mm/page.h |
|---|
| 107,11 → 107,13 |
| /** Level 0 page table entry. */ |
| typedef struct { |
| /* 01b for coarse tables, see below for details */ |
| unsigned descriptor_type : 2; |
| unsigned impl_specific : 3; |
| unsigned domain : 4; |
| unsigned should_be_zero : 1; |
| /* Pointer to the coarse 2nd level page table (holding entries for small (4KB) |
| * or large (64KB) pages. ARM also supports fine 2nd level page tables that |
| * may hold even tiny pages (1KB) but they are bigger (4KB per table in comparison |
| 123,10 → 125,12 |
| /** Level 1 page table entry (small (4KB) pages used). */ |
| typedef struct { |
| /* 0b10 for small pages */ |
| unsigned descriptor_type : 2; |
| unsigned bufferable : 1; |
| unsigned cacheable : 1; |
| /* access permissions for each of 4 subparts of a page |
| * (for each 1KB when small pages used */ |
| unsigned access_permission_0 : 2; |
| 141,10 → 145,13 |
| /** User mode: no access, privileged mode: no access. */ |
| #define PTE_AP_USER_NO_KERNEL_NO 0 |
| /** User mode: no access, privileged mode: read/write. */ |
| #define PTE_AP_USER_NO_KERNEL_RW 1 |
| /** User mode: read only, privileged mode: read/write. */ |
| #define PTE_AP_USER_RO_KERNEL_RW 2 |
| /** User mode: read/write, privileged mode: read/write. */ |
| #define PTE_AP_USER_RW_KERNEL_RW 3 |
| 153,8 → 160,10 |
| /** pte_level0_t and pte_level1_t "not present" flag (used in descriptor_type). */ |
| #define PTE_DESCRIPTOR_NOT_PRESENT 0 |
| /** pte_level0_t coarse page table flag (used in descriptor_type). */ |
| #define PTE_DESCRIPTOR_COARSE_TABLE 1 |
| /** pte_level1_t small page table flag (used in descriptor type). */ |
| #define PTE_DESCRIPTOR_SMALL_PAGE 2 |
| /branches/arm/kernel/arch/arm32/include/cpu.h |
|---|
| 42,14 → 42,19 |
| /** Struct representing ARM CPU identifiaction. */ |
| typedef struct { |
| /** Implementator (vendor) number. */ |
| uint32_t imp_num; |
| /** Variant number. */ |
| uint32_t variant_num; |
| /** Architecture number. */ |
| uint32_t arch_num; |
| /** Primary part number. */ |
| uint32_t prim_part_num; |
| /** Revision number. */ |
| uint32_t rev_num; |
| } cpu_arch_t; |
| /branches/arm/kernel/arch/arm32/src/exception.c |
|---|
| 153,6 → 153,7 |
| ); |
| } |
| /** Switch CPU to mode in which interrupts are serviced (currently it |
| * is Undefined mode). |
| * |
| 186,6 → 187,7 |
| ); |
| } |
| /** Calls exception dispatch routine. */ |
| #define CALL_EXC_DISPATCH(exception) \ |
| asm("mov r0, %0" : : "i" (exception)); \ |
| /branches/arm/kernel/arch/arm32/src/ddi/ddi.c |
|---|
| 37,7 → 37,7 |
| #include <proc/task.h> |
| #include <arch/types.h> |
| /** Enable I/O space range for task. Not used on ARM. |
| /** Enable I/O space range for task (not used on ARM). |
| * |
| * Interrupts are disabled and task is locked. |
| * |
| /branches/arm/kernel/arch/arm32/src/arm32.c |
|---|
| 68,6 → 68,7 |
| } |
| /** Performs arm32 specific initialization before mm is initialized. */ |
| void arch_pre_mm_init(void) |
| { |
| 75,6 → 76,7 |
| interrupts_disable(); |
| } |
| /** Performs arm32 specific initialization afterr mm is initialized. */ |
| void arch_post_mm_init(void) |
| { |
| 92,6 → 94,7 |
| #endif |
| } |
| /** Performs arm32 specific tasks needed after cpu is initialized. |
| * |
| * Currently the function is empty. |
| 100,6 → 103,7 |
| { |
| } |
| /** Performs arm32 specific tasks needed before the multiprocessing is |
| * initialized. |
| * |
| 109,6 → 113,7 |
| { |
| } |
| /** Performs arm32 specific tasks needed after the multiprocessing is |
| * initialized. |
| * |
| 125,6 → 130,7 |
| tlb_invalidate_all(); |
| } |
| /** Performs arm32 specific tasks needed before the new thread is scheduled. |
| * |
| * It sets supervisor_sp. |
| 134,6 → 140,7 |
| supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE-SP_DELTA]; |
| } |
| /** Performs arm32 specific tasks before a thread stops running. |
| * |
| * Currently the function is empty. |
| 142,6 → 149,7 |
| { |
| } |
| /** Halts CPU. */ |
| void cpu_halt(void) |
| { |
| /branches/arm/kernel/arch/arm32/src/mm/tlb.c |
|---|
| 50,6 → 50,7 |
| ); |
| } |
| /** Invalidate all entries in TLB that belong to specified address space. |
| * |
| * @param asid This parameter is ignored as the ARM architecture doesn't support it. |
| 59,6 → 60,7 |
| tlb_invalidate_all(); |
| } |
| /** Invalidate single entry in TLB |
| * |
| * @param page Virtual adress of the page |
| 73,6 → 75,7 |
| ); |
| } |
| /** Invalidate TLB entries for specified page range belonging to specified address space. |
| * |
| * @param asid This parameter is ignored as the ARM architecture doesn't support it. |
| /branches/arm/kernel/arch/arm32/src/mm/page.c |
|---|
| 87,6 → 87,7 |
| * |
| * @param physaddr Physical addres where device is connected |
| * @param size Length of area where device is present |
| * |
| * @return Virtual address where device will be accessable |
| */ |
| uintptr_t hw_map(uintptr_t physaddr, size_t size) |
| /branches/arm/kernel/arch/arm32/src/userspace.c |
|---|
| 55,6 → 55,7 |
| uint32_t pc; |
| } ustate_t; |
| /** Changes processor mode and jumps to the address specified in the first parameter. |
| * |
| * @param kernel_uarg Userspace settings (entry point, stack, ...). |
| /branches/arm/kernel/arch/arm32/src/interrupt.c |
|---|
| 56,6 → 56,7 |
| return ipl; |
| } |
| /** Enable interrupts. |
| * |
| * @return Old interrupt priority level. |
| 69,6 → 70,7 |
| return ipl; |
| } |
| /** Restore interrupt priority level. |
| * |
| * @param ipl Saved interrupt priority level. |
| 81,6 → 83,7 |
| ); |
| } |
| /** Read interrupt priority level. |
| * |
| * @return Current interrupt priority level. |
| 90,6 → 93,7 |
| return current_status_reg_read(); |
| } |
| /** Initialize basic tables for exception dispatching |
| * and starts the timer. |
| */ |