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Ignore whitespace Rev 3856 → Rev 3855

/trunk/kernel/arch/ppc32/src/mm/tlb.c
26,7 → 26,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
 
/** @addtogroup ppc32mm
/** @addtogroup ppc32mm
* @{
*/
/** @file
47,11 → 47,6
static unsigned int seed_real __attribute__ ((section("K_UNMAPPED_DATA_START"))) = 42;
 
 
#define TLB_FLUSH \
"tlbie %0\n" \
"addi %0, %0, 0x1000\n"
 
 
/** Try to find PTE for faulting address
*
* Try to find PTE for faulting address.
416,87 → 411,8
 
void tlb_invalidate_all(void)
{
uint32_t index;
asm volatile (
"li %0, 0\n"
"sync\n"
TLB_FLUSH
TLB_FLUSH
TLB_FLUSH
TLB_FLUSH
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"eieio\n"
"tlbsync\n"
"sync\n"
: "=r" (index)
);
}
 
/trunk/kernel/arch/ppc32/include/asm/regname.h
224,7 → 224,6
#define hid0_dce (1 << 14)
#define hid0_icfi (1 << 11)
#define hid0_dci (1 << 10)
#define hid0_sten (1 << 7)
 
#endif
 
/trunk/kernel/arch/ppc32/include/barrier.h
55,7 → 55,6
"dcbst 0, %0\n"
"sync\n"
"icbi 0, %0\n"
"sync\n"
"isync\n"
:: "r" (addr)
);
77,10 → 76,7
asm volatile ("icbi 0, %0\n" :: "r" (addr + i));
}
 
asm volatile (
"sync\n"
"isync\n"
);
asm volatile ("isync");
}
 
#endif
/trunk/boot/arch/ppc32/loader/asm.S
29,25 → 29,13
#include "asm.h"
#include "regname.h"
 
.macro SMC_COHERENCY addr
.macro FLUSH_CACHE addr
dcbst 0, \addr
sync
icbi 0, \addr
sync
isync
.endm
 
.macro FLUSH_DCACHE addr
dcbst 0, \addr
sync
isync
.endm
 
.macro TLB_FLUSH reg
tlbie \reg
addi \reg, \reg, 0x1000
.endm
 
.text
 
.global halt
183,7 → 171,7
lwz r28, 0(r29)
stw r28, 0(r30)
SMC_COHERENCY r30
FLUSH_CACHE r30
addi r29, r29, 4
addi r30, r30, 4
280,7 → 268,7
# write zeroes
stw r29, 0(r31)
FLUSH_DCACHE r31
FLUSH_CACHE r31
addi r31, r31, 4
subi r30, r30, 4
340,86 → 328,7
#endif
# flush TLB
li r31, 0
sync
TLB_FLUSH r31
TLB_FLUSH r31
TLB_FLUSH r31
TLB_FLUSH r31
TLB_FLUSH r31
TLB_FLUSH r31
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eieio
tlbsync
sync
# start the kernel
#
/trunk/boot/arch/ppc32/loader/regname.h
217,6 → 217,5
#define hid0_dce (1 << 14)
#define hid0_icfi (1 << 11)
#define hid0_dci (1 << 10)
#define hid0_sten (1 << 7)
 
#endif