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Ignore whitespace Rev 3593 → Rev 3592

/branches/sparc/kernel/arch/sparc64/include/drivers/ns16550.h
35,7 → 35,67
#ifndef KERN_sparc64_NS16550_H_
#define KERN_sparc64_NS16550_H_
 
#include <arch/types.h>
#include <arch/drivers/kbd.h>
 
/* NS16550 registers */
#define RBR_REG 0 /** Receiver Buffer Register. */
#define IER_REG 1 /** Interrupt Enable Register. */
#define IIR_REG 2 /** Interrupt Ident Register (read). */
#define FCR_REG 2 /** FIFO control register (write). */
#define LCR_REG 3 /** Line Control register. */
#define LSR_REG 5 /** Line Status Register. */
 
#define IER_ERBFI 0x01 /** Enable Receive Buffer Full Interrupt. */
 
#define LCR_DLAB 0x80 /** Divisor Latch Access bit. */
 
/** Structure representing the ns16550 device. */
typedef struct {
devno_t devno;
volatile uint8_t *reg; /** Memory mapped registers of the ns16550. */
} ns16550_t;
 
static inline uint8_t ns16550_rbr_read(ns16550_t *dev)
{
return dev->reg[RBR_REG];
}
 
static inline uint8_t ns16550_ier_read(ns16550_t *dev)
{
return dev->reg[IER_REG];
}
 
static inline void ns16550_ier_write(ns16550_t *dev, uint8_t v)
{
dev->reg[IER_REG] = v;
}
 
static inline uint8_t ns16550_iir_read(ns16550_t *dev)
{
return dev->reg[IIR_REG];
}
 
static inline void ns16550_fcr_write(ns16550_t *dev, uint8_t v)
{
dev->reg[FCR_REG] = v;
}
 
static inline uint8_t ns16550_lcr_read(ns16550_t *dev)
{
return dev->reg[LCR_REG];
}
 
static inline void ns16550_lcr_write(ns16550_t *dev, uint8_t v)
{
dev->reg[LCR_REG] = v;
}
 
static inline uint8_t ns16550_lsr_read(ns16550_t *dev)
{
return dev->reg[LSR_REG];
}
 
#endif
 
/** @}
/branches/sparc/kernel/arch/sparc64/include/asm.h
42,56 → 42,7
#include <arch/register.h>
#include <config.h>
#include <arch/stack.h>
#include <arch/barrier.h>
 
static inline void outb(ioport_t port, uint8_t v)
{
*((volatile uint8_t *)(port)) = v;
memory_barrier();
}
 
static inline void outw(ioport_t port, uint16_t v)
{
*((volatile uint16_t *)(port)) = v;
memory_barrier();
}
 
static inline void outl(ioport_t port, uint32_t v)
{
*((volatile uint32_t *)(port)) = v;
memory_barrier();
}
 
static inline uint8_t inb(ioport_t port)
{
uint8_t rv;
 
rv = *((volatile uint8_t *)(port));
memory_barrier();
 
return rv;
}
 
static inline uint16_t inw(ioport_t port)
{
uint16_t rv;
 
rv = *((volatile uint16_t *)(port));
memory_barrier();
 
return rv;
}
 
static inline uint32_t inl(ioport_t port)
{
uint32_t rv;
 
rv = *((volatile uint32_t *)(port));
memory_barrier();
 
return rv;
}
 
/** Read Processor State register.
*
* @return Value of PSTATE register.
/branches/sparc/kernel/arch/sparc64/include/types.h
54,8 → 54,6
 
typedef uint64_t ipl_t;
 
typedef uint64_t ioport_t;
 
typedef uint64_t unative_t;
typedef int64_t native_t;
 
/branches/sparc/kernel/arch/sparc64/src/drivers/kbd.c
147,7 → 147,7
#endif
#ifdef CONFIG_NS16550
case KBD_NS16550:
ns16550_init(devno, inr, (ioport_t)vaddr);
ns16550_init(devno, inr, vaddr);
break;
#endif
default:
/branches/sparc/kernel/arch/ia64/include/asm.h
39,11 → 39,10
#include <arch/types.h>
#include <arch/register.h>
 
typedef uint64_t ioport_t;
 
#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
 
static inline void outb(ioport_t port,uint8_t v)
static inline void outb(uint64_t port,uint8_t v)
{
*((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
 
50,7 → 49,7
asm volatile ("mf\n" ::: "memory");
}
 
static inline void outw(ioport_t port,uint16_t v)
static inline void outw(uint64_t port,uint16_t v)
{
*((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
 
57,7 → 56,7
asm volatile ("mf\n" ::: "memory");
}
 
static inline void outl(ioport_t port,uint32_t v)
static inline void outl(uint64_t port,uint32_t v)
{
*((uint32_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 )))) = v;
 
66,7 → 65,7
 
 
 
static inline uint8_t inb(ioport_t port)
static inline uint8_t inb(uint64_t port)
{
asm volatile ("mf\n" ::: "memory");
 
73,7 → 72,7
return *((uint8_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xfff) | ( (port >> 2) << 12 ))));
}
 
static inline uint16_t inw(ioport_t port)
static inline uint16_t inw(uint64_t port)
{
asm volatile ("mf\n" ::: "memory");
 
80,7 → 79,7
return *((uint16_t *)(IA64_IOSPACE_ADDRESS + ( (port & 0xffE) | ( (port >> 2) << 12 ))));
}
 
static inline uint32_t inl(ioport_t port)
static inline uint32_t inl(uint64_t port)
{
asm volatile ("mf\n" ::: "memory");
 
99,14 → 98,9
{
uint64_t v;
 
//I'm not sure why but this code bad inlines in scheduler,
//so THE shifts about 16B and causes kernel panic
//asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
//return v;
asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
//this code have the same meaning but inlines well
asm volatile ("mov %0 = r12" : "=r" (v) );
return v & (~(STACK_SIZE-1));
return v;
}
 
/** Return Processor State Register.
158,16 → 152,6
return v;
}
 
static inline uint64_t cr64_read(void)
{
uint64_t v;
asm volatile ("mov %0 = cr64\n" : "=r" (v));
return v;
}
 
 
/** Write ITC (Interval Timer Counter) register.
*
* @param v New counter value.
/branches/sparc/kernel/arch/ia64/include/mm/page.h
46,20 → 46,8
/** Bit width of the TLB-locked portion of kernel address space. */
#define KERNEL_PAGE_WIDTH 28 /* 256M */
#define IO_PAGE_WIDTH 26 /* 64M */
#define FW_PAGE_WIDTH 28 /* 256M */
 
/** Staticly mapped IO spaces */
 
/* Firmware area (bellow 4GB in phys mem) */
#define FW_OFFSET 0x00000000F0000000
/* Legacy IO space */
#define IO_OFFSET 0x0001000000000000
/* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000*/
#define VIO_OFFSET 0x0002000000000000
 
 
 
 
#define PPN_SHIFT 12
 
#define VRN_SHIFT 61
/branches/sparc/kernel/arch/ia64/include/drivers/it.h
41,7 → 41,7
* from firmware.
*
*/
#define IT_DELTA it_delta
#define IT_DELTA 100000
 
extern void it_init(void);
 
/branches/sparc/kernel/arch/ia64/include/bootinfo.h
29,8 → 29,8
#ifndef KERN_ia64_BOOTINFO_H_
#define KERN_ia64_BOOTINFO_H_
 
#define BOOTINFO_ADDRESS 0x4401000
 
 
#define CONFIG_INIT_TASKS 32
 
typedef struct {
46,12 → 46,6
 
typedef struct {
binit_t taskmap;
 
unsigned long * sapic;
unsigned long sys_freq;
unsigned long freq_scale;
unsigned int wakeup_intno;
 
} bootinfo_t;
 
extern bootinfo_t *bootinfo;
/branches/sparc/kernel/arch/ia64/include/cpu.h
38,7 → 38,6
#include <arch/types.h>
#include <arch/register.h>
#include <arch/asm.h>
#include <arch/bootinfo.h>
 
#define FAMILY_ITANIUM 0x7
#define FAMILY_ITANIUM2 0x1f
64,33 → 63,6
return v;
}
 
 
#define CR64_ID_SHIFT 24
#define CR64_ID_MASK 0xff000000
#define CR64_EID_SHIFT 16
#define CR64_EID_MASK 0xff0000
 
static inline int ia64_get_cpu_id(void)
{
uint64_t cr64=cr64_read();
return ((CR64_ID_MASK)&cr64)>>CR64_ID_SHIFT;
}
 
static inline int ia64_get_cpu_eid(void)
{
uint64_t cr64=cr64_read();
return ((CR64_EID_MASK)&cr64)>>CR64_EID_SHIFT;
}
 
 
 
static inline void ipi_send_ipi(int id,int eid,int intno)
{
(bootinfo->sapic)[2*(id*256+eid)]=intno;
}
 
 
 
#endif
 
/** @}
/branches/sparc/kernel/arch/ia64/include/atomic.h
51,20 → 51,6
return v;
}
 
 
static inline uint64_t test_and_set(atomic_t *val) {
uint64_t v;
asm volatile (
"movl %0=0x01;;\n"
"xchg8 %0=%1,%0;;\n"
: "=r" (v),"+m" (val->count)
);
return v;
}
 
 
static inline void atomic_inc(atomic_t *val) { atomic_add(val, 1); }
static inline void atomic_dec(atomic_t *val) { atomic_add(val, -1); }
 
/branches/sparc/kernel/arch/ia64/Makefile.inc
82,7 → 82,6
arch/$(ARCH)/src/mm/vhpt.c \
arch/$(ARCH)/src/proc/scheduler.c \
arch/$(ARCH)/src/ddi/ddi.c \
arch/$(ARCH)/src/smp/smp.c \
arch/$(ARCH)/src/drivers/it.c
 
ifeq ($(MACHINE),ski)
99,7 → 98,3
BFD = binary
endif
 
ifeq ($(CONFIG_SMP),y)
DEFS += -DCONFIG_SMP
endif
 
/branches/sparc/kernel/arch/ia64/src/smp/smp.c
File deleted
/branches/sparc/kernel/arch/ia64/src/mm/frame.c
42,31 → 42,20
* for real ia64 systems that provide memory map.
*/
#define MEMORY_SIZE (64 * 1024 * 1024)
#define MEMORY_BASE (0 * 64 * 1024 * 1024)
#define MEMORY_BASE (64 * 1024 * 1024)
 
#define ONE_TO_ONE_MAPPING_SIZE (256*1048576) // Mapped at start
 
#define ROM_BASE 0xa0000 //For ski
#define ROM_SIZE (384 * 1024) //For ski
void poke_char(int x,int y,char ch, char c);
 
uintptr_t last_frame;
 
void frame_arch_init(void)
{
 
if(config.cpu_active==1)
{
zone_create(MEMORY_BASE >> FRAME_WIDTH, SIZE2FRAMES(MEMORY_SIZE), (MEMORY_SIZE) >> FRAME_WIDTH, 0);
zone_create(MEMORY_BASE >> FRAME_WIDTH, SIZE2FRAMES(MEMORY_SIZE), (MEMORY_SIZE) >> FRAME_WIDTH, 0);
/*
* Blacklist ROM regions.
*/
//frame_mark_unavailable(ADDR2PFN(ROM_BASE), SIZE2FRAMES(ROM_SIZE));
 
frame_mark_unavailable(ADDR2PFN(0), SIZE2FRAMES(1048576));
last_frame=SIZE2FRAMES((VRN_KERNEL<<VRN_SHIFT)+ONE_TO_ONE_MAPPING_SIZE);
}
/*
* Blacklist ROM regions.
*/
frame_mark_unavailable(ADDR2PFN(ROM_BASE), SIZE2FRAMES(ROM_SIZE));
}
 
/** @}
/branches/sparc/kernel/arch/ia64/src/mm/page.c
47,7 → 47,6
#include <arch/asm.h>
#include <arch/barrier.h>
#include <memstr.h>
#include <align.h>
 
static void set_environment(void);
 
263,27 → 262,5
v->present.tag.tag_word = tag;
}
 
extern uintptr_t last_frame;
 
 
uintptr_t hw_map(uintptr_t physaddr, size_t size)
{
if (last_frame + ALIGN_UP(size, PAGE_SIZE) > KA2PA(KERNEL_ADDRESS_SPACE_END_ARCH))
panic("Unable to map physical memory %p (%d bytes)", physaddr, size)
uintptr_t virtaddr = PA2KA(last_frame);
pfn_t i;
for (i = 0; i < ADDR2PFN(ALIGN_UP(size, PAGE_SIZE)); i++) {
uintptr_t addr = PFN2ADDR(i);
page_mapping_insert(AS_KERNEL, virtaddr + addr, physaddr + addr, PAGE_NOT_CACHEABLE | PAGE_WRITE);
}
last_frame = ALIGN_UP(last_frame + size, FRAME_SIZE);
return virtaddr;
}
 
 
 
/** @}
*/
/branches/sparc/kernel/arch/ia64/src/drivers/it.c
46,16 → 46,6
 
#define IT_SERVICE_CLOCKS 64
 
#define FREQ_NUMERATOR_SHIFT 32
#define FREQ_NUMERATOR_MASK 0xffffffff00000000LL
 
#define FREQ_DENOMINATOR_SHIFT 0
#define FREQ_DENOMINATOR_MASK 0xffffffffLL
 
 
uint64_t it_delta;
 
 
static irq_t it_irq;
 
static irq_ownership_t it_claim(void);
65,25 → 55,14
void it_init(void)
{
cr_itv_t itv;
if(config.cpu_active==1)
{
irq_initialize(&it_irq);
it_irq.inr = INTERRUPT_TIMER;
it_irq.devno = device_assign_devno();
it_irq.claim = it_claim;
it_irq.handler = it_interrupt;
irq_register(&it_irq);
uint64_t base_freq;
base_freq = ((bootinfo->freq_scale) & FREQ_NUMERATOR_MASK) >> FREQ_NUMERATOR_SHIFT;
base_freq *= bootinfo->sys_freq;
base_freq /= ((bootinfo->freq_scale) & FREQ_DENOMINATOR_MASK) >> FREQ_DENOMINATOR_SHIFT;
it_delta = base_freq /HZ;
}
 
irq_initialize(&it_irq);
it_irq.inr = INTERRUPT_TIMER;
it_irq.devno = device_assign_devno();
it_irq.claim = it_claim;
it_irq.handler = it_interrupt;
irq_register(&it_irq);
 
/* initialize Interval Timer external interrupt vector */
itv.value = itv_read();
itv.vector = INTERRUPT_TIMER;
/branches/sparc/kernel/arch/ia64/src/ia64.c
54,17 → 54,7
#include <arch/drivers/ega.h>
#include <arch/bootinfo.h>
#include <genarch/kbd/i8042.h>
#include <genarch/kbd/ns16550.h>
#include <smp/smp.h>
#include <smp/ipi.h>
#include <arch/atomic.h>
#include <panic.h>
#include <print.h>
 
/*NS16550 as a COM 1*/
#define NS16550_IRQ 4
#define NS16550_PORT 0x3f8
 
bootinfo_t *bootinfo;
 
void arch_pre_main(void)
112,15 → 102,12
 
void arch_post_mm_init(void)
{
if(config.cpu_active==1)
{
irq_init(INR_COUNT, INR_COUNT);
irq_init(INR_COUNT, INR_COUNT);
#ifdef SKI
ski_init_console();
ski_init_console();
#else
ega_init();
ega_init();
#endif
}
it_init();
}
 
140,9 → 127,6
{
while (1) {
i8042_poll();
#ifdef CONFIG_NS16550
ns16550_poll();
#endif
thread_usleep(POLL_INTERVAL);
}
}
151,7 → 135,7
void arch_post_smp_init(void)
{
 
{
if (config.cpu_active == 1) {
/*
* Create thread that polls keyboard.
*/
169,10 → 153,6
/* keyboard controller */
i8042_init(kbd, IRQ_KBD, mouse, IRQ_MOUSE);
 
#ifdef CONFIG_NS16550
ns16550_init(kbd, NS16550_IRQ, NS16550_PORT); // as a COM 1
#else
#endif
thread_t *t;
t = thread_create(i8042_kkbdpoll, NULL, TASK, 0, "kkbdpoll", true);
if (!t)
184,7 → 164,6
}
}
 
 
/** Enter userspace and never return. */
void userspace(uspace_arg_t *kernel_uarg)
{
245,7 → 224,7
 
void arch_reboot(void)
{
outb(0x64,0xfe);
// TODO
while (1);
}
 
/branches/sparc/kernel/arch/ia64/src/start.S
39,10 → 39,12
#define KERNEL_TRANSLATION_D 0x0010000000000661
#define KERNEL_TRANSLATION_VIO 0x0010000000000671
#define KERNEL_TRANSLATION_IO 0x00100FFFFC000671
#define KERNEL_TRANSLATION_FW 0x00100000F0000671
#define VIO_OFFSET 0x0002000000000000
 
#define IO_OFFSET 0x0001000000000000
 
 
 
.section K_TEXT_START, "ax"
 
.global kernel_image_start
51,18 → 53,6
kernel_image_start:
.auto
 
#identifi self(CPU) in OS structures by ID / EID
mov r9=cr64
mov r10=1
movl r12=0xffffffff
movl r8=cpu_by_id_eid_list
and r8=r8,r12
shr r9=r9,16
add r8=r8,r9
st1 [r8]=r10
 
 
 
mov psr.l = r0
srlz.i
srlz.d
124,25 → 114,8
itr.d dtr[r7] = r10
 
 
#setup mapping for fimware arrea (also SAPIC)
mov r11 = cr.itir ;;
movl r10 = ~0xfc;;
and r10 =r10 , r11 ;;
movl r11 = (FW_PAGE_WIDTH << PS_SHIFT);;
or r10 =r10 , r11 ;;
mov cr.itir = r10;;
 
 
movl r7 = 3
movl r8 = (VRN_KERNEL << VRN_SHIFT) | FW_OFFSET
mov cr.ifa = r8
movl r10 = (KERNEL_TRANSLATION_FW)
itr.d dtr[r7] = r10
 
 
 
 
 
# initialize PSR
movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */
mov r9 = psr
169,12 → 142,6
 
# switch to register bank 1
bsw.1
 
#Am'I BSP or AP
movl r20=bsp_started;;
ld8 r20=[r20];;
cmp.eq p3,p2=r20,r0;;
 
# initialize register stack
mov ar.rsc = r0
193,35 → 160,25
movl r1 = _hardcoded_load_address
/*
* Initialize hardcoded_* variables. Do only BSP
* Initialize hardcoded_* variables.
*/
(p3) movl r14 = _hardcoded_ktext_size
(p3) movl r15 = _hardcoded_kdata_size
(p3) movl r16 = _hardcoded_load_address ;;
(p3) addl r17 = @gprel(hardcoded_ktext_size), gp
(p3) addl r18 = @gprel(hardcoded_kdata_size), gp
(p3) addl r19 = @gprel(hardcoded_load_address), gp
(p3) addl r21 = @gprel(bootinfo), gp
movl r14 = _hardcoded_ktext_size
movl r15 = _hardcoded_kdata_size
movl r16 = _hardcoded_load_address ;;
addl r17 = @gprel(hardcoded_ktext_size), gp
addl r18 = @gprel(hardcoded_kdata_size), gp
addl r19 = @gprel(hardcoded_load_address), gp
addl r21 = @gprel(bootinfo), gp
;;
(p3) st8 [r17] = r14
(p3) st8 [r18] = r15
(p3) st8 [r19] = r16
(p3) st8 [r21] = r20
st8 [r17] = r14
st8 [r18] = r15
st8 [r19] = r16
st8 [r21] = r20
 
ssm (1 << 19) ;; /* Disable f32 - f127 */
srlz.i
srlz.d ;;
 
(p2) movl r18 = main_ap ;;
(p2) mov b1 = r18 ;;
(p2) br.call.sptk.many b0 = b1
 
#Mark that BSP is on
mov r20=1;;
movl r21=bsp_started;;
st8 [r21]=r20;;
 
 
br.call.sptk.many b0 = arch_pre_main
 
movl r18 = main_bsp ;;
231,46 → 188,3
 
0:
br 0b
.align 4096
 
kernel_image_ap_start:
.auto
#identifi self(CPU) in OS structures by ID / EID
mov r9=cr64
mov r10=1
movl r12=0xffffffff
movl r8=cpu_by_id_eid_list
and r8=r8,r12
shr r9=r9,16
add r8=r8,r9
st1 [r8]=r10
#wait for wakeup sychro signal (#3 in cpu_by_id_eid_list)
kernel_image_ap_start_loop:
movl r11=kernel_image_ap_start_loop
and r11=r11,r12
mov b1 = r11
 
ld1 r20=[r8];;
movl r21=3;;
cmp.eq p2,p3=r20,r21;;
(p3)br.call.sptk.many b0 = b1
 
movl r11=kernel_image_start
and r11=r11,r12
mov b1 = r11
br.call.sptk.many b0 = b1
 
 
.align 16
.global bsp_started
bsp_started:
.space 8
 
 
.align 4096
.global cpu_by_id_eid_list
cpu_by_id_eid_list:
.space 65536
 
 
/branches/sparc/kernel/arch/ppc32/src/asm.S
66,9 → 66,9
mr sp, r4
 
# %r6 is defined to hold pcb_ptr - set it to 0
# %r3 is defined to hold pcb_ptr - set it to 0
 
xor r6, r6, r6
xor r3, r3, r3
# jump to userspace
/branches/sparc/kernel/arch/ppc32/src/mm/tlb.c
96,6 → 96,7
return NULL;
case AS_PF_FAULT:
page_table_lock(as, lock);
printf("Page fault.\n");
*pfrc = rc;
return NULL;
default:
/branches/sparc/kernel/arch/ppc64/src/mm/page.c
103,6 → 103,7
return NULL;
case AS_PF_FAULT:
page_table_lock(as, lock);
printf("Page fault.\n");
*pfrc = rc;
return NULL;
default:
/branches/sparc/kernel/arch/mips32/src/mm/tlb.c
429,6 → 429,7
break;
case AS_PF_FAULT:
page_table_lock(AS, true);
printf("Page fault.\n");
*pfrc = AS_PF_FAULT;
return NULL;
break;