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Ignore whitespace Rev 4204 → Rev 4203

/branches/dd/uspace/srv/pci/pci.c
41,10 → 41,9
/*
* Gain control over PCI configuration ports.
*/
void * addr;
pio_enable((void *) PCI_CONF1, PCI_CONF1_SIZE, &addr);
iospace_enable(task_get_id(), (void *) PCI_CONF1, PCI_CONF1_SIZE);
 
pacc = pci_alloc(); /* Get the pci_access structure */
pacc = pci_alloc(); /* Get the pci_access structure */
pci_init(pacc); /* Initialize the PCI library */
pci_scan_bus(pacc); /* We want to get the list of devices */
for(dev=pacc->devices; dev; dev=dev->next) { /* Iterate over all devices */
/branches/dd/uspace/srv/pci/libpci/i386-ports.c
9,12 → 9,48
*/
 
#include <unistd.h>
#include <ddi.h>
#include <libarch/ddi.h>
 
#include "internal.h"
 
static inline void outb(u8 b, u16 port)
{
asm volatile ("outb %0, %1\n" :: "a" (b), "d" (port));
}
 
static inline void outw(u16 w, u16 port)
{
asm volatile ("outw %0, %1\n" :: "a" (w), "d" (port));
}
 
static inline void outl(u32 l, u16 port)
{
asm volatile ("outl %0, %1\n" :: "a" (l), "d" (port));
}
 
static inline u8 inb(u16 port)
{
u8 val;
 
asm volatile ("inb %1, %0 \n" : "=a" (val) : "d"(port));
return val;
}
 
static inline u16 inw(u16 port)
{
u16 val;
 
asm volatile ("inw %1, %0 \n" : "=a" (val) : "d"(port));
return val;
}
 
static inline u32 inl(u16 port)
{
u32 val;
 
asm volatile ("inl %1, %0 \n" : "=a" (val) : "d"(port));
return val;
}
 
static void conf12_init(struct pci_access *a)
{
}
71,16 → 107,14
unsigned int tmp;
int res = 0;
 
pio_write_8(0xCFB, 0x01);
tmp = pio_read_32(0xCF8);
pio_write_32(0xCF8, 0x80000000);
if (pio_read_32(0xCF8) == 0x80000000) {
outb(0x01, 0xCFB);
tmp = inl(0xCF8);
outl(0x80000000, 0xCF8);
if (inl(0xCF8) == 0x80000000)
res = 1;
}
pio_write_32(0xCF8, tmp);
if (res) {
outl(tmp, 0xCF8);
if (res)
res = intel_sanity_check(a, &pm_intel_conf1);
}
return res;
}
 
91,18 → 125,18
if (pos >= 256)
return 0;
 
pio_write_32(0xcf8, 0x80000000 | ((d->bus & 0xff) << 16) |
(PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3));
outl(0x80000000 | ((d->bus & 0xff) << 16) |
(PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3), 0xcf8);
 
switch (len) {
case 1:
buf[0] = pio_read_8(addr);
buf[0] = inb(addr);
break;
case 2:
((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr));
((u16 *) buf)[0] = cpu_to_le16(inw(addr));
break;
case 4:
((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr));
((u32 *) buf)[0] = cpu_to_le32(inl(addr));
break;
default:
return pci_generic_block_read(d, pos, buf, len);
117,18 → 151,18
if (pos >= 256)
return 0;
 
pio_write_32(0xcf8, 0x80000000 | ((d->bus & 0xff) << 16) |
(PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3));
outl(0x80000000 | ((d->bus & 0xff) << 16) |
(PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3), 0xcf8);
 
switch (len) {
case 1:
pio_write_8(addr, buf[0]);
outb(buf[0], addr);
break;
case 2:
pio_write_16(addr, le16_to_cpu(((u16 *) buf)[0]));
outw(le16_to_cpu(((u16 *) buf)[0]), addr);
break;
case 4:
pio_write_32(addr, le32_to_cpu(((u32 *) buf)[0]));
outl(le32_to_cpu(((u32 *) buf)[0]), addr);
break;
default:
return pci_generic_block_write(d, pos, buf, len);
143,10 → 177,10
static int conf2_detect(struct pci_access *a)
{
/* This is ugly and tends to produce false positives. Beware. */
pio_write_8(0xCFB, 0x00);
pio_write_8(0xCF8, 0x00);
pio_write_8(0xCFA, 0x00);
if (pio_read_8(0xCF8) == 0x00 && pio_read_8(0xCFA) == 0x00)
outb(0x00, 0xCFB);
outb(0x00, 0xCF8);
outb(0x00, 0xCFA);
if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
return intel_sanity_check(a, &pm_intel_conf2);
else
return 0;
162,23 → 196,23
if (d->dev >= 16)
/* conf2 supports only 16 devices per bus */
return 0;
pio_write_8(0xcf8, (d->func << 1) | 0xf0);
pio_write_8(0xcfa, d->bus);
outb((d->func << 1) | 0xf0, 0xcf8);
outb(d->bus, 0xcfa);
switch (len) {
case 1:
buf[0] = pio_read_8(addr);
buf[0] = inb(addr);
break;
case 2:
((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr));
((u16 *) buf)[0] = cpu_to_le16(inw(addr));
break;
case 4:
((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr));
((u32 *) buf)[0] = cpu_to_le32(inl(addr));
break;
default:
pio_write_8(0xcf8, 0);
outb(0, 0xcf8);
return pci_generic_block_read(d, pos, buf, len);
}
pio_write_8((void *)0xcf8, 0);
outb(0, 0xcf8);
return 1;
}
 
191,23 → 225,23
 
if (d->dev >= 16)
d->access->error("conf2_write: only first 16 devices exist.");
pio_write_8(0xcf8, (d->func << 1) | 0xf0);
pio_write_8(0xcfa, d->bus);
outb((d->func << 1) | 0xf0, 0xcf8);
outb(d->bus, 0xcfa);
switch (len) {
case 1:
pio_write_8(addr, buf[0]);
outb(buf[0], addr);
break;
case 2:
pio_write_16(addr, le16_to_cpu(*(u16 *) buf));
outw(le16_to_cpu(*(u16 *) buf), addr);
break;
case 4:
pio_write_32(addr, le32_to_cpu(*(u32 *) buf));
outl(le32_to_cpu(*(u32 *) buf), addr);
break;
default:
pio_write_8(0xcf8, 0);
outb(0, 0xcf8);
return pci_generic_block_write(d, pos, buf, len);
}
pio_write_8(0xcf8, 0);
outb(0, 0xcf8);
return 1;
}