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Ignore whitespace Rev 3835 → Rev 3834

/branches/sparc/kernel/arch/sparc64/include/sun4v/arch.h
File deleted
/branches/sparc/kernel/arch/sparc64/include/mm/sun4v/tlb.h
36,9 → 36,6
#ifndef KERN_sparc64_sun4v_TLB_H_
#define KERN_sparc64_sun4v_TLB_H_
 
#define MMU_FSA_ALIGNMENT 64
#define MMU_FSA_SIZE 128
 
#ifndef __ASM__
 
#include <arch/mm/sun4v/tte.h>
/branches/sparc/kernel/arch/sparc64/include/mm/sun4v/mmu.h
36,8 → 36,6
#ifndef KERN_sparc64_sun4v_MMU_H_
#define KERN_sparc64_sun4v_MMU_H_
 
#define ASI_REAL 0x14
 
#define VA_PRIMARY_CONTEXT_REG 0x8 /**< DMMU primary context registeri VA. */
#define ASI_PRIMARY_CONTEXT_REG 0x21 /**< DMMU primary context register ASI. */
 
/branches/sparc/kernel/arch/sparc64/include/trap/sun4v/mmu.h
40,8 → 40,6
 
#include <arch/stack.h>
#include <arch/sun4v/regdef.h>
#include <arch/sun4v/arch.h>
#include <arch/sun4v/hypercall.h>
#include <arch/mm/sun4v/tlb.h>
#include <arch/mm/sun4v/mmu.h>
#include <arch/mm/sun4v/tte.h>
59,52 → 57,23
 
#ifdef __ASM__
 
/* MMU fault status area data fault offset */
#define FSA_DFA_OFFSET 0x48
 
/* MMU fault status area data context */
#define FSA_DFC_OFFSET 0x50
 
/* offset of the target address within the TTE Data entry */
#define TTE_DATA_TADDR_OFFSET 13
 
.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER
.endm
 
/*
* Handler of the Fast Data Access MMU Miss trap. If the trap occurred in the kernel
* (context 0), an identity mapping (with displacement) is installed. Otherwise
* a higher level service routine is called.
*
* TODO implement calling the higher level service routine
* So far it is here only to process the trap which occurs when the kernel
* needs to access the bootinfo structure, which is placed in the bootloader
* memory (i.e. before address 0x400000).
*/
.macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
 
mov SCRATCHPAD_MMU_FSA, %g1
ldxa [%g1] ASI_SCRATCHPAD, %g1 ! g1 <= RA of MMU fault status area
 
/* service by higher-level routine when context != 0 */
add %g1, FSA_DFC_OFFSET, %g2 ! g2 <= RA of data fault context
ldxa [%g2] ASI_REAL, %g3 ! read the fault context
brnz %g3, 0f
nop
 
/* read the faulting address */
add %g1, FSA_DFA_OFFSET, %g2 ! g2 <= RA of data fault address
ldxa [%g2] ASI_REAL, %g1 ! read the fault address
srlx %g1, TTE_DATA_TADDR_OFFSET, %g1 ! truncate it to page boundary
sllx %g1, TTE_DATA_TADDR_OFFSET, %g1
 
/* exclude page number 0 from installing the identity mapping */
brz %g1, 0f
nop
 
/* installing the identity does not fit into 32 instructions, call a separate routine */
ba install_identity_mapping
nop
 
0: ! TODO - call higher level service routine
 
save %sp, -STACK_WINDOW_SAVE_AREA_SIZE, %sp
set 0x8000, %o0
set 0x0, %o1
setx 0x80000000804087c3, %g1, %o2
set 0x3, %o3
ta 0x83
restore %g0, 0, %g0
retry
.endm
 
.macro FAST_DATA_ACCESS_PROTECTION_HANDLER tl
/branches/sparc/kernel/arch/sparc64/Makefile.inc
111,7 → 111,7
arch/$(ARCH)/src/$(USARCH)/sparc64.c \
arch/$(ARCH)/src/mm/$(USARCH)/tlb.c \
arch/$(ARCH)/src/mm/$(USARCH)/as.c \
arch/$(ARCH)/src/cpu/$(USARCH)/cpu.c \
arch/$(ARCH)/src/cpu/$(USARCH)/cpu.c
 
# specific to machine type
 
128,6 → 128,7
arch/$(ARCH)/src/mm/page.c \
arch/$(ARCH)/src/proc/scheduler.c \
arch/$(ARCH)/src/proc/thread.c \
arch/$(ARCH)/src/trap/mmu.S \
arch/$(ARCH)/src/trap/trap.c \
arch/$(ARCH)/src/trap/exception.c \
arch/$(ARCH)/src/trap/interrupt.c \
142,8 → 143,7
ifeq ($(USARCH),sun4v)
ARCH_SOURCES += \
arch/$(ARCH)/src/drivers/niagara.c \
arch/$(ARCH)/src/sun4v/md.c \
arch/$(ARCH)/src/trap/sun4v/mmu.S
arch/$(ARCH)/src/sun4v/md.c
endif
 
ifeq ($(CONFIG_SMP),y)
/branches/sparc/kernel/arch/sparc64/src/sun4v/start.S
31,8 → 31,6
#include <arch/stack.h>
#include <arch/sun4v/regdef.h>
#include <arch/sun4v/hypercall.h>
#include <arch/sun4v/arch.h>
#include <arch/sun4v/cpu.h>
#include <arch/mm/pagesize.h>
#include <arch/mm/sun4v/tte.h>
#include <arch/mm/sun4v/mmu.h>
193,34 → 191,6
stx %l6, [%l4 + %lo(physmem_base)]
 
/*
* Set CPUID.
*/
__HYPERCALL_FAST(CPU_MYID)
mov SCRATCHPAD_CPUID, %g1
stxa %o1, [%g1] ASI_SCRATCHPAD
 
/*
* Set MMU fault status area for the current CPU.
*/
set mmu_fsas, %o0 ! o0 <= addr. of fault status areas array
add %o0, %l6, %o0 ! kernel address to real address
mulx %o1, MMU_FSA_SIZE, %g1 ! g1 <= offset of current CPU's fault status area
add %g1, %o0, %o0 ! o0 <= FSA of the current CPU
mov SCRATCHPAD_MMU_FSA, %g1
stxa %o0, [%g1] ASI_SCRATCHPAD ! remember MMU fault status area to speed up miss handler
__HYPERCALL_FAST(MMU_FAULT_AREA_CONF)
/*
* Store a template of a TTE Data entry for kernel mappings.
* This template will be used from the kernel MMU miss handler.
*/
!TTE_DATA(0, %l5, %g2, %g3, %g1)
setx TTE_FLAGS | PAGESIZE_8K, %g2, %g1; \
add %g1, %l5, %g1; \
set kernel_8k_tlb_data_template, %g4
stx %g1, [%g4]
 
/*
* So far, we have not touched the stack.
* It is a good idea to set the kernel stack to a known state now.
*/
263,14 → 233,3
.global physmem_base ! copy of the physical memory base address
physmem_base:
.quad 0
 
.global kernel_8k_tlb_data_template
kernel_8k_tlb_data_template:
.quad 0
 
/* MMU fault status areas for all CPUs */
.align MMU_FSA_ALIGNMENT
.global mmu_fsas
mmu_fsas:
!.space (MMU_FSA_SIZE * MAX_NUM_STRANDS)
.space 8192
/branches/sparc/kernel/arch/sparc64/src/mm/sun4v/tlb.c
74,12 → 74,37
};
#endif
 
/*
* Invalidate all non-locked DTLB and ITLB entries.
*/
mmu_fault_status_area_t mmu_fault_status_areas[MAX_NUM_STRANDS]
__attribute__ ((aligned (64)));
 
void tlb_arch_init(void)
{
uint64_t errno;
/*
* Invalidate all non-locked DTLB and ITLB entries.
*/
tlb_invalidate_all();
 
/*
* Set the MMU fault status area for the current CPU.
*/
uint64_t myid;
__hypercall_fast_ret1(0, 0, 0, 0, 0, CPU_MYID, &myid);
errno = __hypercall_fast1(MMU_FAULT_AREA_CONF,
KA2PA(&(mmu_fault_status_areas[myid])));
if (errno != EOK) {
panic("Could not set MMU fault area for CPU %d, errno = %d.\n",
myid, errno);
}
printf("Setting MMU fault area for CPU %d at %x.\n", myid, KA2PA(&(mmu_fault_status_areas[myid])));
#if 0
/*
* Clear both SFSRs.
*/
dtlb_sfsr_write(0);
itlb_sfsr_write(0);
#endif
}
 
/** Insert privileged mapping into DMMU TLB.
/branches/sparc/kernel/arch/sparc64/src/trap/sun4v/mmu.S
File deleted
/branches/sparc/kernel/arch/sparc64/src/trap/sun4v/trap_table.S
540,7 → 540,7
nop ! it will be easy to find
 
/* prevent unnecessary CLEANWIN exceptions */
wrpr %g0, NWINDOWS - 1, %cleanwin
wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(0), %wstate
1:
/*
* Prevent SAVE instruction from causing a spill exception. If the
/branches/sparc/kernel/arch/sparc64/src/trap/mmu.S
0,0 → 1,42
#
# Copyright (c) 2006 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
#
# - Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# - Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# - The name of the author may not be used to endorse or promote products
# derived from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
/**
* @file
* @brief MMU trap handlers that do not fit into the trap table.
*/
 
.register %g2, #scratch
.register %g3, #scratch
 
.text
 
#include <arch/trap/sun4u/mmu.h>
#include <arch/trap/trap_table.h>
#include <arch/sun4u/regdef.h>