Subversion Repositories HelenOS

Compare Revisions

Ignore whitespace Rev 114 → Rev 115

/SPARTAN/trunk/doc/requirements
1,45 → 1,47
ia32 port
=========
 
HARDWARE REQUIREMENTS
o IA-32 processor (Pentium and successors)
HARDWARE REQUIREMENTS
o IA-32 processor (Pentium and successors)
 
COMPILER REQUIREMENTS
o binutils 2.15
o gcc 2.95
o gcc 3.3.2 - gcc 3.3.5
COMPILER REQUIREMENTS
o binutils 2.15
o gcc 2.95
o gcc 3.3.2 - gcc 3.3.5
 
SMP COMPATIBILITY
o Bochs 2.0.2 - Bochs 2.2
o 2x-8x 686 CPU
o ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41
o 2x 200Mhz Pentium CPU
SMP COMPATIBILITY
o Bochs 2.0.2 - Bochs 2.2
o 2x-8x 686 CPU
o Simics 2.0.28
o 4x Pentium 4 CPU
o ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41
o 2x 200Mhz Pentium CPU
EMULATORS AND VIRTUALIZERS
o Bochs 2.0.2 - Bochs 2.2-cvs
o VMware Workstation 4, VMware Workstation 5
EMULATORS AND VIRTUALIZERS
o Bochs 2.0.2 - Bochs 2.2
o VMware Workstation 4, VMware Workstation 5
 
 
mips port
=========
 
HARDWARE REQUIREMENTS
o no real hardware supported
o msim emulated MIPS R4000 CPU (see mips)
HARDWARE REQUIREMENTS
o no real hardware supported
o msim emulated MIPS R4000 CPU (see mips)
 
COMPILER REQUIREMENTS
o binutils 2.14 mips cross binutils
o gcc 2.8.1 mips cross compiler
o gcc 3.2.3 mips cross compiler
COMPILER REQUIREMENTS
o binutils 2.14 mips cross binutils
o gcc 2.8.1 mips cross compiler
o gcc 3.2.3 mips cross compiler
 
EMULATORS AND VIRTUALIZERS
o msim
EMULATORS AND VIRTUALIZERS
o msim
 
ia64 port
=========
 
HARDWARE REQUIREMENTS
o no real hardware supported
HARDWARE REQUIREMENTS
o no real hardware supported
 
EMULATORS AND VIRTUALIZERS
o ski
EMULATORS AND VIRTUALIZERS
o ski
/SPARTAN/trunk/src/synch/semaphore.c
30,6 → 30,7
#include <synch/semaphore.h>
#include <synch/waitq.h>
#include <synch/spinlock.h>
#include <arch/asm.h>
 
void semaphore_initialize(semaphore_t *s, int val)
{
/SPARTAN/trunk/src/debug/print.c
30,6 → 30,7
#include <print.h>
#include <synch/spinlock.h>
#include <arch/arg.h>
#include <arch/asm.h>
 
 
static char digits[] = "0123456789abcdef"; /**< Hexadecimal characters */
/SPARTAN/trunk/src/proc/scheduler.c
131,7 → 131,7
continue;
}
/* avoid deadlock with relink_rq */
/* avoid deadlock with relink_rq() */
if (!spinlock_trylock(&CPU->lock)) {
/*
* Unlock r and try again.
446,7 → 446,6
cpu_t *cpu;
 
cpu = &cpus[(i + k) % config.cpu_active];
r = &cpu->rq[j];
 
/*
* Not interested in ourselves.
453,9 → 452,10
* Doesn't require interrupt disabling for kcpulb is X_WIRED.
*/
if (CPU == cpu)
continue;
continue;
 
restart: pri = cpu_priority_high();
r = &cpu->rq[j];
spinlock_lock(&r->lock);
if (r->n == 0) {
spinlock_unlock(&r->lock);
470,10 → 470,11
/*
* We don't want to steal CPU-wired threads neither threads already stolen.
* The latter prevents threads from migrating between CPU's without ever being run.
* We don't want to steal threads whose FPU context is still in CPU
* We don't want to steal threads whose FPU context is still in CPU.
*/
spinlock_lock(&t->lock);
if ( (!(t->flags & (X_WIRED | X_STOLEN))) && (!(t->fpu_context_engaged)) ) {
/*
* Remove t from r.
*/
/SPARTAN/trunk/src/proc/thread.c
176,7 → 176,7
frame_ks = frame_alloc(FRAME_KA);
if (THREAD_USER_STACK & flags) {
frame_us = frame_alloc(0);
frame_us = frame_alloc(FRAME_KA);
}
 
pri = cpu_priority_high();
/SPARTAN/trunk/src/mm/vm.c
38,6 → 38,7
#include <config.h>
#include <list.h>
#include <panic.h>
#include <arch/asm.h>
 
vm_t *vm_create(void)
{
/SPARTAN/trunk/src/mm/frame.c
42,6 → 42,8
 
#include <synch/spinlock.h>
 
#include <arch/asm.h>
 
count_t frames = 0;
count_t frames_free;
 
/SPARTAN/trunk/src/mm/heap.c
32,6 → 32,7
#include <memstr.h>
#include <panic.h>
#include <arch/types.h>
#include <arch/asm.h>
 
/*
* First-fit algorithm.
/SPARTAN/trunk/arch/ia32/include/atomic.h
31,10 → 31,36
 
#include <arch/types.h>
 
extern void atomic_inc(volatile int *val);
extern void atomic_dec(volatile int *val);
static inline void atomic_inc(volatile int *val) {
#ifdef __SMP__
__asm__ volatile ("lock incl (%0)\n" : : "r" (val));
#else
__asm__ volatile ("incl (%0)\n" : : "r" (val));
#endif /* __SMP__ */
}
 
extern int test_and_set(int *val);
static inline void atomic_dec(volatile int *val) {
#ifdef __SMP__
__asm__ volatile ("lock decl (%0)\n" : : "r" (val));
#else
__asm__ volatile ("decl (%0)\n" : : "r" (val));
#endif /* __SMP__ */
}
 
static inline int test_and_set(int *val) {
int v;
__asm__ volatile (
"movl $1, %0\n"
"xchgl %0, (%1)\n"
: "=r" (v)
: "r" (val)
);
return v;
}
 
 
extern void spinlock_arch(int *val);
 
#endif
/SPARTAN/trunk/arch/ia32/include/asm.h
37,11 → 37,7
extern __u32 interrupt_handler_size;
 
extern void paging_on(void);
extern __address cpu_read_dba(void);
extern void cpu_write_dba(__address dba);
 
extern __address cpu_read_cr2(void);
 
extern void interrupt_handlers(void);
 
extern __u8 inb(int port);
54,13 → 50,109
 
extern void enable_l_apic_in_msr(void);
 
extern void halt_cpu(void);
extern void cpu_sleep(void);
/** Halt CPU
*
* Halt the current CPU until interrupt event.
*/
static inline void cpu_halt(void) { __asm__("hlt"); };
static inline void cpu_sleep(void) { __asm__("hlt"); };
 
static inline void write_dr0(__u32 v);
static inline __u32 read_dr0(void);
/** Read CR2
*
* Return value in CR2
*
* @return Value read.
*/
static inline __u32 read_cr2(void) { __u32 v; __asm__ volatile ("movl %%cr2,%0" : "=r" (v)); return v; }
 
inline void write_dr0(__u32 v) { __asm__ volatile ("movl %0,%%dr0\n" : : "r" (v)); }
inline __u32 read_dr0(void) { __u32 v; __asm__ volatile ("movl %%dr0,%0" : "=r" (v)); return v; }
/** Write CR3
*
* Write value to CR3.
*
* @param v Value to be written.
*/
static inline void write_cr3(__u32 v) { __asm__ volatile ("movl %0,%%cr3\n" : : "r" (v)); }
 
/** Read CR3
*
* Return value in CR3
*
* @return Value read.
*/
static inline __u32 read_cr3(void) { __u32 v; __asm__ volatile ("movl %%cr3,%0" : "=r" (v)); return v; }
 
/** Write DR0
*
* Write value to DR0.
*
* @param v Value to be written.
*/
static inline void write_dr0(__u32 v) { __asm__ volatile ("movl %0,%%dr0\n" : : "r" (v)); }
 
/** Read DR0
*
* Return value in DR0
*
* @return Value read.
*/
static inline __u32 read_dr0(void) { __u32 v; __asm__ volatile ("movl %%dr0,%0" : "=r" (v)); return v; }
 
/** Set priority level low
*
* Enable interrupts and return previous
* value of EFLAGS.
*/
static inline pri_t cpu_priority_low(void) {
pri_t v;
__asm__ volatile (
"pushf\n"
"popl %0\n"
"sti\n"
: "=r" (v)
);
return v;
}
 
/** Set priority level high
*
* Disable interrupts and return previous
* value of EFLAGS.
*/
static inline pri_t cpu_priority_high(void) {
pri_t v;
__asm__ volatile (
"pushf\n"
"popl %0\n"
"cli\n"
: "=r" (v)
);
return v;
}
 
/** Restore priority level
*
* Restore EFLAGS.
*/
static inline void cpu_priority_restore(pri_t pri) {
__asm__ volatile (
"pushl %0\n"
"popf\n"
: : "r" (pri)
);
}
 
/** Return raw priority level
*
* Return EFLAFS.
*/
static inline pri_t cpu_priority_read(void) {
pri_t v;
__asm__ volatile (
"pushf\n"
"popl %0\n"
: "=r" (v)
);
return v;
}
 
#endif
/SPARTAN/trunk/arch/ia32/src/asm.s
30,16 → 30,9
 
.text
 
.global cpu_priority_high
.global cpu_priority_low
.global cpu_priority_restore
.global cpu_priority_read
.global cpu_halt
.global cpu_sleep
.global paging_on
.global cpu_read_dba
.global cpu_write_dba
.global cpu_read_cr2
.global enable_l_apic_in_msr
.global interrupt_handlers
.global inb
54,59 → 47,6
.global memcmp
 
 
## Set priority level high
#
# Disable interrupts and return previous
# EFLAGS in EAX.
#
cpu_priority_high:
pushf
pop %eax
cli
ret
 
 
## Set priority level low
#
# Enable interrupts and return previous
# EFLAGS in EAX.
#
cpu_priority_low:
pushf
pop %eax
sti
ret
 
 
## Restore priority level
#
# Restore EFLAGS.
#
cpu_priority_restore:
push 4(%esp)
popf
ret
 
## Return raw priority level
#
# Return EFLAFS in EAX.
#
cpu_priority_read:
pushf
pop %eax
ret
 
 
## Halt the CPU
#
# Halt the CPU using HLT.
#
cpu_halt:
cpu_sleep:
hlt
ret
 
 
## Turn paging on
#
# Enable paging and write-back caching in CR0.
123,36 → 63,6
ret
 
 
## Read CR3
#
# Store CR3 in EAX.
#
cpu_read_dba:
movl %cr3,%eax
ret
 
 
## Write CR3
#
# Set CR3.
#
cpu_write_dba:
pushl %eax
movl 8(%esp),%eax
movl %eax,%cr3
popl %eax
ret
 
 
## Read CR2
#
# Store CR2 in EAX.
#
cpu_read_cr2:
movl %cr2,%eax
ret
 
 
## Enable local APIC
#
# Enable local APIC in MSR.
/SPARTAN/trunk/arch/ia32/src/smp/apic.c
44,6 → 44,7
* Advanced Programmable Interrupt Controller for MP systems.
* Tested on:
* Bochs 2.0.2 - Bochs 2.2 with 2-8 CPUs
* Simics 2.0.28
* ASUS P/I-P65UP5 + ASUS C-P55T2D REV. 1.41 with 2x 200Mhz Pentium CPUs
*/
 
/SPARTAN/trunk/arch/ia32/src/mm/tlb.c
31,5 → 31,5
 
void tlb_invalidate(int asid)
{
cpu_write_dba(cpu_read_dba());
write_cr3(read_cr3());
}
/SPARTAN/trunk/arch/ia32/src/mm/page.c
69,7 → 69,7
}
 
trap_register(14, page_fault);
cpu_write_dba(KA2PA(dba));
write_cr3(KA2PA(dba));
}
else {
/*
81,7 → 81,7
 
dba = frame_alloc(FRAME_KA | FRAME_PANIC);
memcopy(bootstrap_dba, dba, PAGE_SIZE);
cpu_write_dba(KA2PA(dba));
write_cr3(KA2PA(dba));
}
 
paging_on();
107,7 → 107,7
int pde, pte;
 
if (root) dba = root;
else dba = cpu_read_dba();
else dba = read_cr3();
 
pde = page >> 22; /* page directory entry */
pte = (page >> 12) & 0x3ff; /* page table entry */
/SPARTAN/trunk/arch/ia32/src/interrupt.c
111,7 → 111,7
 
void page_fault(__u8 n, __u32 stack[])
{
printf("page fault address: %X\n", cpu_read_cr2());
printf("page fault address: %X\n", read_cr2());
printf("stack[0]=%X, %%eip=%X, %%cs=%X, flags=%X\n", stack[0], stack[1], stack[2], stack[3]);
printf("%%eax=%L, %%ebx=%L, %%ecx=%L, %%edx=%L,\n%%edi=%L, %%esi=%L, %%ebp=%L, %%esp=%L\n", stack[-2], stack[-5], stack[-3], stack[-4], stack[-9], stack[-8], stack[-1], stack);
printf("stack: %X, %X, %X, %X\n", stack[4], stack[5], stack[6], stack[7]);
/SPARTAN/trunk/arch/ia32/src/atomic.S
28,48 → 28,10
 
.text
 
.global atomic_inc
atomic_inc:
pushl %ebx
movl 8(%esp),%ebx
#ifdef __SMP__
lock incl (%ebx)
#else
incl (%ebx)
#endif
popl %ebx
ret
 
.global atomic_dec
atomic_dec:
pushl %ebx
movl 8(%esp),%ebx
#ifdef __SMP__
lock decl (%ebx)
#else
decl (%ebx)
#endif
popl %ebx
ret
 
#ifdef __SMP__
 
 
.global test_and_set
.global spinlock_arch
 
test_and_set:
pushl %ebx
movl 8(%esp),%ebx
movl $1,%eax
xchgl %eax,(%ebx) # xchg implicitly turns on the LOCK signal
popl %ebx
ret
 
 
#
# This is a bus-and-hyperthreading-friendly implementation of spinlock
#