/trunk/kernel/genarch/include/drivers/i8042/i8042.h |
---|
53,6 → 53,7 |
} i8042_instance_t; |
extern indev_t *i8042_init(i8042_t *, inr_t); |
extern void i8042_cpu_reset(i8042_t *); |
#endif |
/trunk/kernel/genarch/src/drivers/i8042/i8042.c |
---|
50,6 → 50,7 |
#define i8042_SET_COMMAND 0x60 |
#define i8042_COMMAND 0x69 |
#define i8042_CPU_RESET 0xfe |
#define i8042_BUFFER_FULL_MASK 0x01 |
#define i8042_WAIT_MASK 0x02 |
97,9 → 98,7 |
instance->irq.instance = instance; |
irq_register(&instance->irq); |
/* |
* Clear input buffer. |
*/ |
/* Clear input buffer */ |
while (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK) |
(void) pio_read_8(&dev->data); |
106,5 → 105,18 |
return &instance->kbrdin; |
} |
/* Reset CPU by pulsing pin 0 */ |
void i8042_cpu_reset(i8042_t *dev) |
{ |
interrupts_disable(); |
/* Clear input buffer */ |
while (pio_read_8(&dev->status) & i8042_BUFFER_FULL_MASK) |
(void) pio_read_8(&dev->data); |
/* Reset CPU */ |
pio_write_8(&dev->status, i8042_CPU_RESET); |
} |
/** @} |
*/ |
/trunk/kernel/arch/amd64/src/amd64.c |
---|
281,5 → 281,12 |
return addr; |
} |
void arch_reboot(void) |
{ |
#ifdef CONFIG_PC_KBD |
i8042_cpu_reset((i8042_t *) I8042_BASE); |
#endif |
} |
/** @} |
*/ |
/trunk/kernel/arch/amd64/src/pm.c |
---|
230,24 → 230,5 |
tr_load(gdtselector(TSS_DES)); |
} |
/* Reboot the machine by initiating |
* a triple fault |
*/ |
void arch_reboot(void) |
{ |
preemption_disable(); |
ipl_t ipl = interrupts_disable(); |
memsetb(idt, sizeof(idt), 0); |
idtr_load(&idtr); |
interrupts_restore(ipl); |
asm volatile ( |
"int $0x03\n" |
"cli\n" |
"hlt\n" |
); |
} |
/** @} |
*/ |
/trunk/kernel/arch/ia32/src/ia32.c |
---|
237,5 → 237,12 |
return addr; |
} |
void arch_reboot(void) |
{ |
#ifdef CONFIG_PC_KBD |
i8042_cpu_reset((i8042_t *) I8042_BASE); |
#endif |
} |
/** @} |
*/ |
/trunk/kernel/arch/ia32/src/pm.c |
---|
232,28 → 232,5 |
gdtr_load(&cpugdtr); |
} |
/* Reboot the machine by initiating |
* a triple fault |
*/ |
void arch_reboot(void) |
{ |
preemption_disable(); |
ipl_t ipl = interrupts_disable(); |
memsetb(idt, sizeof(idt), 0); |
ptr_16_32_t idtr; |
idtr.limit = sizeof(idt); |
idtr.base = (uintptr_t) idt; |
idtr_load(&idtr); |
interrupts_restore(ipl); |
asm volatile ( |
"int $0x03\n" |
"cli\n" |
"hlt\n" |
); |
} |
/** @} |
*/ |