| /trunk/kernel/genarch/include/drivers/ega/ega.h |
|---|
| 46,7 → 46,7 |
| #define EGA_DATA_REG 1 |
| extern void ega_redraw(void); |
| extern void ega_init(ioport_t, uintptr_t); |
| extern void ega_init(ioport8_t *, uintptr_t); |
| #endif |
| /trunk/kernel/genarch/src/drivers/ega/ega.c |
|---|
| 58,7 → 58,7 |
| static uint32_t ega_cursor; |
| static uint8_t *videoram; |
| static uint8_t *backbuf; |
| static ioport_t ega_base; |
| static ioport8_t *ega_base; |
| chardev_t ega_console; |
| 131,7 → 131,7 |
| .write = ega_putchar |
| }; |
| void ega_init(ioport_t base, uintptr_t videoram_phys) |
| void ega_init(ioport8_t *base, uintptr_t videoram_phys) |
| { |
| /* Initialize the software structure. */ |
| ega_base = base; |
| /trunk/kernel/generic/src/ipc/irq.c |
|---|
| 101,10 → 101,10 |
| code->cmds[i].value; |
| break; |
| case CMD_PORT_READ_1: |
| dstval = pio_read_8((long) code->cmds[i].addr); |
| dstval = pio_read_8((ioport8_t *) code->cmds[i].addr); |
| break; |
| case CMD_PORT_WRITE_1: |
| pio_write_8((long) code->cmds[i].addr, code->cmds[i].value); |
| pio_write_8((ioport8_t *) code->cmds[i].addr, code->cmds[i].value); |
| break; |
| default: |
| break; |
| /trunk/kernel/arch/ia64/include/drivers/ega.h |
|---|
| 36,7 → 36,7 |
| #define KERN_ia64_EGA_H |
| #define EGA_VIDEORAM 0xb8000 |
| #define EGA_BASE 0x3d4 |
| #define EGA_BASE ((ioport8_t *)0x3d4) |
| #endif |
| /trunk/kernel/arch/ia32/include/drivers/ega.h |
|---|
| 36,7 → 36,7 |
| #define KERN_ia32_EGA_H |
| #define EGA_VIDEORAM 0xb8000 |
| #define EGA_BASE 0x3d4 |
| #define EGA_BASE ((ioport8_t *)0x3d4) |
| #endif |
| /trunk/kernel/arch/ia32/include/drivers/i8259.h |
|---|
| 38,10 → 38,10 |
| #include <arch/types.h> |
| #include <arch/interrupt.h> |
| #define PIC_PIC0PORT1 0x20 |
| #define PIC_PIC0PORT2 0x21 |
| #define PIC_PIC1PORT1 0xa0 |
| #define PIC_PIC1PORT2 0xa1 |
| #define PIC_PIC0PORT1 ((ioport8_t *) 0x20) |
| #define PIC_PIC0PORT2 ((ioport8_t *) 0x21) |
| #define PIC_PIC1PORT1 ((ioport8_t *) 0xa0) |
| #define PIC_PIC1PORT2 ((ioport8_t *) 0xa1) |
| #define PIC_NEEDICW4 (1<<0) |
| #define PIC_ICW1 (1<<4) |
| /trunk/kernel/arch/ia32/src/smp/smp.c |
|---|
| 122,8 → 122,8 |
| * Save 0xa to address 0xf of the CMOS RAM. |
| * BIOS will not do the POST after the INIT signal. |
| */ |
| pio_write_8(0x70, 0xf); |
| pio_write_8(0x71, 0xa); |
| pio_write_8((ioport8_t *)0x70, 0xf); |
| pio_write_8((ioport8_t *)0x71, 0xa); |
| pic_disable_irqs(0xffff); |
| apic_init(); |
| /trunk/kernel/arch/ia32/src/drivers/i8259.c |
|---|
| 119,8 → 119,8 |
| void pic_eoi(void) |
| { |
| pio_write_8(0x20, 0x20); |
| pio_write_8(0xa0, 0x20); |
| pio_write_8((ioport8_t *)0x20, 0x20); |
| pio_write_8((ioport8_t *)0xa0, 0x20); |
| } |
| void pic_spurious(int n __attribute__((unused)), istate_t *istate __attribute__((unused))) |
| /trunk/kernel/arch/ia32/src/drivers/i8254.c |
|---|
| 53,8 → 53,8 |
| #include <ddi/irq.h> |
| #include <ddi/device.h> |
| #define CLK_PORT1 0x40 |
| #define CLK_PORT4 0x43 |
| #define CLK_PORT1 ((ioport8_t *)0x40) |
| #define CLK_PORT4 ((ioport8_t *)0x43) |
| #define CLK_CONST 1193180 |
| #define MAGIC_NUMBER 1194 |