/trunk/kernel/generic/include/align.h |
---|
26,16 → 26,17 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup generic |
* @ingroup others |
* @{ |
*/ |
/** @file |
/** |
* @file |
* @brief Macros for making values and addresses aligned. |
*/ |
#ifndef __ALIGN_H__ |
#define __ALIGN_H__ |
#ifndef KERN_ALIGN_H_ |
#define KERN_ALIGN_H_ |
/** Align to the nearest lower address. |
* |
/trunk/kernel/arch/sparc64/include/interrupt.h |
---|
33,11 → 33,12 |
/** @file |
*/ |
#ifndef __sparc64_INTERRUPT_H__ |
#define __sparc64_INTERRUPT_H__ |
#ifndef KERN_sparc64_INTERRUPT_H_ |
#define KERN_sparc64_INTERRUPT_H_ |
#include <typedefs.h> |
#include <arch/types.h> |
#include <arch/regdef.h> |
#define IRQ_COUNT 1 /* TODO */ |
52,17 → 53,17 |
static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr) |
{ |
/* TODO */ |
istate->tpc = retaddr; |
} |
static inline int istate_from_uspace(istate_t *istate) |
{ |
/* TODO */ |
return 0; |
return !(istate->tstate & TSTATE_PRIV_BIT); |
} |
static inline unative_t istate_get_pc(istate_t *istate) |
{ |
/* TODO */ |
return 0; |
return istate->tpc; |
} |
/trunk/kernel/arch/sparc64/include/regdef.h |
---|
46,6 → 46,7 |
#define TSTATE_PSTATE_SHIFT 8 |
#define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT<<TSTATE_PSTATE_SHIFT) |
#define TSTATE_IE_BIT (PSTATE_IE_BIT<<TSTATE_PSTATE_SHIFT) |
#define TSTATE_CWP_MASK 0x1f |
/trunk/kernel/arch/sparc64/include/fpu_context.h |
---|
26,14 → 26,14 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64 |
/** @addtogroup sparc64 |
* @{ |
*/ |
/** @file |
*/ |
#ifndef __sparc64_FPU_CONTEXT_H__ |
#define __sparc64_FPU_CONTEXT_H__ |
#ifndef KERN_sparc64_FPU_CONTEXT_H_ |
#define KERN_sparc64_FPU_CONTEXT_H_ |
#include <arch/types.h> |
42,6 → 42,5 |
#endif |
/** @} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/include/byteorder.h |
---|
26,14 → 26,14 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64 |
/** @addtogroup sparc64 |
* @{ |
*/ |
/** @file |
*/ |
#ifndef __sparc64_BYTEORDER_H__ |
#define __sparc64_BYTEORDER_H__ |
#ifndef KERN_sparc64_BYTEORDER_H_ |
#define KERN_sparc64_BYTEORDER_H_ |
#include <arch/types.h> |
#include <byteorder.h> |
50,6 → 50,5 |
#endif |
/** @} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/include/console.h |
---|
36,7 → 36,6 |
#define KERN_sparc64_CONSOLE_H_ |
extern void kkbdpoll(void *arg); |
extern void ofw_sparc64_console_init(void); |
extern void standalone_sparc64_console_init(void); |
#endif |
/trunk/kernel/arch/sparc64/include/types.h |
---|
26,14 → 26,14 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64 |
/** @addtogroup sparc64 |
* @{ |
*/ |
/** @file |
*/ |
#ifndef __sparc64_TYPES_H__ |
#define __sparc64_TYPES_H__ |
#ifndef KERN_sparc64_TYPES_H_ |
#define KERN_sparc64_TYPES_H_ |
#define NULL 0 |
61,6 → 61,5 |
#endif |
/** @} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/include/elf.h |
---|
32,8 → 32,8 |
/** @file |
*/ |
#ifndef __sparc64_ELF_H__ |
#define __sparc64_ELF_H__ |
#ifndef KERN_sparc64_ELF_H_ |
#define KERN_sparc64_ELF_H_ |
#define ELF_MACHINE EM_SPARCV9 |
#define ELF_DATA_ENCODING ELFDATA2MSB |
/trunk/kernel/arch/sparc64/include/memstr.h |
---|
26,14 → 26,14 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64 |
/** @addtogroup sparc64 |
* @{ |
*/ |
/** @file |
*/ |
#ifndef __sparc64_MEMSTR_H__ |
#define __sparc64_MEMSTR_H__ |
#ifndef KERN_sparc64_MEMSTR_H_ |
#define KERN_sparc64_MEMSTR_H_ |
#define memcpy(dst, src, cnt) __builtin_memcpy((dst), (src), (cnt)) |
44,6 → 44,5 |
#endif |
/** @} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/include/arg.h |
---|
26,19 → 26,18 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64 |
/** @addtogroup sparc64 |
* @{ |
*/ |
/** @file |
*/ |
#ifndef __sparc64_ARG_H__ |
#define __sparc64_ARG_H__ |
#ifndef KERN_sparc64_ARG_H_ |
#define KERN_sparc64_ARG_H_ |
#include <stdarg.h> |
#endif |
/** @} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/include/atomic.h |
---|
32,8 → 32,8 |
/** @file |
*/ |
#ifndef __sparc64_ATOMIC_H__ |
#define __sparc64_ATOMIC_H__ |
#ifndef KERN_sparc64_ATOMIC_H_ |
#define KERN_sparc64_ATOMIC_H_ |
#include <arch/types.h> |
#include <typedefs.h> |
/trunk/kernel/arch/sparc64/include/arch.h |
---|
34,8 → 34,8 |
* @brief Various sparc64-specific macros. |
*/ |
#ifndef __sparc64_ARCH_H__ |
#define __sparc64_ARCH_H__ |
#ifndef KERN_sparc64_ARCH_H_ |
#define KERN_sparc64_ARCH_H_ |
#define ASI_AIUP 0x10 /** Access to primary context with user privileges. */ |
#define ASI_AIUS 0x11 /** Access to secondary context with user privileges. */ |
/trunk/kernel/arch/sparc64/include/proc/task.h |
---|
26,14 → 26,14 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64proc |
/** @addtogroup sparc64proc |
* @{ |
*/ |
/** @file |
*/ |
#ifndef __sparc64_TASK_H__ |
#define __sparc64_TASK_H__ |
#ifndef KERN_sparc64_TASK_H_ |
#define KERN_sparc64_TASK_H_ |
typedef struct { |
} task_arch_t; |
43,6 → 43,5 |
#endif |
/** @} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/include/faddr.h |
---|
26,14 → 26,14 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64 |
/** @addtogroup sparc64 |
* @{ |
*/ |
/** @file |
*/ |
#ifndef __sparc64_FADDR_H__ |
#define __sparc64_FADDR_H__ |
#ifndef KERN_sparc64_FADDR_H_ |
#define KERN_sparc64_FADDR_H_ |
#include <arch/types.h> |
41,6 → 41,5 |
#endif |
/** @} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/include/asm.h |
---|
330,6 → 330,8 |
extern void write_to_ag_g7(uint64_t val); |
extern void write_to_ig_g6(uint64_t val); |
extern void switch_to_userspace(uint64_t pc, uint64_t sp); |
#endif |
/** @} |
/trunk/kernel/arch/sparc64/include/trap/regwin.h |
---|
34,8 → 34,8 |
* @brief This file contains register window trap handlers. |
*/ |
#ifndef __sparc64_REGWIN_H__ |
#define __sparc64_REGWIN_H__ |
#ifndef KERN_sparc64_REGWIN_H_ |
#define KERN_sparc64_REGWIN_H_ |
#include <arch/stack.h> |
#include <arch/arch.h> |
/trunk/kernel/arch/sparc64/include/trap/interrupt.h |
---|
34,8 → 34,8 |
* @brief This file contains interrupt vector trap handler. |
*/ |
#ifndef __sparc64_TRAP_INTERRUPT_H__ |
#define __sparc64_TRAP_INTERRUPT_H__ |
#ifndef KERN_sparc64_TRAP_INTERRUPT_H_ |
#define KERN_sparc64_TRAP_INTERRUPT_H_ |
#include <arch/trap/trap_table.h> |
#include <arch/stack.h> |
/trunk/kernel/arch/sparc64/include/trap/trap_table.h |
---|
32,13 → 32,9 |
/** @file |
*/ |
#ifndef __sparc64_TRAP_TABLE_H__ |
#define __sparc64_TRAP_TABLE_H__ |
#ifndef KERN_sparc64_TRAP_TABLE_H_ |
#define KERN_sparc64_TRAP_TABLE_H_ |
#ifndef __ASM__ |
#include <arch/types.h> |
#endif /* __ASM__ */ |
#include <arch/stack.h> |
#define TRAP_TABLE_ENTRY_COUNT 1024 |
46,6 → 42,9 |
#define TRAP_TABLE_SIZE (TRAP_TABLE_ENTRY_COUNT*TRAP_TABLE_ENTRY_SIZE) |
#ifndef __ASM__ |
#include <arch/types.h> |
struct trap_table_entry { |
uint8_t octets[TRAP_TABLE_ENTRY_SIZE]; |
} __attribute__ ((packed)); |
/trunk/kernel/arch/sparc64/include/trap/exception.h |
---|
33,8 → 33,8 |
* @file |
*/ |
#ifndef __sparc64_EXCEPTION_H__ |
#define __sparc64_EXCEPTION_H__ |
#ifndef KERN_sparc64_EXCEPTION_H_ |
#define KERN_sparc64_EXCEPTION_H_ |
#define TT_INSTRUCTION_ACCESS_EXCEPTION 0x08 |
#define TT_ILLEGAL_INSTRUCTION 0x10 |
/trunk/kernel/arch/sparc64/include/trap/mmu.h |
---|
42,6 → 42,7 |
#include <arch/mm/tlb.h> |
#include <arch/mm/mmu.h> |
#include <arch/mm/tte.h> |
#include <arch/trap/regwin.h> |
#define TT_FAST_INSTRUCTION_ACCESS_MMU_MISS 0x64 |
#define TT_FAST_DATA_ACCESS_MMU_MISS 0x68 |
50,10 → 51,11 |
#define FAST_MMU_HANDLER_SIZE 128 |
#ifdef __ASM__ |
.macro FAST_INSTRUCTION_ACCESS_MMU_MISS_HANDLER |
/* |
* First, try to refill TLB from TSB. |
*/ |
! |
! First, try to refill TLB from TSB. |
! |
! TODO |
wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
74,7 → 76,7 |
* |
* Note that branch-delay slots are used in order to save space. |
*/ |
0: |
mov VA_DMMU_TAG_ACCESS, %g1 |
ldxa [%g1] ASI_DMMU, %g1 ! read the faulting Context and VPN |
set TLB_TAG_ACCESS_CONTEXT_MASK, %g2 |
84,28 → 86,61 |
bz 0f ! page address is zero |
or %g3, (TTE_CP|TTE_P|TTE_W), %g2 ! 8K pages are the default (encoded as 0) |
set 1, %g3 |
sllx %g3, TTE_V_SHIFT, %g3 |
or %g2, %g3, %g2 |
mov 1, %g3 |
sllx %g3, TTE_V_SHIFT, %g3 |
or %g2, %g3, %g2 |
stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG ! identity map the kernel page |
retry |
/* |
* Third, catch and handle special cases when the trap is caused by |
* some register window trap handler. |
* the userspace register window spill or fill handler. In case |
* one of these two traps caused this trap, we just lower the trap |
* level and service the DTLB miss. In the end, we restart |
* the offending SAVE or RESTORE. |
*/ |
0: |
! TODO |
HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL |
0: |
wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
PREEMPTIBLE_HANDLER fast_data_access_mmu_miss |
.endm |
.macro FAST_DATA_ACCESS_PROTECTION_HANDLER |
/* |
* First, try to refill TLB from TSB. |
*/ |
! TODO |
/* |
* The same special case as in FAST_DATA_ACCESS_MMU_MISS_HANDLER. |
*/ |
HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL |
wrpr %g0, PSTATE_PRIV_BIT | PSTATE_AG_BIT, %pstate |
PREEMPTIBLE_HANDLER fast_data_access_protection |
.endm |
/* |
* Macro used to lower TL when a MMU trap is caused by |
* the userspace register window spill or fill handler. |
*/ |
.macro HANDLE_MMU_TRAPS_FROM_SPILL_OR_FILL |
rdpr %tl, %g1 |
dec %g1 |
brz %g1, 0f ! if TL was 1, skip |
nop |
wrpr %g1, 0, %tl ! TL-- |
rdpr %tt, %g2 |
cmp %g2, TT_SPILL_1_NORMAL |
be 0f ! trap from spill_1_normal |
cmp %g2, TT_FILL_1_NORMAL |
be 0f ! trap from fill_1_normal |
inc %g1 |
wrpr %g1, 0, %tl ! another trap, TL++ |
0: |
.endm |
#endif /* __ASM__ */ |
#endif |
/trunk/kernel/arch/sparc64/include/trap/trap.h |
---|
32,8 → 32,8 |
/** @file |
*/ |
#ifndef __sparc64_TRAP_H__ |
#define __sparc64_TRAP_H__ |
#ifndef KERN_sparc64_TRAP_H_ |
#define KERN_sparc64_TRAP_H_ |
extern void trap_init(void); |
/trunk/kernel/arch/sparc64/include/mm/frame.h |
---|
47,8 → 47,8 |
uintptr_t address; |
struct { |
unsigned : 23; |
uint64_t pfn : 28; /**< Physical Frame Number. */ |
unsigned offset : 13; /**< Offset. */ |
uint64_t pfn : 28; /**< Physical Frame Number. */ |
unsigned offset : 13; /**< Offset. */ |
} __attribute__ ((packed)); |
}; |
/trunk/kernel/arch/sparc64/include/mm/memory_init.h |
---|
26,14 → 26,14 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef __sparc64_MEMORY_INIT_H__ |
#define __sparc64_MEMORY_INIT_H__ |
#ifndef KERN_sparc64_MEMORY_INIT_H_ |
#define KERN_sparc64_MEMORY_INIT_H_ |
#include <typedefs.h> |
41,6 → 41,5 |
#endif |
/** @} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/include/mm/tte.h |
---|
32,8 → 32,8 |
/** @file |
*/ |
#ifndef __sparc64_TTE_H__ |
#define __sparc64_TTE_H__ |
#ifndef KERN_sparc64_TTE_H_ |
#define KERN_sparc64_TTE_H_ |
#define TTE_G (1<<0) |
#define TTE_W (1<<1) |
/trunk/kernel/arch/sparc64/include/mm/mmu.h |
---|
32,8 → 32,8 |
/** @file |
*/ |
#ifndef __sparc64_MMU_H__ |
#define __sparc64_MMU_H__ |
#ifndef KERN_sparc64_MMU_H_ |
#define KERN_sparc64_MMU_H_ |
/* LSU Control Register ASI. */ |
#define ASI_LSU_CONTROL_REG 0x45 /**< Load/Store Unit Control Register. */ |
/trunk/kernel/arch/sparc64/include/mm/tlb.h |
---|
32,10 → 32,9 |
/** @file |
*/ |
#ifndef __sparc64_TLB_H__ |
#define __sparc64_TLB_H__ |
#ifndef KERN_sparc64_TLB_H_ |
#define KERN_sparc64_TLB_H_ |
#define ITLB_ENTRY_COUNT 64 |
#define DTLB_ENTRY_COUNT 64 |
/trunk/kernel/arch/sparc64/include/mm/as.h |
---|
26,14 → 26,14 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
*/ |
#ifndef __sparc64_AS_H__ |
#define __sparc64_AS_H__ |
#ifndef KERN_sparc64_AS_H_ |
#define KERN_sparc64_AS_H_ |
#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH 1 |
44,12 → 44,10 |
#define USTACK_ADDRESS_ARCH (0x7fffffffffffffff-(PAGE_SIZE-1)) |
#define as_install_arch(as) |
extern void as_arch_init(void); |
#endif |
/** @} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/include/context.h |
---|
32,18 → 32,18 |
/** @file |
*/ |
#ifndef __sparc64_CONTEXT_H__ |
#define __sparc64_CONTEXT_H__ |
#ifndef KERN_sparc64_CONTEXT_H_ |
#define KERN_sparc64_CONTEXT_H_ |
#ifndef __sparc64_STACK_H__ |
#ifndef KERN_sparc64_STACK_H_ |
# include <arch/stack.h> |
#endif |
#ifndef __sparc64_TYPES_H__ |
#ifndef KERN_sparc64_TYPES_H_ |
# include <arch/types.h> |
#endif |
#ifndef __ALIGN_H__ |
#ifndef KERN_ALIGN_H_ |
# include <align.h> |
#endif |
/trunk/kernel/arch/sparc64/include/debug.h |
---|
26,17 → 26,16 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64debug |
/** @addtogroup sparc64debug |
* @{ |
*/ |
/** @file |
*/ |
#ifndef __sparc64_DEBUG_H__ |
#define __sparc64_DEBUG_H__ |
#ifndef KERN_sparc64_DEBUG_H_ |
#define KERN_sparc64_DEBUG_H_ |
#endif |
/** @} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/include/barrier.h |
---|
32,8 → 32,8 |
/** @file |
*/ |
#ifndef __sparc64_BARRIER_H__ |
#define __sparc64_BARRIER_H__ |
#ifndef KERN_sparc64_BARRIER_H_ |
#define KERN_sparc64_BARRIER_H_ |
/* |
* TODO: Implement true SPARC V9 memory barriers for macros below. |
/trunk/kernel/arch/sparc64/include/cpu.h |
---|
32,8 → 32,8 |
/** @file |
*/ |
#ifndef __sparc64_CPU_H__ |
#define __sparc64_CPU_H__ |
#ifndef KERN_sparc64_CPU_H_ |
#define KERN_sparc64_CPU_H_ |
#include <arch/register.h> |
/trunk/kernel/arch/sparc64/include/drivers/tick.h |
---|
32,8 → 32,8 |
/** @file |
*/ |
#ifndef __sparc64_TICK_H__ |
#define __sparc64_TICK_H__ |
#ifndef KERN_sparc64_TICK_H_ |
#define KERN_sparc64_TICK_H_ |
#include <typedefs.h> |
/trunk/kernel/arch/sparc64/src/ddi/ddi.c |
---|
26,7 → 26,7 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64ddi |
/** @addtogroup sparc64ddi |
* @{ |
*/ |
/** @file |
52,6 → 52,5 |
return 0; |
} |
/** @} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/src/asm.S |
---|
28,6 → 28,7 |
#include <arch/stack.h> |
#include <arch/regdef.h> |
#include <arch/mm/mmu.h> |
.text |
143,3 → 144,39 |
.global read_from_ag_g7 |
read_from_ag_g7: |
READ_ALTERNATE_REGISTER %g7, PSTATE_AG_BIT |
/** Switch to userspace. |
* |
* %o0 Userspace entry address. |
* %o1 Userspace stack pointer address. |
*/ |
.global switch_to_userspace |
switch_to_userspace: |
flushw |
wrpr %g0, 0, %cleanwin ! avoid information leak |
save %o1, -STACK_WINDOW_SAVE_AREA_SIZE, %sp |
clr %i2 |
clr %i3 |
clr %i4 |
clr %i5 |
clr %i6 |
wrpr %g0, 1, %tl ! enforce mapping via nucleus |
rdpr %cwp, %g1 |
wrpr %g1, TSTATE_IE_BIT, %tstate |
wrpr %i0, 0, %tnpc |
/* |
* Set primary context according to secondary context. |
* Secondary context has been already installed by |
* higher-level functions. |
*/ |
wr %g0, ASI_DMMU, %asi |
ldxa [VA_SECONDARY_CONTEXT_REG] %asi, %g1 |
stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi |
flush %i7 |
done ! jump to userspace |
/trunk/kernel/arch/sparc64/src/proc/scheduler.c |
---|
91,8 → 91,10 |
* Write kernel stack address to %g6 and a pointer to the last item |
* in the userspace window buffer to %g7 in the alternate and interrupt sets. |
*/ |
write_to_ig_g6((uintptr_t) THREAD->kstack + STACK_SIZE - STACK_BIAS); |
write_to_ag_g6((uintptr_t) THREAD->kstack + STACK_SIZE - STACK_BIAS); |
uint64_t sp = (uintptr_t) THREAD->kstack + STACK_SIZE |
- (STACK_BIAS + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT)); |
write_to_ig_g6(sp); |
write_to_ag_g6(sp); |
write_to_ag_g7((uintptr_t) THREAD->arch.uspace_window_buffer); |
} |
} |
/trunk/kernel/arch/sparc64/src/sparc64.c |
---|
34,6 → 34,7 |
#include <arch.h> |
#include <debug.h> |
#include <config.h> |
#include <arch/trap/trap.h> |
#include <arch/console.h> |
#include <arch/drivers/tick.h> |
41,8 → 42,9 |
#include <console/console.h> |
#include <arch/boot/boot.h> |
#include <arch/arch.h> |
#include <arch/mm/tlb.h> |
#include <mm/asid.h> |
#include <arch/mm/page.h> |
#include <arch/stack.h> |
#include <userspace.h> |
bootinfo_t bootinfo; |
91,5 → 93,17 |
{ |
} |
/** Switch to userspace. */ |
void userspace(uspace_arg_t *kernel_uarg) |
{ |
switch_to_userspace((uintptr_t) kernel_uarg->uspace_entry, |
((uintptr_t) kernel_uarg->uspace_stack) + STACK_SIZE |
- (ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT) + STACK_BIAS)); |
for (;;) |
; |
/* not reached */ |
} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/src/trap/trap_table.S |
---|
40,6 → 40,7 |
#include <arch/trap/interrupt.h> |
#include <arch/trap/exception.h> |
#include <arch/trap/mmu.h> |
#include <arch/mm/mmu.h> |
#include <arch/mm/page.h> |
#include <arch/stack.h> |
#include <arch/regdef.h> |
348,15 → 349,15 |
rdpr %cansave, %l0 |
wrpr %l0, %otherwin |
wrpr %g0, %cansave |
wrpr %g0, NWINDOW-1, %cleanwin |
wrpr %g0, NWINDOW - 1, %cleanwin |
/* |
* Switch to primary context 0. |
*/ |
mov VA_PRIMARY_CONTEXT_REG, %l0 |
stxa %g0, [%l0] ASI_DMMU |
set kernel_image_start, %l0 |
flush %l0 |
stxa %g0, [%l0] ASI_DMMU |
rd %pc, %l0 |
flush %l0 |
ba 1f |
nop |
497,6 → 498,14 |
* handlers. |
*/ |
wrpr %g0, WSTATE_OTHER(0) | WSTATE_NORMAL(1), %wstate |
/* |
* Set primary context according to secondary context. |
*/ |
wr %g0, ASI_DMMU, %asi |
ldxa [VA_SECONDARY_CONTEXT_REG] %asi, %g1 |
stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi |
flush %o7 |
rdpr %cwp, %g1 |
rdpr %otherwin, %g2 |
/trunk/kernel/arch/sparc64/src/mm/tlb.c |
---|
374,9 → 374,16 |
*/ |
void tlb_invalidate_asid(asid_t asid) |
{ |
/* TODO: write asid to some Context register and encode the register in second parameter below. */ |
itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0); |
tlb_context_reg_t sc_save, ctx; |
ctx.v = sc_save.v = mmu_secondary_context_read(); |
ctx.context = asid; |
mmu_secondary_context_write(ctx.v); |
itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_SECONDARY, 0); |
dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_SECONDARY, 0); |
mmu_secondary_context_write(sc_save.v); |
} |
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space. |
388,12 → 395,18 |
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt) |
{ |
int i; |
tlb_context_reg_t sc_save, ctx; |
ctx.v = sc_save.v = mmu_secondary_context_read(); |
ctx.context = asid; |
mmu_secondary_context_write(ctx.v); |
for (i = 0; i < cnt; i++) { |
/* TODO: write asid to some Context register and encode the register in second parameter below. */ |
itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE); |
itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, page + i * PAGE_SIZE); |
dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, page + i * PAGE_SIZE); |
} |
mmu_secondary_context_write(sc_save.v); |
} |
/** @} |
/trunk/kernel/arch/sparc64/src/mm/as.c |
---|
26,7 → 26,7 |
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
*/ |
/** @addtogroup sparc64mm |
/** @addtogroup sparc64mm |
* @{ |
*/ |
/** @file |
33,6 → 33,7 |
*/ |
#include <arch/mm/as.h> |
#include <arch/mm/tlb.h> |
#include <genarch/mm/as_ht.h> |
#include <genarch/mm/asid_fifo.h> |
43,6 → 44,22 |
asid_fifo_init(); |
} |
/** @} |
void as_install_arch(as_t *as) |
{ |
tlb_context_reg_t ctx; |
/* |
* Write ASID to secondary context register. |
* The primary context register has to be set |
* from TL>0 so it will be filled from the |
* secondary context register from the TL=1 |
* code just before switch to userspace. |
*/ |
ctx.v = 0; |
ctx.context = as->asid; |
mmu_secondary_context_write(ctx.v); |
} |
/** @} |
*/ |
/trunk/kernel/arch/sparc64/src/dummy.s |
---|
39,7 → 39,6 |
.global fpu_context_save |
.global fpu_enable |
.global fpu_init |
.global userspace |
.global sys_tls_set |
.global dummy |
55,7 → 54,6 |
fpu_context_save: |
fpu_enable: |
fpu_init: |
userspace: |
sys_tls_set: |
dummy: |
/trunk/kernel/arch/sparc64/src/start.S |
---|
68,7 → 68,7 |
and %g1, ~(PSTATE_AM_BIT|PSTATE_IE_BIT), %g1 |
wrpr %g1, 0, %pstate |
wrpr %r0, 0, %pil ! intialize %pil |
wrpr %g0, 0, %pil ! intialize %pil |
/* |
* Copy the bootinfo structure passed from the boot loader |