| 58,6 → 58,7 |
|---|
| #define IIR_REG 2 /** Interrupt Ident Register (read). */ |
| #define FCR_REG 2 /** FIFO control register (write). */ |
| #define LCR_REG 3 /** Line Control register. */ |
| #define MCR_REG 4 /** Modem Control Register. */ |
| #define LSR_REG 5 /** Line Status Register. */ |
| |
| #define IER_ERBFI 0x01 /** Enable Receive Buffer Full Interrupt. */ |
| 64,10 → 65,13 |
|---|
| |
| #define LCR_DLAB 0x80 /** Divisor Latch Access bit. */ |
| |
| #define MCR_OUT2 0x08 /** OUT2. */ |
| |
| /** Structure representing the ns16550 device. */ |
| typedef struct { |
| devno_t devno; |
| volatile ioport_t io_port; /** Memory mapped registers of the ns16550. */ |
| /** Memory mapped registers of the ns16550. */ |
| volatile ioport_t io_port; |
| } ns16550_t; |
| |
| static inline uint8_t ns16550_rbr_read(ns16550_t *dev) |
| 114,7 → 118,15 |
|---|
| return inb(dev->io_port+LSR_REG); |
| } |
| |
| static inline uint8_t ns16550_mcr_read(ns16550_t *dev) |
| { |
| return inb(dev->io_port + MCR_REG); |
| } |
| |
| static inline void ns16550_mcr_write(ns16550_t *dev, uint8_t v) |
| { |
| outb(dev->io_port + MCR_REG, v); |
| } |
| |
| #endif |
| |