/trunk/kernel/arch/sparc64/include/asm.h |
---|
44,25 → 44,25 |
#include <arch/stack.h> |
#include <arch/barrier.h> |
static inline void outb(ioport_t port, uint8_t v) |
static inline void pio_write_8(ioport_t port, uint8_t v) |
{ |
*((volatile uint8_t *)(port)) = v; |
memory_barrier(); |
} |
static inline void outw(ioport_t port, uint16_t v) |
static inline void pio_write_16(ioport_t port, uint16_t v) |
{ |
*((volatile uint16_t *)(port)) = v; |
memory_barrier(); |
} |
static inline void outl(ioport_t port, uint32_t v) |
static inline void pio_write_32(ioport_t port, uint32_t v) |
{ |
*((volatile uint32_t *)(port)) = v; |
memory_barrier(); |
} |
static inline uint8_t inb(ioport_t port) |
static inline uint8_t pio_read_8(ioport_t port) |
{ |
uint8_t rv; |
72,7 → 72,7 |
return rv; |
} |
static inline uint16_t inw(ioport_t port) |
static inline uint16_t pio_read_16(ioport_t port) |
{ |
uint16_t rv; |
82,7 → 82,7 |
return rv; |
} |
static inline uint32_t inl(ioport_t port) |
static inline uint32_t pio_read_32(ioport_t port) |
{ |
uint32_t rv; |
/trunk/kernel/arch/ia64/include/asm.h |
---|
41,7 → 41,7 |
#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL |
static inline void outb(ioport_t port, uint8_t v) |
static inline void pio_write_8(ioport_t port, uint8_t v) |
{ |
*((uint8_t *)(IA64_IOSPACE_ADDRESS + |
((port & 0xfff) | ((port >> 2) << 12)))) = v; |
49,7 → 49,7 |
asm volatile ("mf\n" ::: "memory"); |
} |
static inline void outw(ioport_t port, uint16_t v) |
static inline void pio_write_16(ioport_t port, uint16_t v) |
{ |
*((uint16_t *)(IA64_IOSPACE_ADDRESS + |
((port & 0xfff) | ((port >> 2) << 12)))) = v; |
57,7 → 57,7 |
asm volatile ("mf\n" ::: "memory"); |
} |
static inline void outl(ioport_t port, uint32_t v) |
static inline void pio_write_32(ioport_t port, uint32_t v) |
{ |
*((uint32_t *)(IA64_IOSPACE_ADDRESS + |
((port & 0xfff) | ((port >> 2) << 12)))) = v; |
65,7 → 65,7 |
asm volatile ("mf\n" ::: "memory"); |
} |
static inline uint8_t inb(ioport_t port) |
static inline uint8_t pio_read_8(ioport_t port) |
{ |
asm volatile ("mf\n" ::: "memory"); |
73,7 → 73,7 |
((port & 0xfff) | ((port >> 2) << 12)))); |
} |
static inline uint16_t inw(ioport_t port) |
static inline uint16_t pio_read_16(ioport_t port) |
{ |
asm volatile ("mf\n" ::: "memory"); |
81,7 → 81,7 |
((port & 0xffE) | ((port >> 2) << 12)))); |
} |
static inline uint32_t inl(ioport_t port) |
static inline uint32_t pio_read_32(ioport_t port) |
{ |
asm volatile ("mf\n" ::: "memory"); |
/trunk/kernel/arch/ia64/include/drivers/i8042.h |
---|
47,22 → 47,22 |
static inline void i8042_data_write(uint8_t data) |
{ |
outb(i8042_DATA, data); |
pio_write_8(i8042_DATA, data); |
} |
static inline uint8_t i8042_data_read(void) |
{ |
return inb(i8042_DATA); |
return pio_read_8(i8042_DATA); |
} |
static inline uint8_t i8042_status_read(void) |
{ |
return inb(i8042_STATUS); |
return pio_read_8(i8042_STATUS); |
} |
static inline void i8042_command_write(uint8_t command) |
{ |
outb(i8042_STATUS, command); |
pio_write_8(i8042_STATUS, command); |
} |
#endif |
/trunk/kernel/arch/ia64/src/ia64.c |
---|
249,7 → 249,7 |
void arch_reboot(void) |
{ |
outb(0x64, 0xfe); |
pio_write_8(0x64, 0xfe); |
while (1) |
; |
} |
/trunk/kernel/arch/arm32/include/asm.h |
---|
46,15 → 46,14 |
{ |
} |
/** No I/O port address space on ARM. */ |
static inline void outb(ioport_t port, uint8_t v) |
static inline void pio_write_8(ioport_t port, uint8_t v) |
{ |
/* XXX */ |
} |
/** No I/O port address space on ARM. */ |
static inline uint8_t inb(ioport_t port) |
static inline uint8_t pio_read_8(ioport_t port) |
{ |
return 0; |
return 0; /* XXX */ |
} |
/** Return base address of current stack. |
/trunk/kernel/arch/ppc32/include/asm.h |
---|
149,15 → 149,14 |
extern void userspace_asm(uintptr_t uspace_uarg, uintptr_t stack, uintptr_t entry); |
/** No I/O port address space on PowerPC. */ |
static inline void outb(ioport_t port, uint8_t v) |
static inline void pio_write_8(ioport_t port, uint8_t v) |
{ |
/* XXX */ |
} |
/** No I/O port address space on PowerPC. */ |
static inline uint8_t inb(ioport_t port) |
static inline uint8_t pio_read_8(ioport_t port) |
{ |
return 0; |
return 0; /* XXX */ |
} |
#endif |
/trunk/kernel/arch/amd64/include/asm.h |
---|
73,7 → 73,7 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline uint8_t inb(uint16_t port) |
static inline uint8_t pio_read_8(uint16_t port) |
{ |
uint8_t val; |
88,7 → 88,7 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outb(uint16_t port, uint8_t val) |
static inline void pio_write_8(uint16_t port, uint8_t val) |
{ |
asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port)); |
} |
/trunk/kernel/arch/mips32/include/asm.h |
---|
70,15 → 70,14 |
extern void interrupts_restore(ipl_t ipl); |
extern ipl_t interrupts_read(void); |
/** No I/O port address space on MIPS. */ |
static inline void outb(ioport_t port, uint8_t v) |
static inline void pio_write_8(ioport_t port, uint8_t v) |
{ |
/* XXX */ |
} |
/** No I/O port address space on MIPS. */ |
static inline uint8_t inb(ioport_t port) |
static inline uint8_t pio_read_8(ioport_t port) |
{ |
return 0; |
return 0; /* XXX */ |
} |
#endif |
/trunk/kernel/arch/ia32/include/asm.h |
---|
105,7 → 105,7 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outb(uint16_t port, uint8_t val) |
static inline void pio_write_8(uint16_t port, uint8_t val) |
{ |
asm volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); |
} |
117,7 → 117,7 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outw(uint16_t port, uint16_t val) |
static inline void pio_write_16(uint16_t port, uint16_t val) |
{ |
asm volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); |
} |
129,7 → 129,7 |
* @param port Port to write to |
* @param val Value to write |
*/ |
static inline void outl(uint16_t port, uint32_t val) |
static inline void pio_write_32(uint16_t port, uint32_t val) |
{ |
asm volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); |
} |
141,7 → 141,7 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline uint8_t inb(uint16_t port) |
static inline uint8_t pio_read_8(uint16_t port) |
{ |
uint8_t val; |
156,7 → 156,7 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline uint16_t inw(uint16_t port) |
static inline uint16_t pio_read_16(uint16_t port) |
{ |
uint16_t val; |
171,7 → 171,7 |
* @param port Port to read from |
* @return Value read |
*/ |
static inline uint32_t inl(uint16_t port) |
static inline uint32_t pio_read_32(uint16_t port) |
{ |
uint32_t val; |
/trunk/kernel/arch/ia32/include/drivers/i8042.h |
---|
47,22 → 47,22 |
static inline void i8042_data_write(uint8_t data) |
{ |
outb(i8042_DATA, data); |
pio_write_8(i8042_DATA, data); |
} |
static inline uint8_t i8042_data_read(void) |
{ |
return inb(i8042_DATA); |
return pio_read_8(i8042_DATA); |
} |
static inline uint8_t i8042_status_read(void) |
{ |
return inb(i8042_STATUS); |
return pio_read_8(i8042_STATUS); |
} |
static inline void i8042_command_write(uint8_t command) |
{ |
outb(i8042_STATUS, command); |
pio_write_8(i8042_STATUS, command); |
} |
#endif |
/trunk/kernel/arch/ia32/src/smp/smp.c |
---|
122,8 → 122,8 |
* Save 0xa to address 0xf of the CMOS RAM. |
* BIOS will not do the POST after the INIT signal. |
*/ |
outb(0x70, 0xf); |
outb(0x71, 0xa); |
pio_write_8(0x70, 0xf); |
pio_write_8(0x71, 0xa); |
pic_disable_irqs(0xffff); |
apic_init(); |
/trunk/kernel/arch/ia32/src/drivers/i8259.c |
---|
49,28 → 49,28 |
void i8259_init(void) |
{ |
/* ICW1: this is ICW1, ICW4 to follow */ |
outb(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4); |
pio_write_8(PIC_PIC0PORT1, PIC_ICW1 | PIC_NEEDICW4); |
/* ICW2: IRQ 0 maps to INT IRQBASE */ |
outb(PIC_PIC0PORT2, IVT_IRQBASE); |
pio_write_8(PIC_PIC0PORT2, IVT_IRQBASE); |
/* ICW3: pic1 using IRQ IRQ_PIC1 */ |
outb(PIC_PIC0PORT2, 1 << IRQ_PIC1); |
pio_write_8(PIC_PIC0PORT2, 1 << IRQ_PIC1); |
/* ICW4: i8086 mode */ |
outb(PIC_PIC0PORT2, 1); |
pio_write_8(PIC_PIC0PORT2, 1); |
/* ICW1: ICW1, ICW4 to follow */ |
outb(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4); |
pio_write_8(PIC_PIC1PORT1, PIC_ICW1 | PIC_NEEDICW4); |
/* ICW2: IRQ 8 maps to INT (IVT_IRQBASE + 8) */ |
outb(PIC_PIC1PORT2, IVT_IRQBASE + 8); |
pio_write_8(PIC_PIC1PORT2, IVT_IRQBASE + 8); |
/* ICW3: pic1 is known as IRQ_PIC1 */ |
outb(PIC_PIC1PORT2, IRQ_PIC1); |
pio_write_8(PIC_PIC1PORT2, IRQ_PIC1); |
/* ICW4: i8086 mode */ |
outb(PIC_PIC1PORT2, 1); |
pio_write_8(PIC_PIC1PORT2, 1); |
/* |
* Register interrupt handler for the PIC spurious interrupt. |
94,12 → 94,12 |
uint8_t x; |
if (irqmask & 0xff) { |
x = inb(PIC_PIC0PORT2); |
outb(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff)))); |
x = pio_read_8(PIC_PIC0PORT2); |
pio_write_8(PIC_PIC0PORT2, (uint8_t) (x & (~(irqmask & 0xff)))); |
} |
if (irqmask >> 8) { |
x = inb(PIC_PIC1PORT2); |
outb(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8)))); |
x = pio_read_8(PIC_PIC1PORT2); |
pio_write_8(PIC_PIC1PORT2, (uint8_t) (x & (~(irqmask >> 8)))); |
} |
} |
108,19 → 108,19 |
uint8_t x; |
if (irqmask & 0xff) { |
x = inb(PIC_PIC0PORT2); |
outb(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff))); |
x = pio_read_8(PIC_PIC0PORT2); |
pio_write_8(PIC_PIC0PORT2, (uint8_t) (x | (irqmask & 0xff))); |
} |
if (irqmask >> 8) { |
x = inb(PIC_PIC1PORT2); |
outb(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8))); |
x = pio_read_8(PIC_PIC1PORT2); |
pio_write_8(PIC_PIC1PORT2, (uint8_t) (x | (irqmask >> 8))); |
} |
} |
void pic_eoi(void) |
{ |
outb(0x20, 0x20); |
outb(0xa0, 0x20); |
pio_write_8(0x20, 0x20); |
pio_write_8(0xa0, 0x20); |
} |
void pic_spurious(int n __attribute__((unused)), istate_t *istate __attribute__((unused))) |
/trunk/kernel/arch/ia32/src/drivers/i8254.c |
---|
94,10 → 94,10 |
void i8254_normal_operation(void) |
{ |
outb(CLK_PORT4, 0x36); |
pio_write_8(CLK_PORT4, 0x36); |
pic_disable_irqs(1 << IRQ_CLK); |
outb(CLK_PORT1, (CLK_CONST / HZ) & 0xf); |
outb(CLK_PORT1, (CLK_CONST / HZ) >> 8); |
pio_write_8(CLK_PORT1, (CLK_CONST / HZ) & 0xf); |
pio_write_8(CLK_PORT1, (CLK_CONST / HZ) >> 8); |
pic_enable_irqs(1 << IRQ_CLK); |
} |
114,36 → 114,36 |
* One-shot timer. Count-down from 0xffff at 1193180Hz |
* MAGIC_NUMBER is the magic value for 1ms. |
*/ |
outb(CLK_PORT4, 0x30); |
outb(CLK_PORT1, 0xff); |
outb(CLK_PORT1, 0xff); |
pio_write_8(CLK_PORT4, 0x30); |
pio_write_8(CLK_PORT1, 0xff); |
pio_write_8(CLK_PORT1, 0xff); |
do { |
/* will read both status and count */ |
outb(CLK_PORT4, 0xc2); |
not_ok = (uint8_t) ((inb(CLK_PORT1) >> 6) & 1); |
t1 = inb(CLK_PORT1); |
t1 |= inb(CLK_PORT1) << 8; |
pio_write_8(CLK_PORT4, 0xc2); |
not_ok = (uint8_t) ((pio_read_8(CLK_PORT1) >> 6) & 1); |
t1 = pio_read_8(CLK_PORT1); |
t1 |= pio_read_8(CLK_PORT1) << 8; |
} while (not_ok); |
asm_delay_loop(LOOPS); |
outb(CLK_PORT4, 0xd2); |
t2 = inb(CLK_PORT1); |
t2 |= inb(CLK_PORT1) << 8; |
pio_write_8(CLK_PORT4, 0xd2); |
t2 = pio_read_8(CLK_PORT1); |
t2 |= pio_read_8(CLK_PORT1) << 8; |
/* |
* We want to determine the overhead of the calibrating mechanism. |
*/ |
outb(CLK_PORT4, 0xd2); |
o1 = inb(CLK_PORT1); |
o1 |= inb(CLK_PORT1) << 8; |
pio_write_8(CLK_PORT4, 0xd2); |
o1 = pio_read_8(CLK_PORT1); |
o1 |= pio_read_8(CLK_PORT1) << 8; |
asm_fake_loop(LOOPS); |
outb(CLK_PORT4, 0xd2); |
o2 = inb(CLK_PORT1); |
o2 |= inb(CLK_PORT1) << 8; |
pio_write_8(CLK_PORT4, 0xd2); |
o2 = pio_read_8(CLK_PORT1); |
o2 |= pio_read_8(CLK_PORT1) << 8; |
CPU->delay_loop_const = |
((MAGIC_NUMBER * LOOPS) / 1000) / ((t1 - t2) - (o1 - o2)) + |