| /trunk/kernel/arch/xen32/include/pm.h |
|---|
| 1,0 → 0,0 |
| link ../../ia32/include/pm.h |
| /* |
| * Copyright (C) 2001-2004 Jakub Jermar |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup xen32 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef __PM_H__ |
| #define __PM_H__ |
| #define IDT_ITEMS 64 |
| #define GDT_ITEMS 7 |
| #define NULL_DES 0 |
| #define KTEXT_DES 1 |
| #define KDATA_DES 2 |
| #define UTEXT_DES 3 |
| #define UDATA_DES 4 |
| #define TSS_DES 5 |
| #define TLS_DES 6 /* Pointer to Thread-Local-Storage data */ |
| #define selector(des) ((des) << 3) |
| #define PL_KERNEL 1 |
| #define PL_USER 3 |
| #define AR_PRESENT (1<<7) |
| #define AR_DATA (2<<3) |
| #define AR_CODE (3<<3) |
| #define AR_WRITABLE (1<<1) |
| #define AR_INTERRUPT (0xe) |
| #define AR_TSS (0x9) |
| #define DPL_KERNEL (PL_KERNEL<<5) |
| #define DPL_USER (PL_USER<<5) |
| #define TSS_BASIC_SIZE 104 |
| #define TSS_IOMAP_SIZE (16*1024+1) /* 16K for bitmap + 1 terminating byte for convenience */ |
| #define IO_PORTS (64*1024) |
| #ifndef __ASM__ |
| #include <arch/types.h> |
| #include <typedefs.h> |
| #include <arch/context.h> |
| struct ptr_16_32 { |
| uint16_t limit; |
| uint32_t base; |
| } __attribute__ ((packed)); |
| typedef struct ptr_16_32 ptr_16_32_t; |
| struct descriptor { |
| unsigned limit_0_15: 16; |
| unsigned base_0_15: 16; |
| unsigned base_16_23: 8; |
| unsigned access: 8; |
| unsigned limit_16_19: 4; |
| unsigned available: 1; |
| unsigned unused: 1; |
| unsigned special: 1; |
| unsigned granularity : 1; |
| unsigned base_24_31: 8; |
| } __attribute__ ((packed)); |
| typedef struct descriptor descriptor_t; |
| struct idescriptor { |
| unsigned offset_0_15: 16; |
| unsigned selector: 16; |
| unsigned unused: 8; |
| unsigned access: 8; |
| unsigned offset_16_31: 16; |
| } __attribute__ ((packed)); |
| typedef struct idescriptor idescriptor_t; |
| struct tss { |
| uint16_t link; |
| unsigned : 16; |
| uint32_t esp0; |
| uint16_t ss0; |
| unsigned : 16; |
| uint32_t esp1; |
| uint16_t ss1; |
| unsigned : 16; |
| uint32_t esp2; |
| uint16_t ss2; |
| unsigned : 16; |
| uint32_t cr3; |
| uint32_t eip; |
| uint32_t eflags; |
| uint32_t eax; |
| uint32_t ecx; |
| uint32_t edx; |
| uint32_t ebx; |
| uint32_t esp; |
| uint32_t ebp; |
| uint32_t esi; |
| uint32_t edi; |
| uint16_t es; |
| unsigned : 16; |
| uint16_t cs; |
| unsigned : 16; |
| uint16_t ss; |
| unsigned : 16; |
| uint16_t ds; |
| unsigned : 16; |
| uint16_t fs; |
| unsigned : 16; |
| uint16_t gs; |
| unsigned : 16; |
| uint16_t ldtr; |
| unsigned : 16; |
| unsigned : 16; |
| uint16_t iomap_base; |
| uint8_t iomap[TSS_IOMAP_SIZE]; |
| } __attribute__ ((packed)); |
| typedef struct tss tss_t; |
| extern ptr_16_32_t gdtr; |
| extern ptr_16_32_t bootstrap_gdtr; |
| extern ptr_16_32_t protected_ap_gdtr; |
| extern struct tss *tss_p; |
| extern descriptor_t gdt[]; |
| extern void pm_init(void); |
| extern void gdt_setbase(descriptor_t *d, uintptr_t base); |
| extern void gdt_setlimit(descriptor_t *d, uint32_t limit); |
| extern void idt_init(void); |
| extern void idt_setoffset(idescriptor_t *d, uintptr_t offset); |
| extern void tss_initialize(tss_t *t); |
| extern void set_tls_desc(uintptr_t tls); |
| #endif /* __ASM__ */ |
| #endif |
| /** @} |
| */ |
| Property changes: |
| Deleted: svn:special |
| -* |
| \ No newline at end of property |
| /trunk/kernel/arch/xen32/include/asm.h |
|---|
| 1,0 → 0,0 |
| link ../../ia32/include/asm.h |
| /* |
| * Copyright (C) 2001-2004 Jakub Jermar |
| * Copyright (C) 2005 Sergey Bondari |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup xen32 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef __xen32_ASM_H__ |
| #define __xen32_ASM_H__ |
| #include <arch/pm.h> |
| #include <arch/types.h> |
| #include <config.h> |
| extern uint32_t interrupt_handler_size; |
| extern void paging_on(void); |
| extern void interrupt_handlers(void); |
| extern void enable_l_apic_in_msr(void); |
| extern void asm_delay_loop(uint32_t t); |
| extern void asm_fake_loop(uint32_t t); |
| /** Halt CPU |
| * |
| * Halt the current CPU until interrupt event. |
| */ |
| static inline void cpu_halt(void) { __asm__("hlt\n"); }; |
| static inline void cpu_sleep(void) { __asm__("hlt\n"); }; |
| #define GEN_READ_REG(reg) static inline unative_t read_ ##reg (void) \ |
| { \ |
| unative_t res; \ |
| __asm__ volatile ("movl %%" #reg ", %0" : "=r" (res) ); \ |
| return res; \ |
| } |
| #define GEN_WRITE_REG(reg) static inline void write_ ##reg (unative_t regn) \ |
| { \ |
| __asm__ volatile ("movl %0, %%" #reg : : "r" (regn)); \ |
| } |
| GEN_READ_REG(cr0); |
| GEN_READ_REG(cr2); |
| GEN_READ_REG(cr3); |
| GEN_WRITE_REG(cr3); |
| GEN_READ_REG(dr0); |
| GEN_READ_REG(dr1); |
| GEN_READ_REG(dr2); |
| GEN_READ_REG(dr3); |
| GEN_READ_REG(dr6); |
| GEN_READ_REG(dr7); |
| GEN_WRITE_REG(dr0); |
| GEN_WRITE_REG(dr1); |
| GEN_WRITE_REG(dr2); |
| GEN_WRITE_REG(dr3); |
| GEN_WRITE_REG(dr6); |
| GEN_WRITE_REG(dr7); |
| /** Byte to port |
| * |
| * Output byte to port |
| * |
| * @param port Port to write to |
| * @param val Value to write |
| */ |
| static inline void outb(uint16_t port, uint8_t val) { __asm__ volatile ("outb %b0, %w1\n" : : "a" (val), "d" (port) ); } |
| /** Word to port |
| * |
| * Output word to port |
| * |
| * @param port Port to write to |
| * @param val Value to write |
| */ |
| static inline void outw(uint16_t port, uint16_t val) { __asm__ volatile ("outw %w0, %w1\n" : : "a" (val), "d" (port) ); } |
| /** Double word to port |
| * |
| * Output double word to port |
| * |
| * @param port Port to write to |
| * @param val Value to write |
| */ |
| static inline void outl(uint16_t port, uint32_t val) { __asm__ volatile ("outl %l0, %w1\n" : : "a" (val), "d" (port) ); } |
| /** Byte from port |
| * |
| * Get byte from port |
| * |
| * @param port Port to read from |
| * @return Value read |
| */ |
| static inline uint8_t inb(uint16_t port) { uint8_t val; __asm__ volatile ("inb %w1, %b0 \n" : "=a" (val) : "d" (port) ); return val; } |
| /** Word from port |
| * |
| * Get word from port |
| * |
| * @param port Port to read from |
| * @return Value read |
| */ |
| static inline uint16_t inw(uint16_t port) { uint16_t val; __asm__ volatile ("inw %w1, %w0 \n" : "=a" (val) : "d" (port) ); return val; } |
| /** Double word from port |
| * |
| * Get double word from port |
| * |
| * @param port Port to read from |
| * @return Value read |
| */ |
| static inline uint32_t inl(uint16_t port) { uint32_t val; __asm__ volatile ("inl %w1, %l0 \n" : "=a" (val) : "d" (port) ); return val; } |
| /** Enable interrupts. |
| * |
| * Enable interrupts and return previous |
| * value of EFLAGS. |
| * |
| * @return Old interrupt priority level. |
| */ |
| static inline ipl_t interrupts_enable(void) |
| { |
| ipl_t v; |
| __asm__ volatile ( |
| "pushf\n\t" |
| "popl %0\n\t" |
| "sti\n" |
| : "=r" (v) |
| ); |
| return v; |
| } |
| /** Disable interrupts. |
| * |
| * Disable interrupts and return previous |
| * value of EFLAGS. |
| * |
| * @return Old interrupt priority level. |
| */ |
| static inline ipl_t interrupts_disable(void) |
| { |
| ipl_t v; |
| __asm__ volatile ( |
| "pushf\n\t" |
| "popl %0\n\t" |
| "cli\n" |
| : "=r" (v) |
| ); |
| return v; |
| } |
| /** Restore interrupt priority level. |
| * |
| * Restore EFLAGS. |
| * |
| * @param ipl Saved interrupt priority level. |
| */ |
| static inline void interrupts_restore(ipl_t ipl) |
| { |
| __asm__ volatile ( |
| "pushl %0\n\t" |
| "popf\n" |
| : : "r" (ipl) |
| ); |
| } |
| /** Return interrupt priority level. |
| * |
| * @return EFLAFS. |
| */ |
| static inline ipl_t interrupts_read(void) |
| { |
| ipl_t v; |
| __asm__ volatile ( |
| "pushf\n\t" |
| "popl %0\n" |
| : "=r" (v) |
| ); |
| return v; |
| } |
| /** Return base address of current stack |
| * |
| * Return the base address of the current stack. |
| * The stack is assumed to be STACK_SIZE bytes long. |
| * The stack must start on page boundary. |
| */ |
| static inline uintptr_t get_stack_base(void) |
| { |
| uintptr_t v; |
| __asm__ volatile ("andl %%esp, %0\n" : "=r" (v) : "0" (~(STACK_SIZE-1))); |
| return v; |
| } |
| static inline uint64_t rdtsc(void) |
| { |
| uint64_t v; |
| __asm__ volatile("rdtsc\n" : "=A" (v)); |
| return v; |
| } |
| /** Return current IP address */ |
| static inline uintptr_t * get_ip() |
| { |
| uintptr_t *ip; |
| __asm__ volatile ( |
| "mov %%eip, %0" |
| : "=r" (ip) |
| ); |
| return ip; |
| } |
| /** Invalidate TLB Entry. |
| * |
| * @param addr Address on a page whose TLB entry is to be invalidated. |
| */ |
| static inline void invlpg(uintptr_t addr) |
| { |
| __asm__ volatile ("invlpg %0\n" :: "m" (*(unative_t *)addr)); |
| } |
| /** Load GDTR register from memory. |
| * |
| * @param gdtr_reg Address of memory from where to load GDTR. |
| */ |
| static inline void gdtr_load(ptr_16_32_t *gdtr_reg) |
| { |
| __asm__ volatile ("lgdtl %0\n" : : "m" (*gdtr_reg)); |
| } |
| /** Store GDTR register to memory. |
| * |
| * @param gdtr_reg Address of memory to where to load GDTR. |
| */ |
| static inline void gdtr_store(ptr_16_32_t *gdtr_reg) |
| { |
| __asm__ volatile ("sgdtl %0\n" : : "m" (*gdtr_reg)); |
| } |
| /** Load IDTR register from memory. |
| * |
| * @param idtr_reg Address of memory from where to load IDTR. |
| */ |
| static inline void idtr_load(ptr_16_32_t *idtr_reg) |
| { |
| __asm__ volatile ("lidtl %0\n" : : "m" (*idtr_reg)); |
| } |
| /** Load TR from descriptor table. |
| * |
| * @param sel Selector specifying descriptor of TSS segment. |
| */ |
| static inline void tr_load(uint16_t sel) |
| { |
| __asm__ volatile ("ltr %0" : : "r" (sel)); |
| } |
| #endif |
| /** @} |
| */ |
| Property changes: |
| Deleted: svn:special |
| -* |
| \ No newline at end of property |
| /trunk/kernel/arch/xen32/include/hypercall.h |
|---|
| 30,7 → 30,19 |
| #define __xen32_HYPERCALL_H__ |
| #include <arch/types.h> |
| #include <macros.h> |
| #define XEN_CONSOLE_IO 18 |
| /* |
| * Commands for XEN_CONSOLE_IO |
| */ |
| #define CONSOLE_IO_WRITE 0 |
| #define CONSOLE_IO_READ 1 |
| #define hypercall0(id) \ |
| ({ \ |
| unative_t ret; \ |
| 82,7 → 94,7 |
| "=d" (__ign3) \ |
| : "1" (p1), \ |
| "2" (p2), \ |
| "3" (p3), \ |
| "3" (p3) \ |
| : "memory" \ |
| ); \ |
| ret; \ |
| 101,7 → 113,7 |
| : "1" (p1), \ |
| "2" (p2), \ |
| "3" (p3), \ |
| "4" (p4), \ |
| "4" (p4) \ |
| : "memory" \ |
| ); \ |
| ret; \ |
| 109,7 → 121,7 |
| #define hypercall5(id, p1, p2, p3, p4, p5) \ |
| ({ \ |
| unative_t ret, __ign1, __ign2, __ign3, __ign4, __ing5; \ |
| unative_t ret, __ign1, __ign2, __ign3, __ign4, __ign5; \ |
| asm volatile ( \ |
| "call hypercall_page + (" STRING(id) " * 32)\n" \ |
| : "=a" (ret), \ |
| 122,7 → 134,7 |
| "2" (p2), \ |
| "3" (p3), \ |
| "4" (p4), \ |
| "5" (p5), \ |
| "5" (p5) \ |
| : "memory" \ |
| ); \ |
| ret; \ |
| 129,7 → 141,7 |
| }) |
| static inline int xen_console_io(int cmd, int count, char *str) |
| static inline int xen_console_io(const int cmd, const int count, const char *str) |
| { |
| return hypercall3(XEN_CONSOLE_IO, cmd, count, str); |
| } |
| /trunk/kernel/arch/xen32/include/drivers/xconsole.h |
|---|
| 0,0 → 1,43 |
| /* |
| * Copyright (C) 2006 Martin Decky |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions |
| * are met: |
| * |
| * - Redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer. |
| * - Redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution. |
| * - The name of the author may not be used to endorse or promote products |
| * derived from this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| /** @addtogroup xen32 |
| * @{ |
| */ |
| /** @file |
| */ |
| #ifndef __XCONSOLE_H__ |
| #define __XCONSOLE_H__ |
| extern void xen_console_init(void); |
| #endif |
| /** @} |
| */ |