/trunk/kernel/arch/sparc64/include/regdef.h |
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35,25 → 35,25 |
#ifndef KERN_sparc64_REGDEF_H_ |
#define KERN_sparc64_REGDEF_H_ |
#define PSTATE_IE_BIT (1<<1) |
#define PSTATE_AM_BIT (1<<3) |
#define PSTATE_IE_BIT (1 << 1) |
#define PSTATE_AM_BIT (1 << 3) |
#define PSTATE_AG_BIT (1<<0) |
#define PSTATE_IG_BIT (1<<11) |
#define PSTATE_MG_BIT (1<<10) |
#define PSTATE_AG_BIT (1 << 0) |
#define PSTATE_IG_BIT (1 << 11) |
#define PSTATE_MG_BIT (1 << 10) |
#define PSTATE_PRIV_BIT (1<<2) |
#define PSTATE_PEF_BIT (1<<4) |
#define PSTATE_PRIV_BIT (1 << 2) |
#define PSTATE_PEF_BIT (1 << 4) |
#define TSTATE_PSTATE_SHIFT 8 |
#define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT<<TSTATE_PSTATE_SHIFT) |
#define TSTATE_IE_BIT (PSTATE_IE_BIT<<TSTATE_PSTATE_SHIFT) |
#define TSTATE_PEF_BIT (PSTATE_PEF_BIT<<TSTATE_PSTATE_SHIFT) |
#define TSTATE_PRIV_BIT (PSTATE_PRIV_BIT << TSTATE_PSTATE_SHIFT) |
#define TSTATE_IE_BIT (PSTATE_IE_BIT << TSTATE_PSTATE_SHIFT) |
#define TSTATE_PEF_BIT (PSTATE_PEF_BIT << TSTATE_PSTATE_SHIFT) |
#define TSTATE_CWP_MASK 0x1f |
#define WSTATE_NORMAL(n) (n) |
#define WSTATE_OTHER(n) ((n)<<3) |
#define WSTATE_OTHER(n) ((n) << 3) |
#define UPA_CONFIG_MID_SHIFT 17 |
#define UPA_CONFIG_MID_MASK 0x1f |
/trunk/kernel/arch/sparc64/include/asm.h |
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265,41 → 265,41 |
return v; |
} |
/** Read Trap Base Address register. |
/** Read Trap Program Counter register. |
* |
* @return Current value in TBA. |
* @return Current value in TPC. |
*/ |
static inline uint64_t tba_read(void) |
static inline uint64_t tpc_read(void) |
{ |
uint64_t v; |
__asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
__asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
return v; |
} |
/** Read Trap Program Counter register. |
/** Read Trap Level register. |
* |
* @return Current value in TPC. |
* @return Current value in TL. |
*/ |
static inline uint64_t tpc_read(void) |
static inline uint64_t tl_read(void) |
{ |
uint64_t v; |
__asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v)); |
__asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
return v; |
} |
/** Read Trap Level register. |
/** Read Trap Base Address register. |
* |
* @return Current value in TL. |
* @return Current value in TBA. |
*/ |
static inline uint64_t tl_read(void) |
static inline uint64_t tba_read(void) |
{ |
uint64_t v; |
__asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v)); |
__asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v)); |
return v; |
} |
/trunk/kernel/arch/sparc64/include/trap/syscall.h |
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39,7 → 39,7 |
#ifndef KERN_sparc64_SYSCALL_TRAP_H_ |
#define KERN_sparc64_SYSCALL_TRAP_H_ |
#define TT_TRAP_INSTRUCTION(n) (0x100+(n)) |
#define TT_TRAP_INSTRUCTION(n) (0x100 + (n)) |
#define TT_TRAP_INSTRUCTION_LAST TT_TRAP_INSTRUCTION(127) |
#ifdef __ASM__ |
/trunk/kernel/arch/sparc64/include/trap/interrupt.h |
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43,7 → 43,7 |
/* IMAP register bits */ |
#define IGN_MASK 0x7c0 |
#define INO_MASK 0x1f |
#define IMAP_V_MASK (1ULL<<31) |
#define IMAP_V_MASK (1ULL << 31) |
#define IGN_SHIFT 6 |
/trunk/kernel/arch/sparc64/include/trap/trap_table.h |
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39,7 → 39,7 |
#define TRAP_TABLE_ENTRY_COUNT 1024 |
#define TRAP_TABLE_ENTRY_SIZE 32 |
#define TRAP_TABLE_SIZE (TRAP_TABLE_ENTRY_COUNT*TRAP_TABLE_ENTRY_SIZE) |
#define TRAP_TABLE_SIZE (TRAP_TABLE_ENTRY_COUNT * TRAP_TABLE_ENTRY_SIZE) |
#ifndef __ASM__ |
/trunk/kernel/arch/sparc64/include/mm/frame.h |
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36,7 → 36,7 |
#define KERN_sparc64_FRAME_H_ |
#define FRAME_WIDTH 13 /* 8K */ |
#define FRAME_SIZE (1<<FRAME_WIDTH) |
#define FRAME_SIZE (1 << FRAME_WIDTH) |
#ifdef KERNEL |
#ifndef __ASM__ |
/trunk/kernel/arch/sparc64/include/debug.h |
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1,5 → 1,5 |
/* |
* Copyright (C) 2005 |
* Copyright (C) 2005 Jakub Jermar |
* All rights reserved. |
* |
* Redistribution and use in source and binary forms, with or without |