39,15 → 39,6 |
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void fpu_context_save(fpu_context_t *fctx) |
{ |
fprs_reg_t fprs; |
|
fprs.value = fprs_read(); |
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if (fprs.dl) { |
/* |
* The lower half of floating-point registers is dirty. |
* Spill it to memory. |
*/ |
__asm__ volatile ( |
"std %%f0, %0\n" |
"std %%f2, %1\n" |
70,14 → 61,12 |
"=m" (fctx->d[8]), "=m" (fctx->d[9]), "=m" (fctx->d[10]), "=m" (fctx->d[11]), |
"=m" (fctx->d[12]), "=m" (fctx->d[13]), "=m" (fctx->d[14]), "=m" (fctx->d[15]) |
); |
fprs.dl = false; |
} |
|
if (fprs.du) { |
/* |
* The upper half of floating-point registers is dirty. |
* Spill it to memory. |
* We need to split loading of the floating-point registers because |
* GCC (4.1.1) can't handle more than 30 operands in one asm statement. |
*/ |
|
__asm__ volatile ( |
"std %%f32, %0\n" |
"std %%f34, %1\n" |
100,20 → 89,12 |
"=m" (fctx->d[24]), "=m" (fctx->d[25]), "=m" (fctx->d[26]), "=m" (fctx->d[27]), |
"=m" (fctx->d[28]), "=m" (fctx->d[29]), "=m" (fctx->d[30]), "=m" (fctx->d[31]) |
); |
fprs.du = false; |
} |
|
fprs_write(fprs.value); |
|
__asm__ volatile ("stx %%fsr, %0\n" : "=m" (fctx->fsr)); |
} |
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void fpu_context_restore(fpu_context_t *fctx) |
{ |
fprs_reg_t fprs; |
|
fprs.value = fprs_read(); |
|
__asm__ volatile ( |
"ldd %0, %%f0\n" |
"ldd %1, %%f2\n" |
167,9 → 148,6 |
"m" (fctx->d[28]), "m" (fctx->d[29]), "m" (fctx->d[30]), "m" (fctx->d[31]) |
); |
|
fprs.dl = fprs.du = false; |
fprs_write(fprs.value); |
|
__asm__ volatile ("ldx %0, %%fsr\n" : : "m" (fctx->fsr)); |
} |
|