/trunk/kernel/arch/sparc64/src/mm/tlb.c |
---|
111,7 → 111,9 |
data.pfn = fr.pfn; |
data.l = locked; |
data.cp = cacheable; |
#ifdef CONFIG_VIRT_IDX_CACHE |
data.cv = cacheable; |
#endif /* CONFIG_VIRT_IDX_CACHE */ |
data.p = true; |
data.w = true; |
data.g = false; |
146,7 → 148,9 |
data.pfn = fr.pfn; |
data.l = false; |
data.cp = t->c; |
#ifdef CONFIG_VIRT_IDX_CACHE |
data.cv = t->c; |
#endif /* CONFIG_VIRT_IDX_CACHE */ |
data.p = t->k; /* p like privileged */ |
data.w = ro ? false : t->w; |
data.g = t->g; |
180,7 → 184,9 |
data.pfn = fr.pfn; |
data.l = false; |
data.cp = t->c; |
#ifdef CONFIG_VIRT_IDX_CACHE |
data.cv = t->c; |
#endif /* CONFIG_VIRT_IDX_CACHE */ |
data.p = t->k; /* p like privileged */ |
data.w = false; |
data.g = t->g; |
/trunk/kernel/arch/sparc64/src/mm/tsb.c |
---|
100,7 → 100,9 |
tsb->data.size = PAGESIZE_8K; |
tsb->data.pfn = t->frame >> PAGE_WIDTH; |
tsb->data.cp = t->c; |
#ifdef CONFIG_VIRT_IDX_CACHE |
tsb->data.cv = t->c; |
#endif /* CONFIG_VIRT_IDX_CACHE */ |
tsb->data.p = t->k; /* p as privileged */ |
tsb->data.v = t->p; |
140,7 → 142,9 |
tsb->data.size = PAGESIZE_8K; |
tsb->data.pfn = t->frame >> PAGE_WIDTH; |
tsb->data.cp = t->c; |
#ifdef CONFIG_VIRT_IDX_CACHE |
tsb->data.cv = t->c; |
#endif /* CONFIG_VIRT_IDX_CACHE */ |
tsb->data.p = t->k; /* p as privileged */ |
tsb->data.w = ro ? false : t->w; |
tsb->data.v = t->p; |