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Compare Revisions

• This comparison shows the changes necessary to convert path

  → /trunk/kernel/arch/sparc64/src/mm/ @ 1859

  → /trunk/kernel/arch/sparc64/src/mm/ @ 1860

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 1859 → Rev 1860

/trunk/kernel/arch/sparc64/src/mm/tlb.c
374,9 → 374,16
*/
void tlb_invalidate_asid(asid_t asid)
{
/* TODO: write asid to some Context register and encode the register in second parameter below. */
itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, 0);
tlb_context_reg_t sc_save, ctx;
ctx.v = sc_save.v = mmu_secondary_context_read();
ctx.context = asid;
mmu_secondary_context_write(ctx.v);
itlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_SECONDARY, 0);
dtlb_demap(TLB_DEMAP_CONTEXT, TLB_DEMAP_SECONDARY, 0);
mmu_secondary_context_write(sc_save.v);
}
/** Invalidate all ITLB and DTLB entries for specified page range in specified address space.
388,12 → 395,18
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
int i;
tlb_context_reg_t sc_save, ctx;
ctx.v = sc_save.v = mmu_secondary_context_read();
ctx.context = asid;
mmu_secondary_context_write(ctx.v);
for (i = 0; i < cnt; i++) {
/* TODO: write asid to some Context register and encode the register in second parameter below. */
itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, page + i * PAGE_SIZE);
itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, page + i * PAGE_SIZE);
dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, page + i * PAGE_SIZE);
}
mmu_secondary_context_write(sc_save.v);
}
/** @}

/trunk/kernel/arch/sparc64/src/mm/as.c
26,7 → 26,7
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/** @addtogroup sparc64mm
/** @addtogroup sparc64mm
* @{
*/
/** @file
33,6 → 33,7
*/
#include <arch/mm/as.h>
#include <arch/mm/tlb.h>
#include <genarch/mm/as_ht.h>
#include <genarch/mm/asid_fifo.h>
43,6 → 44,22
asid_fifo_init();
}
/** @}
void as_install_arch(as_t *as)
{
tlb_context_reg_t ctx;
/*
* Write ASID to secondary context register.
* The primary context register has to be set
* from TL>0 so it will be filled from the
* secondary context register from the TL=1
* code just before switch to userspace.
*/
ctx.v = 0;
ctx.context = as->asid;
mmu_secondary_context_write(ctx.v);
}
/** @}
*/